WO1998048570A3 - Synchronization of multiple video and graphic sources with a display using a slow pll approach - Google Patents

Synchronization of multiple video and graphic sources with a display using a slow pll approach Download PDF

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Publication number
WO1998048570A3
WO1998048570A3 PCT/IB1998/000543 IB9800543W WO9848570A3 WO 1998048570 A3 WO1998048570 A3 WO 1998048570A3 IB 9800543 W IB9800543 W IB 9800543W WO 9848570 A3 WO9848570 A3 WO 9848570A3
Authority
WO
WIPO (PCT)
Prior art keywords
synchronization
display
source
displays
slow
Prior art date
Application number
PCT/IB1998/000543
Other languages
French (fr)
Other versions
WO1998048570A2 (en
Inventor
John E Dean
Richard C Shen
Alan P Cavallerano
Original Assignee
Koninkl Philips Electronics Nv
Philips Svenska Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv, Philips Svenska Ab filed Critical Koninkl Philips Electronics Nv
Priority to JP52939898A priority Critical patent/JP3902667B2/en
Priority to EP98910930A priority patent/EP0913053B1/en
Publication of WO1998048570A2 publication Critical patent/WO1998048570A2/en
Publication of WO1998048570A3 publication Critical patent/WO1998048570A3/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/06—Generation of synchronising signals
    • H04N5/067—Arrangements or circuits at the transmitter end
    • H04N5/073—Arrangements or circuits at the transmitter end for mutually locking plural sources of synchronising signals, e.g. studios or relay stations
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/445—Receiver circuitry for the reception of television signals according to analogue transmission standards for displaying additional information
    • H04N5/45—Picture in picture, e.g. displaying simultaneously another television channel in a region of the screen
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/12—Devices in which the synchronising signals are only operative if a phase difference occurs between synchronising and synchronised scanning devices, e.g. flywheel synchronising
    • H04N5/126—Devices in which the synchronising signals are only operative if a phase difference occurs between synchronising and synchronised scanning devices, e.g. flywheel synchronising whereby the synchronisation signal indirectly commands a frequency generator

Abstract

A slow Phase Locked Loop (PLL) is utilized to prevent an abrupt change to a video display containing multiple images when the source of the synchronization is changed. Such displays include Picture in Picture (PIP) television systems and computer displays. By appropriate buffering and memory management, visual disruptions can be minimized by slowly synchronizing the display synchronization signals to the new synchronization source. The slow synchronization also produces a less disruptive visual image when the source, or channel, of a single image display is changed, and allows for smooth visual transitions on displays having inertial elements, such as color wheels.
PCT/IB1998/000543 1997-04-21 1998-04-09 Synchronization of multiple video and graphic sources with a display using a slow pll approach WO1998048570A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP52939898A JP3902667B2 (en) 1997-04-21 1998-04-09 Synchronizing multiple video and graphics sources to a display using a slow PLL approach
EP98910930A EP0913053B1 (en) 1997-04-21 1998-04-09 Synchronization of multiple video and graphic sources with a display using a slow pll approach

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/843,807 1997-04-21
US08/843,807 US5914757A (en) 1997-04-21 1997-04-21 Synchronization of multiple video and graphic sources with a display using a slow PLL approach

Publications (2)

Publication Number Publication Date
WO1998048570A2 WO1998048570A2 (en) 1998-10-29
WO1998048570A3 true WO1998048570A3 (en) 1999-01-28

Family

ID=25291062

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB1998/000543 WO1998048570A2 (en) 1997-04-21 1998-04-09 Synchronization of multiple video and graphic sources with a display using a slow pll approach

Country Status (4)

Country Link
US (1) US5914757A (en)
EP (1) EP0913053B1 (en)
JP (1) JP3902667B2 (en)
WO (1) WO1998048570A2 (en)

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Also Published As

Publication number Publication date
JP2000513169A (en) 2000-10-03
JP3902667B2 (en) 2007-04-11
US5914757A (en) 1999-06-22
EP0913053B1 (en) 2011-06-15
EP0913053A2 (en) 1999-05-06
WO1998048570A2 (en) 1998-10-29

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