WO1998048449A3 - Flip chip and chip scale package - Google Patents

Flip chip and chip scale package Download PDF

Info

Publication number
WO1998048449A3
WO1998048449A3 PCT/US1998/008008 US9808008W WO9848449A3 WO 1998048449 A3 WO1998048449 A3 WO 1998048449A3 US 9808008 W US9808008 W US 9808008W WO 9848449 A3 WO9848449 A3 WO 9848449A3
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
bumps
chip
conductive
scale package
Prior art date
Application number
PCT/US1998/008008
Other languages
French (fr)
Other versions
WO1998048449A2 (en
Inventor
Peter Elenius
Roger Malmrose
Original Assignee
Flip Chip Technologies L L C
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Flip Chip Technologies L L C filed Critical Flip Chip Technologies L L C
Publication of WO1998048449A2 publication Critical patent/WO1998048449A2/en
Publication of WO1998048449A3 publication Critical patent/WO1998048449A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

A chip scale package assembly includes an integrated circuit die (1) having a number of input/output pads formed about the periphery thereof. An array of contact pads are disposed interior of the periphery of such die, each contact pad being coupled by conductive trace to one of the input/output pads. A first set of conductive bumps (5) are formed upon the contact pads. A substrate (201) includes a plurality of conductive vias (210) extending therethrough and aligned with the first set of bumps. A first surface of the substrate lies adjacent the first set of bumps for allowing the conductive vias to be affixed thereto. A second set of conductive bumps (219) is formed on the opposing second surface of the substrate for attachment to a circuit. An underfill (220) may be applied to fill the gap (221) between the integrated circuit die and the substrate.
PCT/US1998/008008 1997-04-21 1998-04-21 Flip chip and chip scale package WO1998048449A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US83764497A 1997-04-21 1997-04-21
US08/837,644 1997-04-21

Publications (2)

Publication Number Publication Date
WO1998048449A2 WO1998048449A2 (en) 1998-10-29
WO1998048449A3 true WO1998048449A3 (en) 1999-03-18

Family

ID=25275043

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1998/008008 WO1998048449A2 (en) 1997-04-21 1998-04-21 Flip chip and chip scale package

Country Status (1)

Country Link
WO (1) WO1998048449A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6333209B1 (en) * 1999-04-29 2001-12-25 International Business Machines Corporation One step method for curing and joining BGA solder balls
SG114508A1 (en) 2001-11-02 2005-09-28 Inst Of Microelectronics Enhanced chip scale package for wire bonds dies
US9257763B2 (en) 2013-07-02 2016-02-09 Gyrus Acmi, Inc. Hybrid interconnect
US9510739B2 (en) 2013-07-12 2016-12-06 Gyrus Acmi, Inc. Endoscope small imaging system

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4948754A (en) * 1987-09-02 1990-08-14 Nippondenso Co., Ltd. Method for making a semiconductor device
US5471096A (en) * 1991-08-16 1995-11-28 International Business Machines Corporation Solder interconnection from a composition containing a mixture of dicyanates
US5637920A (en) * 1995-10-04 1997-06-10 Lsi Logic Corporation High contact density ball grid array package for flip-chips
US5640051A (en) * 1993-12-13 1997-06-17 Matsushita Electric Industrial Co., Ltd. Chip package, a chip carrier, a terminal electrode for a circuit substrate and a chip package-mounted complex
US5705858A (en) * 1993-04-14 1998-01-06 Nec Corporation Packaging structure for a hermetically sealed flip chip semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4948754A (en) * 1987-09-02 1990-08-14 Nippondenso Co., Ltd. Method for making a semiconductor device
US5471096A (en) * 1991-08-16 1995-11-28 International Business Machines Corporation Solder interconnection from a composition containing a mixture of dicyanates
US5705858A (en) * 1993-04-14 1998-01-06 Nec Corporation Packaging structure for a hermetically sealed flip chip semiconductor device
US5640051A (en) * 1993-12-13 1997-06-17 Matsushita Electric Industrial Co., Ltd. Chip package, a chip carrier, a terminal electrode for a circuit substrate and a chip package-mounted complex
US5637920A (en) * 1995-10-04 1997-06-10 Lsi Logic Corporation High contact density ball grid array package for flip-chips

Also Published As

Publication number Publication date
WO1998048449A2 (en) 1998-10-29

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