WO1998038771A3 - Flow control in switches - Google Patents

Flow control in switches Download PDF

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Publication number
WO1998038771A3
WO1998038771A3 PCT/SE1998/000355 SE9800355W WO9838771A3 WO 1998038771 A3 WO1998038771 A3 WO 1998038771A3 SE 9800355 W SE9800355 W SE 9800355W WO 9838771 A3 WO9838771 A3 WO 9838771A3
Authority
WO
WIPO (PCT)
Prior art keywords
selector
buffers
flow control
data packets
ingress
Prior art date
Application number
PCT/SE1998/000355
Other languages
French (fr)
Other versions
WO1998038771A2 (en
Inventor
Krzysztof Kaminski
Original Assignee
Ericsson Telefon Ab L M
Krzysztof Kaminski
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M, Krzysztof Kaminski filed Critical Ericsson Telefon Ab L M
Priority to AU66427/98A priority Critical patent/AU6642798A/en
Publication of WO1998038771A2 publication Critical patent/WO1998038771A2/en
Publication of WO1998038771A3 publication Critical patent/WO1998038771A3/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3081—ATM peripheral units, e.g. policing, insertion or extraction
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/20—Support for services
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding in a switch fabric
    • H04L49/253—Routing or path finding in a switch fabric using establishment or release of connections between ports
    • H04L49/254—Centralised controller, i.e. arbitration or scheduling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5651—Priority, marking, classes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5679—Arbitration or scheduling

Abstract

The present invention relates to a method of controlling the flow of data packets in a switching unit that includes a number of ingress-selector stages (11, 12, ..., 1n), a number of egress-selector stages (21, 22, ..., 2n), a selector core (3), a number of queue buffers (111, 112, ..., 11n) related to respective ingress-selector stages, a number of output buffers (21B, 22B, ..., 2nB) of which at least one is related to a respective egress-selector stage, and a flow control unit (4). Information-carrying data packets can be stored temporarily in queue buffers (111) related to an ingress-selector stage (11), whereafter these data packets can be transferred to and thereafter stored in one of the output buffers (21B) via the selector core (3). The flow control unit (4) functions to control the data packet flow between the queue buffers (111, 112, ..., 11n) and the output buffers (21B, 22B, ..., 2nB). This control is achieved by allowing the transfer of data packets between the queue buffers (111, 112, ..., 11n) and the output buffers (21B, 22B,..., 2nB) solely in response to the issuance of an order from the flow control unit (4), and totally in accord with said order. The present invention also relates to a switching unit which is adapted to function in accordance with the inventive method.
PCT/SE1998/000355 1997-02-27 1998-02-27 Flow control in switches WO1998038771A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU66427/98A AU6642798A (en) 1997-02-27 1998-02-27 A control method for a switching unit and a switching unit adapted to function in accordance with the method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9700714-0 1997-02-27
SE9700714A SE9700714L (en) 1997-02-27 1997-02-27 Method of controlling the data packet flow in a switch unit and a switch unit adapted to operate according to the method

Publications (2)

Publication Number Publication Date
WO1998038771A2 WO1998038771A2 (en) 1998-09-03
WO1998038771A3 true WO1998038771A3 (en) 1998-12-03

Family

ID=20405963

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/SE1998/000355 WO1998038771A2 (en) 1997-02-27 1998-02-27 Flow control in switches

Country Status (3)

Country Link
AU (1) AU6642798A (en)
SE (1) SE9700714L (en)
WO (1) WO1998038771A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FI972040A (en) 1997-05-13 1998-11-14 Nokia Telecommunications Oy Method for packet-switched data transmission
KR100333250B1 (en) 1998-10-05 2002-05-17 가나이 쓰토무 Packet forwarding apparatus with a flow detection table

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4475192A (en) * 1982-02-16 1984-10-02 At&T Bell Laboratories Data packet flow control scheme for switching networks
US4616359A (en) * 1983-12-19 1986-10-07 At&T Bell Laboratories Adaptive preferential flow control for packet switching system
EP0249035A2 (en) * 1986-06-13 1987-12-16 International Business Machines Corporation Adaptive session-level pacing
EP0603916A2 (en) * 1992-12-25 1994-06-29 Nec Corporation Packet switching system using idle/busy status of output buffers
US5511070A (en) * 1992-05-20 1996-04-23 Xerox Corporation Reservation ring mechanism for controlling contention in a broadband ISDN fast packet switch suitable for use in a local area network
US5517495A (en) * 1994-12-06 1996-05-14 At&T Corp. Fair prioritized scheduling in an input-buffered switch
EP0715436A2 (en) * 1994-12-02 1996-06-05 AT&T Corp. ATM buffer memory priority controller
EP0719012A2 (en) * 1994-12-19 1996-06-26 Alcatel Data Networks Traffic management and congestion control for packet-based network
US5535197A (en) * 1991-09-26 1996-07-09 Ipc Information Systems, Inc. Shared buffer switching module
US5550815A (en) * 1994-12-30 1996-08-27 Lucent Technologies Inc. Apparatus and method for reducing data losses in a growable packet switch

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4475192A (en) * 1982-02-16 1984-10-02 At&T Bell Laboratories Data packet flow control scheme for switching networks
US4616359A (en) * 1983-12-19 1986-10-07 At&T Bell Laboratories Adaptive preferential flow control for packet switching system
EP0249035A2 (en) * 1986-06-13 1987-12-16 International Business Machines Corporation Adaptive session-level pacing
US5535197A (en) * 1991-09-26 1996-07-09 Ipc Information Systems, Inc. Shared buffer switching module
US5511070A (en) * 1992-05-20 1996-04-23 Xerox Corporation Reservation ring mechanism for controlling contention in a broadband ISDN fast packet switch suitable for use in a local area network
EP0603916A2 (en) * 1992-12-25 1994-06-29 Nec Corporation Packet switching system using idle/busy status of output buffers
EP0715436A2 (en) * 1994-12-02 1996-06-05 AT&T Corp. ATM buffer memory priority controller
US5517495A (en) * 1994-12-06 1996-05-14 At&T Corp. Fair prioritized scheduling in an input-buffered switch
EP0719012A2 (en) * 1994-12-19 1996-06-26 Alcatel Data Networks Traffic management and congestion control for packet-based network
US5550815A (en) * 1994-12-30 1996-08-27 Lucent Technologies Inc. Apparatus and method for reducing data losses in a growable packet switch

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IBM TECHNICAL DISCLOSURE BULLETIN, Volume 30, No. 3, August 1997, (Armonk, New York), "A New Couting Window Pacing Scheme", pages 1143-45. *
IEEE TRANSACTIONS ON COMMUNICATIONS, Volume 40, No. 2, February 1992, (USA), K. ENG et al., "A Growble Packet (ATM) Switch Architecture: Design Principles and Applications". *

Also Published As

Publication number Publication date
AU6642798A (en) 1998-09-18
SE9700714D0 (en) 1997-02-27
SE9700714L (en) 1998-08-28
WO1998038771A2 (en) 1998-09-03

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