WO1998035299A3 - Verfahren zur Selbstsynchronisation von konfigurierbaren Elementen eines programmierbaren Bausteines - Google Patents

Verfahren zur Selbstsynchronisation von konfigurierbaren Elementen eines programmierbaren Bausteines Download PDF

Info

Publication number
WO1998035299A3
WO1998035299A3 PCT/DE1998/000334 DE9800334W WO9835299A3 WO 1998035299 A3 WO1998035299 A3 WO 1998035299A3 DE 9800334 W DE9800334 W DE 9800334W WO 9835299 A3 WO9835299 A3 WO 9835299A3
Authority
WO
WIPO (PCT)
Prior art keywords
synchronization
self
programmable component
configurable elements
modules
Prior art date
Application number
PCT/DE1998/000334
Other languages
English (en)
French (fr)
Other versions
WO1998035299A2 (de
Inventor
Martin Vorbach
Robert Muench
Original Assignee
Pact Inf Tech Gmbh
Martin Vorbach
Robert Muench
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=7819640&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=WO1998035299(A3) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Priority to AT98909346T priority Critical patent/ATE298907T1/de
Priority to DE19880129T priority patent/DE19880129D2/de
Priority to CA002279917A priority patent/CA2279917A1/en
Priority to DE59812895T priority patent/DE59812895D1/de
Application filed by Pact Inf Tech Gmbh, Martin Vorbach, Robert Muench filed Critical Pact Inf Tech Gmbh
Priority to EA199900653A priority patent/EA001823B1/ru
Priority to AU63918/98A priority patent/AU740243B2/en
Priority to EP98909346A priority patent/EP0961980B1/de
Priority to JP53356398A priority patent/JP4146519B2/ja
Publication of WO1998035299A2 publication Critical patent/WO1998035299A2/de
Publication of WO1998035299A3 publication Critical patent/WO1998035299A3/de
Priority to US09/369,653 priority patent/US6542998B1/en
Priority to US10/379,403 priority patent/US7036036B2/en
Priority to US12/109,280 priority patent/USRE44383E1/en
Priority to US12/909,150 priority patent/USRE45223E1/en
Priority to US12/909,061 priority patent/USRE44365E1/en
Priority to US12/909,203 priority patent/USRE45109E1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture

Abstract

Bei einem Verfahren zur Synchronisation und Umkonfiguration von konfigurierbaren Elementen in Bausteinen mit zwei- oder mehrdimensionaler programmierbarer Zellstruktur (DFP, FPGA, DPGA, RAW-Machines), sowie zur Steuerung bedingter Sprünge in üblichen Mikroprozessoren, Digitalen Signalprozessoren und Mikrokontrollern werden Synchronisationssignale während der Verarbeitung innerhalb des Datenstromes von den verarbeitenden konfigurierbaren Elementen durch Vergleiche, Vorzeichen, Überträge von arithmetischen Operationen, Fehlerzuständen, u.dgl., generiert und an weitere Elemente zur Synchronisation über den Datenbus gesandt. Aus dem Datenstrom heraus werden anhand entsprechender Befehle Konfigurationswörter innerhalb eines konfigurierbaren Elementes generiert und über den Datenbus zusammen mit der Adresse des anzusprechenden Registers an ein weiteres konfigurierbares Element übertragen, wobei dieses dadurch ohne den Einfluß einer externen Ladelogik (um)konfiguriert wird. Zur Laufzeit anhand von Synchronisationssignalen wird eine gültige Konfiguration der konfigurierbaren Elemente aus einer Mehrzahl an Konfigurationen oder ein gültiger Befehl aus mehreren möglichen Befehlen eines Rechenwerkes ausgewählt.
PCT/DE1998/000334 1997-02-08 1998-02-07 Verfahren zur selbstsynchronisation von konfigurierbaren elementen eines programmierbaren bausteines WO1998035299A2 (de)

Priority Applications (14)

Application Number Priority Date Filing Date Title
CA002279917A CA2279917A1 (en) 1997-02-08 1998-02-07 Method for self-synchronization of configurable elements of a programmable component
EP98909346A EP0961980B1 (de) 1997-02-08 1998-02-07 Verfahren zur selbstsynchronisation von konfigurierbaren elementen eines programmierbaren bausteines
JP53356398A JP4146519B2 (ja) 1997-02-08 1998-02-07 プログラミング可能なコンポーネントにおけるコンフィグレーション可能な各エレメントの自己同期を確立する方法
DE59812895T DE59812895D1 (de) 1997-02-08 1998-02-07 Verfahren zur selbstsynchronisation von konfigurierbaren elementen eines programmierbaren bausteines
DE19880129T DE19880129D2 (de) 1997-02-08 1998-02-07 Verfahren zur Selbstsynchronisation von konfigurierbaren Elementen eines programmierbaren Bausteines
EA199900653A EA001823B1 (ru) 1997-02-08 1998-02-07 Способ самосинхронизации конфигурируемых элементов программируемой микросхемы
AU63918/98A AU740243B2 (en) 1997-02-08 1998-02-07 Method of self-synchronization of configurable elements of a programmable component
AT98909346T ATE298907T1 (de) 1997-02-08 1998-02-07 Verfahren zur selbstsynchronisation von konfigurierbaren elementen eines programmierbaren bausteines
US09/369,653 US6542998B1 (en) 1997-02-08 1999-08-06 Method of self-synchronization of configurable elements of a programmable module
US10/379,403 US7036036B2 (en) 1997-02-08 2003-03-04 Method of self-synchronization of configurable elements of a programmable module
US12/109,280 USRE44383E1 (en) 1997-02-08 2008-04-24 Method of self-synchronization of configurable elements of a programmable module
US12/909,150 USRE45223E1 (en) 1997-02-08 2010-10-21 Method of self-synchronization of configurable elements of a programmable module
US12/909,061 USRE44365E1 (en) 1997-02-08 2010-10-21 Method of self-synchronization of configurable elements of a programmable module
US12/909,203 USRE45109E1 (en) 1997-02-08 2010-10-21 Method of self-synchronization of configurable elements of a programmable module

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19704728A DE19704728A1 (de) 1997-02-08 1997-02-08 Verfahren zur Selbstsynchronisation von konfigurierbaren Elementen eines programmierbaren Bausteines
DE19704728.9 1997-02-08

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US08/946,812 Continuation-In-Part US6081903A (en) 1997-02-08 1997-10-08 Method of the self-synchronization of configurable elements of a programmable unit

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US09/369,653 Continuation-In-Part US6542998B1 (en) 1997-02-08 1999-08-06 Method of self-synchronization of configurable elements of a programmable module

Publications (2)

Publication Number Publication Date
WO1998035299A2 WO1998035299A2 (de) 1998-08-13
WO1998035299A3 true WO1998035299A3 (de) 1998-09-17

Family

ID=7819640

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1998/000334 WO1998035299A2 (de) 1997-02-08 1998-02-07 Verfahren zur selbstsynchronisation von konfigurierbaren elementen eines programmierbaren bausteines

Country Status (10)

Country Link
US (3) US6081903A (de)
EP (2) EP1669885A3 (de)
JP (1) JP4146519B2 (de)
CN (1) CN1252144A (de)
AT (1) ATE298907T1 (de)
AU (1) AU740243B2 (de)
CA (1) CA2279917A1 (de)
DE (3) DE19704728A1 (de)
EA (1) EA001823B1 (de)
WO (1) WO1998035299A2 (de)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE44365E1 (en) 1997-02-08 2013-07-09 Martin Vorbach Method of self-synchronization of configurable elements of a programmable module
US8869121B2 (en) 2001-08-16 2014-10-21 Pact Xpp Technologies Ag Method for the translation of programs for reconfigurable architectures
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device

Families Citing this family (73)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7266725B2 (en) 2001-09-03 2007-09-04 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
DE19651075A1 (de) * 1996-12-09 1998-06-10 Pact Inf Tech Gmbh Einheit zur Verarbeitung von numerischen und logischen Operationen, zum Einsatz in Prozessoren (CPU's), Mehrrechnersystemen, Datenflußprozessoren (DFP's), digitalen Signal Prozessoren (DSP's) oder dergleichen
US6338106B1 (en) 1996-12-20 2002-01-08 Pact Gmbh I/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures
DE19654595A1 (de) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0- und Speicherbussystem für DFPs sowie Bausteinen mit zwei- oder mehrdimensionaler programmierbaren Zellstrukturen
DE19654846A1 (de) * 1996-12-27 1998-07-09 Pact Inf Tech Gmbh Verfahren zum selbständigen dynamischen Umladen von Datenflußprozessoren (DFPs) sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen (FPGAs, DPGAs, o. dgl.)
ATE243390T1 (de) 1996-12-27 2003-07-15 Pact Inf Tech Gmbh Verfahren zum selbständigen dynamischen umladen von datenflussprozessoren (dfps) sowie bausteinen mit zwei- oder mehrdimensionalen programmierbaren zellstrukturen (fpgas, dpgas, o.dgl.)
DE19704728A1 (de) 1997-02-08 1998-08-13 Pact Inf Tech Gmbh Verfahren zur Selbstsynchronisation von konfigurierbaren Elementen eines programmierbaren Bausteines
DE19704742A1 (de) * 1997-02-11 1998-09-24 Pact Inf Tech Gmbh Internes Bussystem für DFPs, sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen, zur Bewältigung großer Datenmengen mit hohem Vernetzungsaufwand
US8686549B2 (en) 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
DE19861088A1 (de) * 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Verfahren zur Reparatur von integrierten Schaltkreisen
DE19807872A1 (de) 1998-02-25 1999-08-26 Pact Inf Tech Gmbh Verfahren zur Verwaltung von Konfigurationsdaten in Datenflußprozessoren sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstruktur (FPGAs, DPGAs, o. dgl.
US6243836B1 (en) * 1998-08-17 2001-06-05 Lucent Technologies, Inc. Apparatus and method for circular buffering on an on-chip discontinuity trace
US8230411B1 (en) 1999-06-10 2012-07-24 Martin Vorbach Method for interleaving a program over a plurality of cells
EP2226732A3 (de) * 2000-06-13 2016-04-06 PACT XPP Technologies AG Cachehierarchie für einen Multicore-Prozessor
US20040015899A1 (en) * 2000-10-06 2004-01-22 Frank May Method for processing data
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
DE10059270B4 (de) * 2000-11-29 2012-08-02 Heidelberger Druckmaschinen Ag Vorrichtung und Verfahren zur Synchronisation von an mehreren Einheiten ablaufende Prozesse
US6990555B2 (en) * 2001-01-09 2006-01-24 Pact Xpp Technologies Ag Method of hierarchical caching of configuration data having dataflow processors and modules having two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)
US7210129B2 (en) * 2001-08-16 2007-04-24 Pact Xpp Technologies Ag Method for translating programs for reconfigurable architectures
US20090300262A1 (en) * 2001-03-05 2009-12-03 Martin Vorbach Methods and devices for treating and/or processing data
US7844796B2 (en) 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
US9037807B2 (en) * 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
EP1454258A2 (de) * 2001-03-05 2004-09-08 Pact Informationstechnologie GmbH Verfahren und vorrichtungen zur datenbe- und/oder verarbeitung
US20090210653A1 (en) * 2001-03-05 2009-08-20 Pact Xpp Technologies Ag Method and device for treating and processing data
US7624204B2 (en) * 2001-03-22 2009-11-24 Nvidia Corporation Input/output controller node in an adaptable computing environment
EP1402382B1 (de) 2001-06-20 2010-08-18 Richter, Thomas Verfahren zur bearbeitung von daten
US10031733B2 (en) * 2001-06-20 2018-07-24 Scientia Sol Mentis Ag Method for processing data
US7434191B2 (en) 2001-09-03 2008-10-07 Pact Xpp Technologies Ag Router
AU2002338729A1 (en) 2001-09-19 2003-04-01 Pact Xpp Technologies Ag Router
US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
US7594229B2 (en) * 2001-10-09 2009-09-22 Nvidia Corp. Predictive resource allocation in computing systems
US7644279B2 (en) * 2001-12-05 2010-01-05 Nvidia Corporation Consumer product distribution in the embedded system market
US7577822B2 (en) * 2001-12-14 2009-08-18 Pact Xpp Technologies Ag Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization
US20050132344A1 (en) * 2002-01-18 2005-06-16 Martin Vorbach Method of compilation
AU2003208266A1 (en) 2002-01-19 2003-07-30 Pact Xpp Technologies Ag Reconfigurable processor
WO2003071432A2 (de) 2002-02-18 2003-08-28 Pact Xpp Technologies Ag Bussysteme und rekonfigurationsverfahren
WO2003081454A2 (de) * 2002-03-21 2003-10-02 Pact Xpp Technologies Ag Verfahren und vorrichtung zur datenverarbeitung
US7093255B1 (en) * 2002-05-31 2006-08-15 Quicksilver Technology, Inc. Method for estimating cost when placing operations within a modulo scheduler when scheduling for processors with a large number of function units or reconfigurable data paths
US7620678B1 (en) 2002-06-12 2009-11-17 Nvidia Corporation Method and system for reducing the time-to-market concerns for embedded system design
US7802108B1 (en) 2002-07-18 2010-09-21 Nvidia Corporation Secure storage of program code for an embedded system
AU2003286131A1 (en) 2002-08-07 2004-03-19 Pact Xpp Technologies Ag Method and device for processing data
US7657861B2 (en) 2002-08-07 2010-02-02 Pact Xpp Technologies Ag Method and device for processing data
US20110238948A1 (en) * 2002-08-07 2011-09-29 Martin Vorbach Method and device for coupling a data processing unit and a data processing array
US7394284B2 (en) 2002-09-06 2008-07-01 Pact Xpp Technologies Ag Reconfigurable sequencer structure
US7502915B2 (en) * 2002-09-30 2009-03-10 Nvidia Corporation System and method using embedded microprocessor as a node in an adaptable computing machine
US8949576B2 (en) * 2002-11-01 2015-02-03 Nvidia Corporation Arithmetic node including general digital signal processing functions for an adaptive computing machine
US7617100B1 (en) 2003-01-10 2009-11-10 Nvidia Corporation Method and system for providing an excitation-pattern based audio coding scheme
EP1611528A2 (de) * 2003-04-04 2006-01-04 PACT XPP Technologies AG Verfahren und vorrichtung für die datenverarbeitung
US8296764B2 (en) * 2003-08-14 2012-10-23 Nvidia Corporation Internal synchronization control for adaptive integrated circuitry
EP1676208A2 (de) 2003-08-28 2006-07-05 PACT XPP Technologies AG Datenverarbeitungseinrichtung und verfahren
US8130825B2 (en) * 2004-05-10 2012-03-06 Nvidia Corporation Processor for video data encoding/decoding
US8018463B2 (en) * 2004-05-10 2011-09-13 Nvidia Corporation Processor for video data
JP2006011705A (ja) * 2004-06-24 2006-01-12 Fujitsu Ltd プロセッサおよび半導体装置
TWI256013B (en) * 2004-10-12 2006-06-01 Uli Electronics Inc Sound-effect processing circuit
JP2008530642A (ja) * 2005-02-07 2008-08-07 ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト 低レイテンシーの大量並列データ処理装置
WO2007062327A2 (en) * 2005-11-18 2007-05-31 Ideal Industries, Inc. Releasable wire connector
EP1974265A1 (de) 2006-01-18 2008-10-01 PACT XPP Technologies AG Hardwaredefinitionsverfahren
US7999820B1 (en) 2006-10-23 2011-08-16 Nvidia Corporation Methods and systems for reusing memory addresses in a graphics system
US20080111923A1 (en) * 2006-11-09 2008-05-15 Scheuermann W James Processor for video data
US7904863B2 (en) * 2006-12-04 2011-03-08 Fujitsu Limited Circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method
US8169789B1 (en) 2007-04-10 2012-05-01 Nvidia Corporation Graphics processing unit stiffening frame
US7987065B1 (en) 2007-04-17 2011-07-26 Nvidia Corporation Automatic quality testing of multimedia rendering by software drivers
US8572598B1 (en) 2007-04-18 2013-10-29 Nvidia Corporation Method and system for upgrading software in a computing device
US8726283B1 (en) 2007-06-04 2014-05-13 Nvidia Corporation Deadlock avoidance skid buffer
US7944453B1 (en) 2007-06-07 2011-05-17 Nvidia Corporation Extrapolation texture filtering for nonresident mipmaps
US7948500B2 (en) * 2007-06-07 2011-05-24 Nvidia Corporation Extrapolation of nonresident mipmap data using resident mipmap data
US7932227B1 (en) 2007-09-17 2011-04-26 University Of Virginia Patent Foundation Lacritin-syndecan fusion proteins
US8438522B1 (en) 2008-09-24 2013-05-07 Iowa State University Research Foundation, Inc. Logic element architecture for generic logic chains in programmable devices
US8661394B1 (en) 2008-09-24 2014-02-25 Iowa State University Research Foundation, Inc. Depth-optimal mapping of logic chains in reconfigurable fabrics
CN101616175B (zh) * 2009-07-24 2013-01-09 中国科学院上海技术物理研究所 用于分布式多dsp系统的网络拓扑结构获取方法和装置
EP3117210A4 (de) 2014-03-12 2017-11-01 University Of Virginia Patent Foundation Zusammensetzungen und verfahren zur behandlung von auegeninfektionen und -erkrankungen
CN104967783B (zh) * 2015-07-01 2018-01-09 西北工业大学 面向微纳星的多路微图像采集系统

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5493239A (en) * 1995-01-31 1996-02-20 Motorola, Inc. Circuit and method of configuring a field programmable gate array
EP0726532A2 (de) * 1995-02-10 1996-08-14 International Business Machines Corporation Arrayprozessorarchitektur zur Kommunikation mit Rundsendebefehlen

Family Cites Families (212)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US34363A (en) * 1862-02-11 Improvement in machinery for cleaning cotton
US2067477A (en) 1931-03-20 1937-01-12 Allis Chalmers Mfg Co Gearing
GB971191A (en) 1962-05-28 1964-09-30 Wolf Electric Tools Ltd Improvements relating to electrically driven equipment
US3681572A (en) 1970-08-11 1972-08-01 Siegfried Johannes Gerathewohl Air traveler's rest period calculator
DE2057312A1 (de) 1970-11-21 1972-05-25 Bhs Bayerische Berg Planetenradgetriebe mit Lastdruckausgleich
US3855577A (en) 1973-06-11 1974-12-17 Texas Instruments Inc Power saving circuit for calculator system
US4498134A (en) 1982-01-26 1985-02-05 Hughes Aircraft Company Segregator functional plane for use in a modular array processor
US4489857A (en) 1982-03-22 1984-12-25 Bobrick Washroom Equipment, Inc. Liquid dispenser
JPS5936857A (ja) 1982-08-25 1984-02-29 Nec Corp プロセツサユニツト
US4663706A (en) 1982-10-28 1987-05-05 Tandem Computers Incorporated Multiprocessor multisystem communications network
US4739474A (en) * 1983-03-10 1988-04-19 Martin Marietta Corporation Geometric-arithmetic parallel processor
US4566102A (en) 1983-04-18 1986-01-21 International Business Machines Corporation Parallel-shift error reconfiguration
US5123109A (en) * 1983-05-31 1992-06-16 Thinking Machines Corporation Parallel processor including a processor array with plural data transfer arrangements including (1) a global router and (2) a proximate-neighbor transfer system
USRE34363E (en) 1984-03-12 1993-08-31 Xilinx, Inc. Configurable electrical circuit having configurable logic elements and configurable interconnects
US4870302A (en) * 1984-03-12 1989-09-26 Xilinx, Inc. Configurable electrical circuit having configurable logic elements and configurable interconnects
US4761755A (en) * 1984-07-11 1988-08-02 Prime Computer, Inc. Data processing system and method having an improved arithmetic unit
US4682284A (en) 1984-12-06 1987-07-21 American Telephone & Telegraph Co., At&T Bell Lab. Queue administration method and apparatus
DE3681463D1 (de) 1985-01-29 1991-10-24 Secr Defence Brit Verarbeitungszelle fuer fehlertolerante matrixanordnungen.
US5023775A (en) * 1985-02-14 1991-06-11 Intel Corporation Software programmable logic array utilizing "and" and "or" gates
US5247689A (en) * 1985-02-25 1993-09-21 Ewert Alfred P Parallel digital processor including lateral transfer buses with interrupt switches to form bus interconnection segments
US4706216A (en) * 1985-02-27 1987-11-10 Xilinx, Inc. Configurable logic element
US5225719A (en) * 1985-03-29 1993-07-06 Advanced Micro Devices, Inc. Family of multiple segmented programmable logic blocks interconnected by a high speed centralized switch matrix
US5015884A (en) * 1985-03-29 1991-05-14 Advanced Micro Devices, Inc. Multiple array high performance programmable logic device family
US4967340A (en) * 1985-06-12 1990-10-30 E-Systems, Inc. Adaptive processing system having an array of individually configurable processing components
US4720780A (en) 1985-09-17 1988-01-19 The Johns Hopkins University Memory-linked wavefront array processor
EP0221360B1 (de) * 1985-11-04 1992-12-30 International Business Machines Corporation Digitale Nachrichtenübertragungsnetzwerke und Aufbau von Übertragungswegen in diesen Netzwerken
US4852048A (en) 1985-12-12 1989-07-25 Itt Corporation Single instruction multiple data (SIMD) cellular array processing apparatus employing a common bus where a first number of bits manifest a first bus portion and a second number of bits manifest a second bus portion
US5021947A (en) * 1986-03-31 1991-06-04 Hughes Aircraft Company Data-flow multiprocessor architecture with three dimensional multistage interconnection network for efficient signal and data processing
GB8612396D0 (en) 1986-05-21 1986-06-25 Hewlett Packard Ltd Chain-configured interface bus system
US4860201A (en) 1986-09-02 1989-08-22 The Trustees Of Columbia University In The City Of New York Binary tree parallel processor
US4910665A (en) 1986-09-02 1990-03-20 General Electric Company Distributed processing system including reconfigurable elements
US5367208A (en) * 1986-09-19 1994-11-22 Actel Corporation Reconfigurable programmable interconnect architecture
FR2606184B1 (fr) 1986-10-31 1991-11-29 Thomson Csf Dispositif de calcul reconfigurable
US4811214A (en) * 1986-11-14 1989-03-07 Princeton University Multinode reconfigurable pipeline computer
US5226122A (en) * 1987-08-21 1993-07-06 Compaq Computer Corp. Programmable logic system for filtering commands to a microprocessor
US5115510A (en) 1987-10-20 1992-05-19 Sharp Kabushiki Kaisha Multistage data flow processor with instruction packet, fetch, storage transmission and address generation controlled by destination information
US5113498A (en) 1987-11-10 1992-05-12 Echelon Corporation Input/output section for an intelligent cell which provides sensing, bidirectional communications and control
US4918690A (en) 1987-11-10 1990-04-17 Echelon Systems Corp. Network and intelligent cell for providing sensing, bidirectional communications and control
US5303172A (en) * 1988-02-16 1994-04-12 Array Microsystems Pipelined combination and vector signal processor
JPH06101043B2 (ja) 1988-06-30 1994-12-12 三菱電機株式会社 マイクロコンピュータ
US4901268A (en) * 1988-08-19 1990-02-13 General Electric Company Multiple function data processor
US5204935A (en) * 1988-08-19 1993-04-20 Fuji Xerox Co., Ltd. Programmable fuzzy logic circuits
US5353432A (en) 1988-09-09 1994-10-04 Compaq Computer Corporation Interactive method for configuration of computer system and circuit boards with user specification of system resources and computer resolution of resource conflicts
EP0363631B1 (de) 1988-09-22 1993-12-15 Siemens Aktiengesellschaft Schaltungsanordnung für Fernmeldevermittlungsanlagen, insbesondere PCM-Zeitmultiplex-Fernsprechvermittlungsanlagen mit Zentralkoppelfeld und angeschlossenen Teilkoppelfeldern
WO1990004235A1 (en) * 1988-10-07 1990-04-19 Martin Marietta Corporation Parallel data processor
US5014193A (en) * 1988-10-14 1991-05-07 Compaq Computer Corporation Dynamically configurable portable computer system
US5136717A (en) * 1988-11-23 1992-08-04 Flavors Technology Inc. Realtime systolic, multiple-instruction, single-data parallel computer system
US5081375A (en) * 1989-01-19 1992-01-14 National Semiconductor Corp. Method for operating a multiple page programmable logic device
GB8906145D0 (en) * 1989-03-17 1989-05-04 Algotronix Ltd Configurable cellular array
US5203005A (en) 1989-05-02 1993-04-13 Horst Robert W Cell structure for linear array wafer scale integration architecture with capability to open boundary i/o bus without neighbor acknowledgement
US5109503A (en) * 1989-05-22 1992-04-28 Ge Fanuc Automation North America, Inc. Apparatus with reconfigurable counter includes memory for storing plurality of counter configuration files which respectively define plurality of predetermined counters
JP2584673B2 (ja) 1989-06-09 1997-02-26 株式会社日立製作所 テストデータ変更回路を有する論理回路テスト装置
CA2021192A1 (en) 1989-07-28 1991-01-29 Malcolm A. Mumme Simplified synchronous mesh processor
US5489857A (en) * 1992-08-03 1996-02-06 Advanced Micro Devices, Inc. Flexible synchronous/asynchronous cell structure for a high density programmable logic device
US5212652A (en) * 1989-08-15 1993-05-18 Advanced Micro Devices, Inc. Programmable gate array with improved interconnect structure
US5233539A (en) 1989-08-15 1993-08-03 Advanced Micro Devices, Inc. Programmable gate array with improved interconnect structure, input/output structure and configurable logic block
US5128559A (en) * 1989-09-29 1992-07-07 Sgs-Thomson Microelectronics, Inc. Logic block for programmable logic devices
JP2968289B2 (ja) * 1989-11-08 1999-10-25 株式会社リコー 中央演算処理装置
GB8925721D0 (en) * 1989-11-14 1990-01-04 Amt Holdings Processor array system
US5522083A (en) * 1989-11-17 1996-05-28 Texas Instruments Incorporated Reconfigurable multi-processor operating in SIMD mode with one processor fetching instructions for use by remaining processors
DE58908974D1 (de) 1989-11-21 1995-03-16 Itt Ind Gmbh Deutsche Datengesteuerter Arrayprozessor.
US5125801A (en) * 1990-02-02 1992-06-30 Isco, Inc. Pumping system
US5142469A (en) * 1990-03-29 1992-08-25 Ge Fanuc Automation North America, Inc. Method for converting a programmable logic controller hardware configuration and corresponding control program for use on a first programmable logic controller to use on a second programmable logic controller
US5198705A (en) * 1990-05-11 1993-03-30 Actel Corporation Logic module with configurable combinational and sequential blocks
US5483620A (en) * 1990-05-22 1996-01-09 International Business Machines Corp. Learning machine synapse processor system apparatus
US5193202A (en) 1990-05-29 1993-03-09 Wavetracer, Inc. Processor array with relocated operand physical address generator capable of data transfer to distant physical processor for each virtual processor while simulating dimensionally larger array processor
US5111079A (en) * 1990-06-29 1992-05-05 Sgs-Thomson Microelectronics, Inc. Power reduction circuit for programmable logic device
SE9002558D0 (sv) * 1990-08-02 1990-08-02 Carlstedt Elektronik Ab Processor
US5274593A (en) 1990-09-28 1993-12-28 Intergraph Corporation High speed redundant rows and columns for semiconductor memories
US5144166A (en) 1990-11-02 1992-09-01 Concurrent Logic, Inc. Programmable logic cell and array
US5590345A (en) * 1990-11-13 1996-12-31 International Business Machines Corporation Advanced parallel array processor(APAP)
US5752067A (en) 1990-11-13 1998-05-12 International Business Machines Corporation Fully scalable parallel processing system having asynchronous SIMD processing
US5588152A (en) * 1990-11-13 1996-12-24 International Business Machines Corporation Advanced parallel processor including advanced support hardware
US5794059A (en) 1990-11-13 1998-08-11 International Business Machines Corporation N-dimensional modified hypercube
US5765011A (en) 1990-11-13 1998-06-09 International Business Machines Corporation Parallel processing system having a synchronous SIMD processing with processing elements emulating SIMD operation using individual instruction streams
US5734921A (en) 1990-11-13 1998-03-31 International Business Machines Corporation Advanced parallel array processor computer package
US5301284A (en) 1991-01-16 1994-04-05 Walker-Estes Corporation Mixed-resolution, N-dimensional object space method and apparatus
US5301344A (en) * 1991-01-29 1994-04-05 Analogic Corporation Multibus sequential processor to perform in parallel a plurality of reconfigurable logic operations on a plurality of data sets
DE59107764D1 (de) * 1991-02-22 1996-06-05 Siemens Ag Speicherprogrammierbare Steuerung
JPH04290155A (ja) * 1991-03-19 1992-10-14 Fujitsu Ltd 並列データ処理方式
JPH04293151A (ja) * 1991-03-20 1992-10-16 Fujitsu Ltd 並列データ処理方式
US5617547A (en) 1991-03-29 1997-04-01 International Business Machines Corporation Switch network extension of bus architecture
KR0125623B1 (ko) * 1991-04-09 1998-07-01 세끼자와 다다시 데이타 프로세서 및 데이타 처리방법
US5551033A (en) * 1991-05-17 1996-08-27 Zenith Data Systems Corporation Apparatus for maintaining one interrupt mask register in conformity with another in a manner invisible to an executing program
WO1992022029A1 (en) * 1991-05-24 1992-12-10 British Technology Group Usa, Inc. Optimizing compiler for computers
US5287344A (en) * 1991-06-05 1994-02-15 At&T Bell Laboratories Transferring lines in a digital loop carrier transmission system
US5659797A (en) 1991-06-24 1997-08-19 U.S. Philips Corporation Sparc RISC based computer system including a single chip processor with memory management and DMA units coupled to a DRAM interface
US5347639A (en) 1991-07-15 1994-09-13 International Business Machines Corporation Self-parallelizing computer system and method
US5338984A (en) * 1991-08-29 1994-08-16 National Semiconductor Corp. Local and express diagonal busses in a configurable logic array
US5260610A (en) * 1991-09-03 1993-11-09 Altera Corporation Programmable logic element interconnections for programmable logic array integrated circuits
FR2681791B1 (fr) 1991-09-27 1994-05-06 Salomon Sa Dispositif d'amortissement des vibrations pour club de golf.
US5223539A (en) * 1991-11-22 1993-06-29 G. D. Searle & Co. N,n-di-alkyl(phenoxy)benzamide derivatives
CA2073516A1 (en) 1991-11-27 1993-05-28 Peter Michael Kogge Dynamic multi-mode parallel processor array architecture computer system
WO1993011503A1 (en) 1991-12-06 1993-06-10 Norman Richard S Massively-parallel direct output processor array
US5208491A (en) * 1992-01-07 1993-05-04 Washington Research Foundation Field programmable gate array
FR2686175B1 (fr) 1992-01-14 1996-12-20 Andre Thepaut Systeme de traitement de donnees multiprocesseur.
JP2791243B2 (ja) * 1992-03-13 1998-08-27 株式会社東芝 階層間同期化システムおよびこれを用いた大規模集積回路
US5452401A (en) 1992-03-31 1995-09-19 Seiko Epson Corporation Selective power-down for high performance CPU/system
US5611049A (en) * 1992-06-03 1997-03-11 Pitts; William M. System for accessing distributed data cache channel at each network node to pass requests and data
WO1993024895A2 (en) * 1992-06-04 1993-12-09 Xilinx, Inc. Timing driven method for laying out a user's circuit onto a programmable integrated circuit device
US5475803A (en) * 1992-07-10 1995-12-12 Lsi Logic Corporation Method for 2-D affine transformation of images
US5590348A (en) 1992-07-28 1996-12-31 International Business Machines Corporation Status predictor for combined shifter-rotate/merge unit
US5581778A (en) * 1992-08-05 1996-12-03 David Sarnoff Researach Center Advanced massively parallel computer using a field of the instruction to selectively enable the profiling counter to increase its value in response to the system clock
US5425036A (en) 1992-09-18 1995-06-13 Quickturn Design Systems, Inc. Method and apparatus for debugging reconfigurable emulation systems
JPH06180653A (ja) 1992-10-02 1994-06-28 Hudson Soft Co Ltd 割り込み処理方法および装置
US5329179A (en) * 1992-10-05 1994-07-12 Lattice Semiconductor Corporation Arrangement for parallel programming of in-system programmable IC logical devices
US5497498A (en) * 1992-11-05 1996-03-05 Giga Operations Corporation Video processing module using a second programmable logic device which reconfigures a first programmable logic device for data transformation
US5392437A (en) 1992-11-06 1995-02-21 Intel Corporation Method and apparatus for independently stopping and restarting functional units
US5361373A (en) * 1992-12-11 1994-11-01 Gilson Kent L Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
US5428526A (en) 1993-02-03 1995-06-27 Flood; Mark A. Programmable controller with time periodic communication
GB9303084D0 (en) * 1993-02-16 1993-03-31 Inmos Ltd Programmable logic circuit
JPH06276086A (ja) * 1993-03-18 1994-09-30 Fuji Xerox Co Ltd フィールドプログラマブルゲートアレイ
US5548773A (en) * 1993-03-30 1996-08-20 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Digital parallel processor array for optimum path planning
US5596742A (en) 1993-04-02 1997-01-21 Massachusetts Institute Of Technology Virtual interconnections for reconfigurable logic systems
US5473266A (en) * 1993-04-19 1995-12-05 Altera Corporation Programmable logic device having fast programmable logic array blocks and a central global interconnect array
DE4416881C2 (de) * 1993-05-13 1998-03-19 Pact Inf Tech Gmbh Verfahren zum Betrieb einer Datenverarbeitungseinrichtung
US5349193A (en) 1993-05-20 1994-09-20 Princeton Gamma Tech, Inc. Highly sensitive nuclear spectrometer apparatus and method
US5444394A (en) * 1993-07-08 1995-08-22 Altera Corporation PLD with selective inputs from local and global conductors
JPH0736858A (ja) * 1993-07-21 1995-02-07 Hitachi Ltd 信号処理プロセッサ
US5457644A (en) * 1993-08-20 1995-10-10 Actel Corporation Field programmable digital signal processing array integrated circuit
US5440538A (en) 1993-09-23 1995-08-08 Massachusetts Institute Of Technology Communication system with redundant links and data bit time multiplexing
US5455525A (en) * 1993-12-06 1995-10-03 Intelligent Logic Systems, Inc. Hierarchically-structured programmable logic array and system for interconnecting logic elements in the logic array
US5535406A (en) * 1993-12-29 1996-07-09 Kolchinsky; Alexander Virtual processor module including a reconfigurable programmable matrix
EP1037149A3 (de) 1994-03-22 2003-10-15 Hyperchip Inc. Direkte Zellenersetzung für fehlertolerante Architektur mit gänzlich integrierten Systemen und mit Mitteln zur direkten Kommunikation mit dem Systembediener
US5561738A (en) * 1994-03-25 1996-10-01 Motorola, Inc. Data processor for executing a fuzzy logic operation and method therefor
US5430687A (en) * 1994-04-01 1995-07-04 Xilinx, Inc. Programmable logic device including a parallel input device for loading memory cells
US5761484A (en) 1994-04-01 1998-06-02 Massachusetts Institute Of Technology Virtual interconnections for reconfigurable logic systems
US5896551A (en) * 1994-04-15 1999-04-20 Micron Technology, Inc. Initializing and reprogramming circuitry for state independent memory array burst operations control
US5426378A (en) * 1994-04-20 1995-06-20 Xilinx, Inc. Programmable logic device which stores more than one configuration and means for switching configurations
US5532693A (en) * 1994-06-13 1996-07-02 Advanced Hardware Architectures Adaptive data compression system with systolic string matching logic
US5513366A (en) * 1994-09-28 1996-04-30 International Business Machines Corporation Method and system for dynamically reconfiguring a register file in a vector processor
US5530946A (en) 1994-10-28 1996-06-25 Dell Usa, L.P. Processor failure detection and recovery circuit in a dual processor computer system and method of operation thereof
EP0721157A1 (de) * 1994-12-12 1996-07-10 Advanced Micro Devices, Inc. Mikroprozessor mit auswählbarer Taktfrequenz
US5532957A (en) * 1995-01-31 1996-07-02 Texas Instruments Incorporated Field reconfigurable logic/memory array
US6052773A (en) 1995-02-10 2000-04-18 Massachusetts Institute Of Technology DPGA-coupled microprocessors
US5742180A (en) 1995-02-10 1998-04-21 Massachusetts Institute Of Technology Dynamically programmable gate array with multiple contexts
US5537057A (en) * 1995-02-14 1996-07-16 Altera Corporation Programmable logic array device with grouped logic regions and three types of conductors
US5892961A (en) 1995-02-17 1999-04-06 Xilinx, Inc. Field programmable gate array having programming instructions in the configuration bitstream
US5570040A (en) * 1995-03-22 1996-10-29 Altera Corporation Programmable logic array integrated circuit incorporating a first-in first-out memory
US5541530A (en) * 1995-05-17 1996-07-30 Altera Corporation Programmable logic array integrated circuits with blocks of logic regions grouped into super-blocks
US5646544A (en) * 1995-06-05 1997-07-08 International Business Machines Corporation System and method for dynamically reconfiguring a programmable gate array
US5889982A (en) * 1995-07-01 1999-03-30 Intel Corporation Method and apparatus for generating event handler vectors based on both operating mode and event type
US5559450A (en) * 1995-07-27 1996-09-24 Lucent Technologies Inc. Field programmable gate array with multi-port RAM
US5649176A (en) * 1995-08-10 1997-07-15 Virtual Machine Works, Inc. Transition analysis and circuit resynthesis method and device for digital circuit modeling
US5778439A (en) * 1995-08-18 1998-07-07 Xilinx, Inc. Programmable logic device with hierarchical confiquration and state storage
US5583450A (en) * 1995-08-18 1996-12-10 Xilinx, Inc. Sequencer for a time multiplexed programmable logic device
US5652894A (en) 1995-09-29 1997-07-29 Intel Corporation Method and apparatus for providing power saving modes to a pipelined processor
US5943242A (en) * 1995-11-17 1999-08-24 Pact Gmbh Dynamically reconfigurable data processing system
US5732209A (en) * 1995-11-29 1998-03-24 Exponential Technology, Inc. Self-testing multi-processor die with internal compare points
US7266725B2 (en) * 2001-09-03 2007-09-04 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
US5854918A (en) * 1996-01-24 1998-12-29 Ricoh Company Ltd. Apparatus and method for self-timed algorithmic execution
US5936424A (en) 1996-02-02 1999-08-10 Xilinx, Inc. High speed bus with tree structure for selecting bus driver
US6020758A (en) * 1996-03-11 2000-02-01 Altera Corporation Partially reconfigurable programmable logic device
US6173434B1 (en) * 1996-04-22 2001-01-09 Brigham Young University Dynamically-configurable digital processor using method for relocating logic array modules
US5894565A (en) 1996-05-20 1999-04-13 Atmel Corporation Field programmable gate array with distributed RAM and increased cell utilization
JP2000513523A (ja) * 1996-06-21 2000-10-10 オーガニック システムズ インコーポレイテッド プロセスの即時制御を行う動的に再構成可能なハードウェアシステム
US5892370A (en) * 1996-06-21 1999-04-06 Quicklogic Corporation Clock network for field programmable gate array
US6023742A (en) * 1996-07-18 2000-02-08 University Of Washington Reconfigurable computing architecture for providing pipelined data paths
US6023564A (en) * 1996-07-19 2000-02-08 Xilinx, Inc. Data processing system using a flash reconfigurable logic device as a dynamic execution unit for a sequence of instructions
US5838165A (en) 1996-08-21 1998-11-17 Chatter; Mukesh High performance self modifying on-the-fly alterable logic FPGA, architecture and method
US5859544A (en) * 1996-09-05 1999-01-12 Altera Corporation Dynamic configurable elements for programmable logic devices
US5828858A (en) * 1996-09-16 1998-10-27 Virginia Tech Intellectual Properties, Inc. Worm-hole run-time reconfigurable processor field programmable gate array (FPGA)
US6005410A (en) 1996-12-05 1999-12-21 International Business Machines Corporation Interconnect structure between heterogeneous core regions in a programmable array
DE19651075A1 (de) 1996-12-09 1998-06-10 Pact Inf Tech Gmbh Einheit zur Verarbeitung von numerischen und logischen Operationen, zum Einsatz in Prozessoren (CPU's), Mehrrechnersystemen, Datenflußprozessoren (DFP's), digitalen Signal Prozessoren (DSP's) oder dergleichen
US6338106B1 (en) * 1996-12-20 2002-01-08 Pact Gmbh I/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures
DE19654593A1 (de) * 1996-12-20 1998-07-02 Pact Inf Tech Gmbh Umkonfigurierungs-Verfahren für programmierbare Bausteine zur Laufzeit
DE19654595A1 (de) * 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0- und Speicherbussystem für DFPs sowie Bausteinen mit zwei- oder mehrdimensionaler programmierbaren Zellstrukturen
DE19654846A1 (de) * 1996-12-27 1998-07-09 Pact Inf Tech Gmbh Verfahren zum selbständigen dynamischen Umladen von Datenflußprozessoren (DFPs) sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen (FPGAs, DPGAs, o. dgl.)
DE19704044A1 (de) * 1997-02-04 1998-08-13 Pact Inf Tech Gmbh Verfahren zur automatischen Adressgenerierung von Bausteinen innerhalb Clustern aus einer Vielzahl dieser Bausteine
US5865239A (en) * 1997-02-05 1999-02-02 Micropump, Inc. Method for making herringbone gears
DE19704728A1 (de) * 1997-02-08 1998-08-13 Pact Inf Tech Gmbh Verfahren zur Selbstsynchronisation von konfigurierbaren Elementen eines programmierbaren Bausteines
US6542998B1 (en) * 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
DE19704742A1 (de) * 1997-02-11 1998-09-24 Pact Inf Tech Gmbh Internes Bussystem für DFPs, sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen, zur Bewältigung großer Datenmengen mit hohem Vernetzungsaufwand
WO1998038958A1 (en) 1997-03-05 1998-09-11 Massachusetts Institute Of Technology A reconfigurable footprint mechanism for omnidirectional vehicles
US5884075A (en) * 1997-03-10 1999-03-16 Compaq Computer Corporation Conflict resolution using self-contained virtual devices
US6047115A (en) * 1997-05-29 2000-04-04 Xilinx, Inc. Method for configuring FPGA memory planes for virtual hardware computation
US6011407A (en) * 1997-06-13 2000-01-04 Xilinx, Inc. Field programmable gate array with dedicated computer bus interface and method for configuring both
US5966534A (en) * 1997-06-27 1999-10-12 Cooke; Laurence H. Method for compiling high level programming languages into an integrated processor with reconfigurable logic
US6038656A (en) * 1997-09-12 2000-03-14 California Institute Of Technology Pipelined completion for asynchronous communication
US6108760A (en) 1997-10-31 2000-08-22 Silicon Spice Method and apparatus for position independent reconfiguration in a network of multiple context processing elements
US6122719A (en) 1997-10-31 2000-09-19 Silicon Spice Method and apparatus for retiming in a network of multiple context processing elements
US5915123A (en) 1997-10-31 1999-06-22 Silicon Spice Method and apparatus for controlling configuration memory contexts of processing elements in a network of multiple context processing elements
US6127908A (en) 1997-11-17 2000-10-03 Massachusetts Institute Of Technology Microelectro-mechanical system actuator device and reconfigurable circuits utilizing same
DE69737750T2 (de) * 1997-12-17 2008-03-06 Hewlett-Packard Development Co., L.P., Houston Erst- und Zweitprozessoren verwendetes Verfahren
DE19861088A1 (de) * 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Verfahren zur Reparatur von integrierten Schaltkreisen
US6172520B1 (en) * 1997-12-30 2001-01-09 Xilinx, Inc. FPGA system with user-programmable configuration ports and method for reconfiguring the FPGA
US6049222A (en) * 1997-12-30 2000-04-11 Xilinx, Inc Configuring an FPGA using embedded memory
US6034538A (en) 1998-01-21 2000-03-07 Lucent Technologies Inc. Virtual logic system for reconfigurable hardware
US6389579B1 (en) 1998-01-26 2002-05-14 Chameleon Systems Reconfigurable logic for table lookup
US5965518A (en) 1998-02-23 1999-10-12 Nakatsu; Tetsuo Fragrance compositions having antimicrobial activity
DE19807872A1 (de) * 1998-02-25 1999-08-26 Pact Inf Tech Gmbh Verfahren zur Verwaltung von Konfigurationsdaten in Datenflußprozessoren sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstruktur (FPGAs, DPGAs, o. dgl.
US6282627B1 (en) 1998-06-29 2001-08-28 Chameleon Systems, Inc. Integrated processor and programmable data path chip for reconfigurable computing
US6202182B1 (en) 1998-06-30 2001-03-13 Lucent Technologies Inc. Method and apparatus for testing field programmable gate arrays
US6345346B1 (en) * 1999-02-26 2002-02-05 Voom Technologies Substantially instantaneous storage restoration for non-computer forensics applications
US6243808B1 (en) 1999-03-08 2001-06-05 Chameleon Systems, Inc. Digital data bit order conversion using universal switch matrix comprising rows of bit swapping selector groups
US6347346B1 (en) * 1999-06-30 2002-02-12 Chameleon Systems, Inc. Local memory unit system with global access for use on reconfigurable chips
GB2352548B (en) * 1999-07-26 2001-06-06 Sun Microsystems Inc Method and apparatus for executing standard functions in a computer system
US6370596B1 (en) 1999-08-03 2002-04-09 Chameleon Systems, Inc. Logic flag registers for monitoring processing system events
US6341318B1 (en) 1999-08-10 2002-01-22 Chameleon Systems, Inc. DMA data streaming
US6288566B1 (en) 1999-09-23 2001-09-11 Chameleon Systems, Inc. Configuration state memory for functional blocks on a reconfigurable chip
US6349346B1 (en) 1999-09-23 2002-02-19 Chameleon Systems, Inc. Control fabric unit including associated configuration memory and PSOP state machine adapted to provide configuration address to reconfigurable functional unit
US6311200B1 (en) 1999-09-23 2001-10-30 Chameleon Systems, Inc. Reconfigurable program sum of products generator
DE19946752A1 (de) * 1999-09-29 2001-04-12 Infineon Technologies Ag Rekonfigurierbares Gate-Array
US6519674B1 (en) * 2000-02-18 2003-02-11 Chameleon Systems, Inc. Configuration bits layout
US6539477B1 (en) * 2000-03-03 2003-03-25 Chameleon Systems, Inc. System and method for control synthesis using a reachable states look-up table
EP2226732A3 (de) * 2000-06-13 2016-04-06 PACT XPP Technologies AG Cachehierarchie für einen Multicore-Prozessor
US6538468B1 (en) * 2000-07-31 2003-03-25 Cypress Semiconductor Corporation Method and apparatus for multiple boot-up functionalities for a programmable logic device (PLD)
US20040015899A1 (en) * 2000-10-06 2004-01-22 Frank May Method for processing data
US6392912B1 (en) 2001-01-10 2002-05-21 Chameleon Systems, Inc. Loading data plane on reconfigurable chip
US7210129B2 (en) * 2001-08-16 2007-04-24 Pact Xpp Technologies Ag Method for translating programs for reconfigurable architectures
US20030055861A1 (en) * 2001-09-18 2003-03-20 Lai Gary N. Multipler unit in reconfigurable chip
US20030052711A1 (en) * 2001-09-19 2003-03-20 Taylor Bradley L. Despreader/correlator unit for use in reconfigurable chip

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5493239A (en) * 1995-01-31 1996-02-20 Motorola, Inc. Circuit and method of configuring a field programmable gate array
EP0726532A2 (de) * 1995-02-10 1996-08-14 International Business Machines Corporation Arrayprozessorarchitektur zur Kommunikation mit Rundsendebefehlen

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
MAXFIELD C: "LOGIC THAT MUTATES WHILE-U-WAIT", EDN ELECTRICAL DESIGN NEWS, vol. 7, 7 November 1996 (1996-11-07), pages 137 - 140, 142, XP002064224 *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE44365E1 (en) 1997-02-08 2013-07-09 Martin Vorbach Method of self-synchronization of configurable elements of a programmable module
USRE44383E1 (en) 1997-02-08 2013-07-16 Martin Vorbach Method of self-synchronization of configurable elements of a programmable module
USRE45109E1 (en) 1997-02-08 2014-09-02 Pact Xpp Technologies Ag Method of self-synchronization of configurable elements of a programmable module
USRE45223E1 (en) 1997-02-08 2014-10-28 Pact Xpp Technologies Ag Method of self-synchronization of configurable elements of a programmable module
US8869121B2 (en) 2001-08-16 2014-10-21 Pact Xpp Technologies Ag Method for the translation of programs for reconfigurable architectures
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device

Also Published As

Publication number Publication date
US6526520B1 (en) 2003-02-25
ATE298907T1 (de) 2005-07-15
EP0961980B1 (de) 2005-06-29
EA199900653A1 (ru) 2000-08-28
DE19880129D2 (de) 2000-01-27
EP1669885A2 (de) 2006-06-14
CA2279917A1 (en) 1998-08-13
JP4146519B2 (ja) 2008-09-10
US20040052130A1 (en) 2004-03-18
AU740243B2 (en) 2001-11-01
DE59812895D1 (de) 2005-08-04
US6968452B2 (en) 2005-11-22
EA001823B1 (ru) 2001-08-27
AU6391898A (en) 1998-08-26
EP1669885A3 (de) 2007-09-12
DE19704728A1 (de) 1998-08-13
WO1998035299A2 (de) 1998-08-13
JP2001511325A (ja) 2001-08-07
CN1252144A (zh) 2000-05-03
EP0961980A2 (de) 1999-12-08
US6081903A (en) 2000-06-27

Similar Documents

Publication Publication Date Title
WO1998035299A3 (de) Verfahren zur Selbstsynchronisation von konfigurierbaren Elementen eines programmierbaren Bausteines
AU6534198A (en) Circuits, system, and methods for processing multiple data streams
EP0840196A3 (de) Schaltungsanordnung zur Umschaltung zwischen Taktquellen in einem Datenverarbeitungssystem
AU9543598A (en) A method and a system for processing a virtual acoustic environment
GB2300504B (en) Programmable switch for fpga input/output signals
AU9112298A (en) System and process for inter-domain interaction across an inter-domain connectivity plane
EP0621545A3 (de) Rechnergestütztes Entwurfs- und Anfertigungssystem für Bauteilanordnung und Rohrverlegungsplanung.
AU2725201A (en) Signal processing system and method
AU3477997A (en) Digital data processing methods and apparatus for fault isolation
AU5235196A (en) Secure receipt-free electronic voting
AU2422201A (en) Supersonic external-compression diffuser and method for designing same
GB0108875D0 (en) Input and output systems for data processing
AU4920697A (en) High speed input buffer
AU8566598A (en) Triphasic composite and method for making same
AU2222097A (en) Pretreatment process in flour milling method
AU628545B2 (en) Initialization system for input/output processing units
GB0013353D0 (en) Method and apparatus for processing digital pixel output signals
AU2001272093A1 (en) System and method for high speed communications using digital signal processing
AU4146999A (en) Echo cancellation in digital data transmission system
AU2002360357A1 (en) Method and apparatus for generating input signals in a physical system
AU2660097A (en) System and method for generating fractional length delay lines in a digital signal processing system
EP0636700A3 (de) Verfahren und Vorrichtung zur Herstellung von metallkeramischen Verbundwerkstoffen.
AU2680299A (en) Downloadable smart proxies for performing processing associated with a remote procedure call in a distributed system
AU2748297A (en) Legal claims processing system and methods of litigation management using the same
GB9612860D0 (en) Methods for implementing logic in auxiliary components associated with programmable logic array devices

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 98803968.0

Country of ref document: CN

AK Designated states

Kind code of ref document: A2

Designated state(s): AL AM AT AU AZ BA BB BG BR BY CA CH CN CU CZ DE DK EE ES FI GB GE GH GM GW HU ID IL IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT UA UG US UZ VN YU ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW SD SZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN ML MR NE SN TD TG

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 1998909346

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 2279917

Country of ref document: CA

Ref document number: 2279917

Country of ref document: CA

Kind code of ref document: A

Ref document number: 1998 533563

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 199900653

Country of ref document: EA

WWE Wipo information: entry into national phase

Ref document number: 63918/98

Country of ref document: AU

WWP Wipo information: published in national office

Ref document number: 1998909346

Country of ref document: EP

REF Corresponds to

Ref document number: 19880129

Country of ref document: DE

Date of ref document: 20000127

WWE Wipo information: entry into national phase

Ref document number: 19880129

Country of ref document: DE

WWG Wipo information: grant in national office

Ref document number: 63918/98

Country of ref document: AU

WWG Wipo information: grant in national office

Ref document number: 1998909346

Country of ref document: EP