WO1998029897A3 - Well boosting threshold voltage rollup - Google Patents
Well boosting threshold voltage rollup Download PDFInfo
- Publication number
- WO1998029897A3 WO1998029897A3 PCT/US1997/022400 US9722400W WO9829897A3 WO 1998029897 A3 WO1998029897 A3 WO 1998029897A3 US 9722400 W US9722400 W US 9722400W WO 9829897 A3 WO9829897 A3 WO 9829897A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- rollup
- threshold voltage
- channel
- implant
- devices
- Prior art date
Links
- 239000007943 implant Substances 0.000 abstract 4
- 125000001475 halogen functional group Chemical group 0.000 abstract 2
- 239000002019 doping agent Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
- H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66537—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a self aligned punch through stopper or threshold implant under the gate region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Abstract
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP97949777A EP0970513A2 (en) | 1996-12-30 | 1997-12-08 | Well boosting threshold voltage rollup |
AU78932/98A AU7893298A (en) | 1996-12-30 | 1997-12-08 | Well boosting threshold voltage rollup |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/777,552 | 1996-12-30 | ||
US08/777,552 US6020244A (en) | 1996-12-30 | 1996-12-30 | Channel dopant implantation with automatic compensation for variations in critical dimension |
Publications (2)
Publication Number | Publication Date |
---|---|
WO1998029897A2 WO1998029897A2 (en) | 1998-07-09 |
WO1998029897A3 true WO1998029897A3 (en) | 1998-09-11 |
Family
ID=25110566
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1997/022400 WO1998029897A2 (en) | 1996-12-30 | 1997-12-08 | Well boosting threshold voltage rollup |
Country Status (7)
Country | Link |
---|---|
US (1) | US6020244A (en) |
EP (1) | EP0970513A2 (en) |
KR (1) | KR20000069811A (en) |
CN (1) | CN1247632A (en) |
AU (1) | AU7893298A (en) |
TW (1) | TW406432B (en) |
WO (1) | WO1998029897A2 (en) |
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US6194768B1 (en) * | 1998-10-23 | 2001-02-27 | Advanced Micro Devices, Inc. | High dielectric constant gate dielectric with an overlying tantalum gate conductor formed on a sidewall surface of a sacrificial structure |
US6180464B1 (en) * | 1998-11-24 | 2001-01-30 | Advanced Micro Devices, Inc. | Metal oxide semiconductor device with localized laterally doped channel |
US6624030B2 (en) | 2000-12-19 | 2003-09-23 | Advanced Power Devices, Inc. | Method of fabricating power rectifier device having a laterally graded P-N junction for a channel region |
US6194293B1 (en) * | 1999-05-25 | 2001-02-27 | Advanced Micro Devices, Inc. | Channel formation after source and drain regions are formed |
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US6221703B1 (en) * | 1999-07-14 | 2001-04-24 | United Microelectronics Corp. | Method of ion implantation for adjusting the threshold voltage of MOS transistors |
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US6372587B1 (en) * | 2000-05-10 | 2002-04-16 | Advanced Micro Devices, Inc. | Angled halo implant tailoring using implant mask |
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US6489223B1 (en) * | 2001-07-03 | 2002-12-03 | International Business Machines Corporation | Angled implant process |
US20030064550A1 (en) * | 2001-09-28 | 2003-04-03 | Layman Paul Arthur | Method of ion implantation for achieving desired dopant concentration |
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US8221544B2 (en) * | 2005-04-06 | 2012-07-17 | The Trustees Of Columbia University In The City Of New York | Line scan sequential lateral solidification of thin films |
KR101368570B1 (en) * | 2005-08-16 | 2014-02-27 | 더 트러스티이스 오브 콜롬비아 유니버시티 인 더 시티 오브 뉴욕 | High throughput crystallization of thin films |
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JP2011515834A (en) * | 2008-02-29 | 2011-05-19 | ザ トラスティーズ オブ コロンビア ユニヴァーシティ イン ザ シティ オブ ニューヨーク | Lithographic method for producing uniform crystalline silicon thin films |
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WO2010056990A1 (en) | 2008-11-14 | 2010-05-20 | The Trustees Of Columbia University In The City Of New York | Systems and methods for the crystallization of thin films |
US7829939B1 (en) * | 2009-04-20 | 2010-11-09 | International Business Machines Corporation | MOSFET including epitaxial halo region |
US8440581B2 (en) * | 2009-11-24 | 2013-05-14 | The Trustees Of Columbia University In The City Of New York | Systems and methods for non-periodic pulse sequential lateral solidification |
US9646831B2 (en) | 2009-11-03 | 2017-05-09 | The Trustees Of Columbia University In The City Of New York | Advanced excimer laser annealing for thin films |
US9087696B2 (en) | 2009-11-03 | 2015-07-21 | The Trustees Of Columbia University In The City Of New York | Systems and methods for non-periodic pulse partial melt film processing |
CN102054699B (en) * | 2009-11-05 | 2012-07-25 | 中芯国际集成电路制造(上海)有限公司 | Method for improving junction depth property of semiconductor device |
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CN102737965A (en) * | 2011-04-12 | 2012-10-17 | 中芯国际集成电路制造(上海)有限公司 | Formation method of Halo structure |
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CN105244260A (en) * | 2015-10-26 | 2016-01-13 | 武汉新芯集成电路制造有限公司 | Semiconductor structure and preparation method |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5320974A (en) * | 1991-07-25 | 1994-06-14 | Matsushita Electric Industrial Co., Ltd. | Method for making semiconductor transistor device by implanting punch through stoppers |
US5543337A (en) * | 1994-06-15 | 1996-08-06 | Lsi Logic Corporation | Method for fabricating field effect transistor structure using symmetrical high tilt angle punchthrough implants |
US5593907A (en) * | 1995-03-08 | 1997-01-14 | Advanced Micro Devices | Large tilt angle boron implant methodology for reducing subthreshold current in NMOS integrated circuit devices |
Family Cites Families (8)
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---|---|---|---|---|
JPH04113634A (en) * | 1990-09-03 | 1992-04-15 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
US5466957A (en) * | 1991-10-31 | 1995-11-14 | Sharp Kabushiki Kaisha | Transistor having source-to-drain nonuniformly-doped channel and method for fabricating the same |
JPH05136403A (en) * | 1991-11-15 | 1993-06-01 | Nippon Steel Corp | Manufacture of mos type semiconductor device |
JPH0637309A (en) * | 1992-07-16 | 1994-02-10 | Toshiba Corp | Semiconductor device and manufacture thereof |
JPH0645600A (en) * | 1992-07-22 | 1994-02-18 | Nec Corp | Semiconductor integrted circuit device |
JP3220267B2 (en) * | 1993-01-06 | 2001-10-22 | 株式会社東芝 | Method for manufacturing semiconductor device |
JP2658810B2 (en) * | 1993-07-30 | 1997-09-30 | 日本電気株式会社 | Non-uniform channel-doped MOS transistor and method of manufacturing the same |
JPH08335697A (en) * | 1995-06-06 | 1996-12-17 | Sony Corp | Semiconductor device and manufacture thereof |
-
1996
- 1996-12-30 US US08/777,552 patent/US6020244A/en not_active Expired - Lifetime
-
1997
- 1997-12-08 EP EP97949777A patent/EP0970513A2/en not_active Withdrawn
- 1997-12-08 WO PCT/US1997/022400 patent/WO1998029897A2/en not_active Application Discontinuation
- 1997-12-08 KR KR1019997005961A patent/KR20000069811A/en not_active Application Discontinuation
- 1997-12-08 CN CN97181967A patent/CN1247632A/en active Pending
- 1997-12-08 AU AU78932/98A patent/AU7893298A/en not_active Abandoned
-
1998
- 1998-01-23 TW TW086119995A patent/TW406432B/en not_active IP Right Cessation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5320974A (en) * | 1991-07-25 | 1994-06-14 | Matsushita Electric Industrial Co., Ltd. | Method for making semiconductor transistor device by implanting punch through stoppers |
US5543337A (en) * | 1994-06-15 | 1996-08-06 | Lsi Logic Corporation | Method for fabricating field effect transistor structure using symmetrical high tilt angle punchthrough implants |
US5593907A (en) * | 1995-03-08 | 1997-01-14 | Advanced Micro Devices | Large tilt angle boron implant methodology for reducing subthreshold current in NMOS integrated circuit devices |
Also Published As
Publication number | Publication date |
---|---|
WO1998029897A2 (en) | 1998-07-09 |
CN1247632A (en) | 2000-03-15 |
TW406432B (en) | 2000-09-21 |
EP0970513A4 (en) | 2000-01-12 |
KR20000069811A (en) | 2000-11-25 |
AU7893298A (en) | 1998-07-31 |
US6020244A (en) | 2000-02-01 |
EP0970513A2 (en) | 2000-01-12 |
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