WO1998027580A1

WO1998027580A1 - Process for forming ultrathin oxynitride layers and thin layer devices containing ultrathin oxynitride layers

Info

Publication number: WO1998027580A1
Application number: PCT/US1997/020175
Authority: WO
Inventors: Gianni D. Leonarduzzi; Dim-Lee Kwong
Original assignee: Scott Specialty Gases, Inc.
Priority date: 1996-12-03
Filing date: 1997-11-03
Publication date: 1998-06-25
Also published as: AU5429998A

Abstract

A method of forming an oxynitride gate dielectric layer is disclosed. The oxynitride layer is formed by thermally growing an oxide layer under an atmosphere of nitric oxide and nitrous oxide. The oxynitride layer suppresses boron diffusion from the overlaying electrode.

Description

PROCESS FOR FORMING ULTRATHIN OXYNITRIDE LAYERS AND THIN LAYER DEVICES CONTAINING ULTRATHIN OXYNITRIDE LAYERS

TECHNICAL FIELD

The present invention relates to processes for forming ultrathin oxynitride layers

such as submicron dielectric layers and devices containing these layers; more specifically,

the present invention relates to oxynitride dielectric layers which reduce leakage currents in

MOS devices and which provide improved resistance to boron penetration from overlying

boron doped electrodes.

BACKGROUND OF THE INVENTION

There is increasing interest in semiconductor devices having gate dimensions less

than 0.25 micron such as the gates in MOS dual-gate integrated circuits. As will be

appreciated by those skilled in the art, devices with such small structures encounter obstacles

that are not serious problems in devices where the gate dimensions are greater than 1.0

micron. Most notably, these very small devices require submicron gate oxide layers,

typically from 30 angstroms to 70 angstroms in thickness. It has been found that the

performance of conventional gate dielectric layers formed of thermally grown silicon

dioxide is often less than ideal when fabricated in these submicron ranges. For example,

ultrathin SiO₂ layers typically have a high density of pinholes. Importantly, ultrathin SiO₂

layers have high boron permeability. As will be known by those skilled in the art, this

susceptibility to boron penetration can result in channel contamination. More specifically, boron from a p+ doped polysilicon gate electrode may penetrate the thin SiO₂ layer during

high temperature processing, thereby contaminating the underlying channel.

The ability to control the thickness of the ultrathin SiO₂ layers is a function of

growth rate. Conventional SiO₂ layers are usually grown at temperatures between 900 and

1000 degrees C or more. It is known that oxidation at these high temperatures is so rapid

that uniform film thickness is difficult to achieve. Moreover, if the process temperature is

reduced to gain greater control over the oxidation rate (for example, less than 900 degrees

C, the SiO₂ layers exhibit a significant increase in compressive stress that produces an

accumulation of electric charge at the semiconductor interface, leading to increased current

leakage.

In order to address the limitations of SiO₂ ultrathin films, oxynitride (Si_xO_yN_z)films

have been proposed for use as gate dielectrics. For example, it is known in the art that

silicon oxynitride films are less permeable to diffusing boron atoms than silicon dioxide

films.

One such prior art technique uses NH₃ for thermal nitridation of Si or SiO . ₂

Although the resultant films have some desirable properties when compared to SiO₂ films,

the hydrogen atoms produce a significant number of electron traps (which may be reduced

somewhat through reoxidation) and the films exhibit a fixed-charge build-up. There has also been some discussion in the prior art on the use of N₂O to produce

thin dielectrics by rapid thermal processing as well as in conventional furnaces. In the case

of N₂O nitridation of silicon (lightly doped with boron), it has been demonstrated that peak

nitrogen concentration is found in the SiO₂ at the SiO₂/Si interfacial region.

In addition, pure NO has been used for nitridation of SiO₂ in order to lower the

thermal budget required with nitridation using N₂O. In this process, higher concentrations

of nitrogen in the oxynitride layer were obtained than with the use of N₂O, presumably due

to complete disassociation of NO. Also, NO direct nitridation of silicon has been proposed

for the fabrication of gate dielectric layers comprising a layer of silicon oxynitride underlain

by a layer of silicon dioxide. These composite films may be made by thermally growing a

thin layer of silicon dioxide, and then forming a layer of silicon oxynitride or silicon nitride

by chemical vapor deposition (CVD).

In U.S. Patent No. 5,464,792, entitled, PROCESS TO INCORPORATE

NITROGEN AT AN INTERFACE OF A DIELECTRIC LAYER IN A

SEMICONDUCTOR DEVICE, there is disclosed a semiconductor device which includes

a substrate on which a first dielectric layer is formed on the substrate with a buffer layer

disposed on the first dielectric layer. The buffer layer is exposed to a nitrogen source and

nitrogen is diffused through the buffer layer and into the first dielectric layer to create a

region of high nitrogen concentration near an interface between the buffer layer and the first

dielectric layer. It is disclosed that either N₂O or NO can be used as the nitrogen source. Finally, the use of a mixture of NO and O₂ has been used to produce an oxynitride

layer in a semiconductor device. In United States Patent No. 5,512,519 entitled, METHOD

OF FORMING A SILICON INSULATING LAYER IN A SEMICONDUCTOR DEVICE,

there is provided a method of forming an insulating layer of a semiconductor device in

which an oxide layer having a preselected nitrogen concentration and also a preselected

thickness is prepared by independently regulating the flow rate of NO and O₂ gas into a

reaction chamber. This method is such that the NO and O₂ gas is supplied to the chamber

by regulating the gas flow while maintaining the inside of the chamber at a temperature of

about 750 to 1050 degrees C for a predetermined time, wherein nitrogen is included at the

Si/SiO₂ interface.

SUMMARY OF THE INVENTION

In one aspect the present invention provides a method of forming an insulating layer

in a semiconductor device. A substrate is provided having a silicon surface in the [100] or

[111] crystalline orientation. The silicon surface is prepared in the customary manner for

thermal growth of an oxide layer. The substrate is placed in a chamber which is purged prior

to oxide growth. A source of nitrous oxide and a source of nitric oxide are provided in

communication with the chamber. The substrate is heated to an appropriate temperature for

oxide formation. The two gases are metered into the chamber where they contact the

prepared silicon surface of the substrate. A reaction occurs at the silicon surface in which

a layer of oxynitride (Si_xO_yN_z) is formed on the silicon surface. The reaction is allowed to

proceed until the desired thickness of the oxynitride layer is achieved. In another aspect the present invention provides an improved semiconductor device

in which a gate oxynitride dielectric layer is provided having an unequal distribution of

nitrogen with the peak nitrogen concentration being present at the region of said layer

adjacent the gate electrode.

These and other aspects and advantages of the present invention will be more fully

appreciated in the following detailed description of the preferred embodiments of the

invention with reference to the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a flow diagram illustrating the steps of the present invention in one

embodiment.

Figure 2 is a diagrammatic view of an oxynitride layer made in accordance with the

present invention.

Figure 3 is a diagrammatic view of an MOS device which incorporates the oxynitride

layer of the present invention.

Figure 4 is a graph illustrating boron penetration and effectiveness of the barrier

properties of the present invention. Figure 5 is a graph illustrating interface state densities at various temperatures which

are a function of suppressed boron penetration.

Figure 6 is a graph illustrating charge-to-breakdown characteristics under -V stress.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS OF THE INVENTION

Referring now to Figure 1 of the drawings, the process of the present invention

begins in step 1 with the preparation of a substrate on which an oxynitride layer is formed.

In the most preferred embodiment the substrate is part of a semiconductor device, most

preferably a metal-oxide-semiconductor (MOS) device. The substrate includes a region of

silicon and will generally comprise a silicon wafer of orientation [100] or [111], i.e. single

crystal silicon. The preparation of the surface will follow customary procedures for

removing a native oxide in a reaction chamber.

Although the present invention is preferably used with a conventional semiconductor

fabrication furnace which includes a vacuum chamber having the usual gas ports, it is also

contemplated that the techniques disclosed herein can be used with Rapid Thermal

Processing (RPT) techniques.

Following preparation of the silicon substrate, the chamber is purged in step 2 prior

to introduction of the nitrogen-containing gases used to form the oxynitride layer. The purge gas may comprise an inert gas such as nitrogen or the chamber may be purged using the

novel nitrogen-containing gas mixture of the present invention.

In step 3, the prepared silicon substrate is heated to a temperature of at least about

700 degrees C, and more preferably from about 750 to about 1100 degrees C. As stated,

in the most preferred embodiment, the reaction chamber will comprise a conventional

semiconductor fabrication furnace. In step 4, the prepared surface is contacted with a

mixture of nitrous oxide (N₂O) and nitric oxide (NO) gases in the chamber. In order to

better control the growth characteristics of the oxynitride layer, the substrate is preferably

heated to reaction temperature, i.e. 750 to 1100 degrees C, prior to introduction of N₂O and

NO in the chamber.

In the present invention, N₂O constitutes from about 50 to about 95 percent by

volume of the gas mixture in the chamber and more preferably from about 70 to about 95

percent by volume at reaction temperature and pressure. NO constitutes from about 5 to

about 50 percent by volume of the gas mixture in the chamber and more preferably from

about 5 to about 30 percent by volume at reaction temperature and pressure. In the most

preferred embodiment, the mixture in the chamber contains from about 90 to about 95

percent by volume N₂O and from about 5 to about 10 percent by volume NO. That is, a

volumetric ratio of N₂O to NO of about 20 to 9 to about 9 to 5.

The N₂O and NO gas mixture is created in one of two ways. Most preferably the

N₂O and NO are metered into the chamber as separate gas streams through discrete gas ports. Alternatively, the two gases may be premixed and then introduced into the chamber

as a single gas stream. The flow rate of gas into the chamber may very, but preferably will

be from about 1000 to about 10,000 standard cubic centimeters per minute (SCCM) and

more preferably from about 1000 to about 5000 SCCM. The gas pressure within the

chamber during formation of the oxynitride layer is preferably from about 500 to about 760

torr. and more preferably form about 600 to about 760 torr. The gases used are high-purity,

i.e. 99.99% and above.

Under these conditions, an oxynitride layer begins to form having an overall

composition of silicon, oxygen and nitrogen, where the concentration of N is from about 0.5

to about 10% (atomic %) and more preferably from about 1 to about 5% (atomic %). The

reaction is not fully understood, but it has been determined that the process of the present

invention results in an oxynitride layer having multiple identifiable layers or regions with

different nitrogen concentrations as will be more fully described herein.

As stated above, the present invention is particularly useful in the preparation of the

gate dielectric layer of a MOS device. In the fabrication of a MOS device, the gate integrity

of the dielectric material is a key factor in determining the long term reliability

characteristics of the device. In a MOS transistor, the gate dielectric material must support

a substantial voltage difference between the gate electrode and the semiconductor substrate.

The gate dielectric material must also maintain its ability to support the voltage difference

between the gate and the substrate, while being subjected to the electron and hole injection

from both the gate electrode and the substrate. In the case of very-large-scale-integration (VLSI) devices, the effective gate lengths are on the order of less than 1 micron and often

less than .25 micron. At such small effective gate lengths, electrons can be injected into the

dielectric layer during periods when the transistor is switched on and off. The injection of

electrons into the dielectric material can, over time, cause a shift in the threshold voltage of

the transistor. Over an extended period of time, a continual shift in the threshold voltage

eventually results in an inability to switch the transistor on and off. Therefore, it is

important in the fabrication of a MOS transistor that a high quality dielectric material be

provided in order to insure long term reliability of the transistor.

Accordingly, in the present invention the reaction conditions are maintained until an

oxynitride layer of from about 30 to about 100 angstroms and more preferably from about

30 to about 50 angstroms is formed. In the preferred reaction temperature, the reaction will

be carried out for from about 1/2 to about 2 minutes and more preferably from about 1 to

about 1 1/2 minutes.

Referring to Figure 2 of the drawings, oxynitride layer 20 is shown as formed in

accordance with the present invention having three generally defined layers or regions, peak

nitrogen layer or gate interface region 22, bulk region 24 and channel interfacial region 26.

It is to be understood that these areas or regions have no precise lines of demarcation but

consist of gradual transitions based on nitrogen content. As stated, region 22 contains the

peak concentration of nitrogen (preferably from about 5 to about 10 atomic % and more

preferably from about 5 to about 7 atomic %) which provides a barrier against boron

migration from the overlying gate electrode. Bulk region 24 preferably has from about 2 to about 1 atomic % nitrogen. Region 26 preferably has from about 0.5 to about 0.1 atomic %

nitrogen. In an alternative embodiment of the present invention these regions are created

by ion implantation using nitrogen.

Referring now to Figure 3 of the drawings, the present invention is illustrated as

semiconductor device 30 which is shown as an n-channel MOS transistor. Therein, source

32 and drain 34 are shown formed as n+ doped regions in p type silicon wafer or body 36.

Channel 38 is defined underlying gate 40. Oxynitride layer 42 made in accordance with the

present invention is shown overlying channel 38 and electrically separating gate electrode

44 therefrom. Gate electrode 44, as stated, is preferably boron doped (p+) polysilicon.

Preferably, the microelectronic device made in accordance with the present invention is a

dual gate CMOS device. Most preferably the device is a surface channel p+ -poly gate

PMOSFET. For a general description of these types of devices (without the oxynitride layer

of the present invention) reference is made to "Design Tradeoffs Between Surface and

Buried-Channel FET's," IEEE Trans. Electron Devices. Vol. ED-32, p. 584, 1985, the entire

disclosure of which is incorporated herein by reference.

EXAMPLES

The following examples are provided to more fully illustrate the present invention

and are in no way intended to limit the full scope of the invention. P+-poly PMOS devices were fabricated on n-type Si (100) substrates. Gate oxides

(53 A) were grown at 900°C in pure 0₂ ambient. Some oxides received a short 15-second

NO anneal at 900°C. After undoped polysilicon deposition (-3000A), samples with and

without NO anneal received nitrogen implantation at 40KeV to a dose of 5xl0¹⁵cm^"2,

followed by a N₂ anneal for 30 minutes at 900°C to drive in nitrogen to the poly/SiO ₂

interface. BF₂ implantation was performed at 50KeV to a dose of 5xl0¹⁵cm ², followed by

dopant activation in N₂ for 30 minutes at 850 °C, 900°C, or 950°C. For reference, POCl₃-

doped n+-polysilicon gate MOS devices were fabricated on p-type (100) substrates

following the same process conditions. Three different nitrogen profiles in gate dielectrics

(confirmed by SIMS) were generated: nitrogen peak at the Si0₂/Si interface (NO annealed

Si0₂) [6], nitrogen peak at the poly/Si0₂ interface (N implant), and nitrogen peaks at the both

poly/Si0₂ and Si0₂/Si interfaces (combination of NO anneal and N implant). We have

compared the diffusion barrier properties, interfacial characteristics, and gate oxide

reliability on these devices.

Boron penetration and effectiveness of the barrier properties in the PMOS devices

are shown in Fig. 1. As can be seen, flatband voltage (V_FB) shift is suppressed in all the

oxynitride devices regardless of the N peak positions. The slight NO anneal (900°C, 15s)

produces a very effective diffusion barrier at the Si0₂/Si interface without suffering from

channel mobility degradation caused by nitrogen-induced fixed charges [6]. Devices with

a nitrogen peak at the poly/Si0₂ interface also exhibit enhanced immunity to boron

penetration, similar to observed in [7]. However, the best diffusion barrier is obtained by the "double N peaks", i.e., the combination of NO anneal and N implantation, for high

thermal budgets (e.g. 950°C).

Initial interface state density (D_it) is also much reduced in the oxynitride devices

compared to control devices due to suppressed boron penetration [8]. As shown in Fig. 2,

good interface properties after 900°C drive-in are obtained by any of the diffusion barriers.

At high drive-in temperature (950°C), however, boron penetration also occurs in oxynitride

devices except devices with "double N peaks", which exhibit superior immunity against the

creation of interface states (Fig.l). It is interesting to note the correlation between the

amount of B penetration and interface states density (Figs. 1 and 2). The formation of B-F

complexes increases D_it as well as weakens the Si0₂/Si interface structure, and is precursor

for the generation of interface states during subsequent electrical stress. Devices with B

penetration to the Si0₂/Si interface show significant distortion of the quasi-state C-V curves

after stressing (now shown), except the devices with double N peaks, in which B penetration

is completely suppressed.

The charge-to-breakdown characteristics under-V_g stress are shown in Fig. 3. As can

be seen, the gate dielectric reliability is significantly influenced by the nitrogen peak

position. Compared to control devices, QBD of oxynitride devices is improved by having

the diffusion barrier at the poly/Si0₂ interface and is degraded by having the diffusion barrier

at the Si0₂/Si interface. The additional diffusion barrier at the Si0₂/Si interface in double N-

peak devices does not further improve the oxide reliability; instead it slightly degrades QBD

(compared to the device containing only a N peak at the poly/Si0₂ interface). In contrast, QBD of NMOS devices with these dielectrics under-V_g stressing are comparable regardless

of the N peak position (not shown). As indicated by charge trapping study during constant

current stress (not shown), devices with more degraded QBD show higher charge trapping

[4], caused by the formation of B-F complexes in Si0₂ [9] pr creation of strained and broken

Si-0 bonds due to boron penetration [5].

Thus, it is apparent that there has been provided in accordance with the invention a

method and apparatus that fully satisfies the objects, aims and advantages set forth above.

While the invention has been described in connection with specific embodiments thereof it

is evident that many alternatives, modifications, and variations will be apparent to those

skilled in the art in light of the foregoing description. Accordingly, it is intended to embrace

all such alternatives, modifications and variations that fall within the spirit and broad scope

of the appended claims.

Claims

CLAIMSWhat is claimed is:

1. A method of forming an insulating layer in a semiconductor device, comprising

the steps of:

providing a substrate having silicon surface;

placing said substrate in a chamber;

heating said silicon surface to at least 750 degrees C;

flowing into said chamber gaseous nitric oxide and nitrous oxide such that said nitric

oxide and said nitrous oxide contact said heated silicon surface; and

maintaining said gases in contact with said heated silicon surface for a period

sufficient to form a layer of silicon dioxide having nitrogen distributed therein.

2. The method of forming an insulating layer in a semiconductor device recited

in claim 1 , wherein said nitric oxide and said nitrous oxide are supplied to said chamber at

a volumetric ratio of from about 20 to about 9 parts nitric oxide to about 9 to about 5 parts

nitrous oxide.

3. The method of forming an insulating layer in a semiconductor device recited in

claim 1, wherein said silicon surface is heated to from about 750 to about 1100 degrees C.

4. The method of forming an insulating layer in a semiconductor device recited

in claim 1, wherein said layer of silicon dioxide having said nitrogen distributed therein has

a thickness of less than about 1 micron.

5. The method of forming an insulating layer in a semiconductor device recited

in claim 1, wherein said layer of silicon dioxide having said nitrogen distributed therein is

a gate dielectric.

6. The method of forming an insulating layer in a semiconductor device recited

in claim 6, wherein said gate dielectric is present in a MOS device.

7. The method of forming an insulating layer in a semiconductor device recited

in claim 1, wherein said silicon dioxide layer has an interfacial region which forms at said

silicon surface, a bulk region which forms on said interfacial region and a top region which

forms on said bulk region and wherein said top region has a greater concentration of

nitrogen than said interfacial region and said bulk region.

8. The method of forming an insulating layer in a semiconductor device recited

in claim 1 , wherein a p+ doped gate is formed on said silicon dioxide layer.

9. The method of forming an insulating layer in a semiconductor device recited

in claim 7, wherein a boron doped gate is formed on said silicon dioxide layer, a channel is

formed below said silicon dioxide layer and wherein said interfacial region forms a barrier

against charge carriers traveling in said channel and said top region forms a barrier against

boron diffusion form said doped electrode.

10. The method of forming an insulating layer in a semiconductor device recited

in claim 1, wherein said nitric oxide and said nitrous oxide are flowed into said chamber as

independent streams.

11. The method of forming an insulating layer in a semiconductor device recited

in claim 1 , wherein said nitric oxide and said nitrous oxide are flowed into said chambers

a single combined stream.

12. The method of forming an insulating layer in a semiconductor device recited

in claim 1 , wherein said gases are flowed into said chamber at a flow rate of from about

1000 to about 10,000 SCCM.

13. The method of forming an insulating layer in a semiconductor device recited

in claim 1 , wherein said gases are maintained in contact with said silicon surface for from

about 14 to about 2 minutes.

14. The method of forming an insulating layer in a semiconductor device recited

in claim 1 , wherein said substrate is a silicon wafer.

15. The method of forming an insulating layer in a semiconductor device recited

in claim 1, wherein said heating step is carried out by infrared heating of said silicon surface

in rapid thermal processing.

16. The method of forming an insulating layer in a semiconductor device recited

in claim 1 , wherein said heating step is carried out in a furnace.

17. A method of forming an insulating layer in a semiconductor device,

comprising the steps of:

providing a substrate having a silicon surface;

placing said substrate in a sealed chamber;

purging said chamber;

heating said silicon surface to from about 750 to about 1100 degrees C;

flowing into said chamber gaseous nitric oxide and mtrous oxide such that said nitric

oxide and said nitrous oxide form a mixture having from about 50 to about 95 % by volume nitrous oxide and from about 5 to about 50 % by volume nitric oxide and such that said

mixture contacts said heated silicon surface; and

maintaining said gases in contact with said heated silicon surface for from about Vi

to about 2 minutes to form a layer of silicon dioxide having nitrogen distributed therein,

wherein said silicon dioxide layer has a thickness less than about 1.0 micron.

18. The method of forming an insulating layer in a semiconductor device recited

in claim 1 , wherein said silicon dioxide layer has an interfacial region which forms at said

nitrogen than said interfacial region and said bulk region.

19. The method of forming an insulating layer in a semiconductor device recited

in claim 5, wherein said gate dielectric is present in a MOS device.

20. In a semiconductor device of the type having at least one gate overlying a

channel, the improvement comprising an oxynitride dielectric layer disposed between said

gate and said channel wherein said oxynitride layer has an unequal distribution of nitrogen

and wherein said oxynitride layer has a peak nitrogen concentration in a region proximal to

said gate.