WO1998016011A1 - Zero power fuse circuit - Google Patents
Zero power fuse circuit Download PDFInfo
- Publication number
- WO1998016011A1 WO1998016011A1 PCT/US1997/017680 US9717680W WO9816011A1 WO 1998016011 A1 WO1998016011 A1 WO 1998016011A1 US 9717680 W US9717680 W US 9717680W WO 9816011 A1 WO9816011 A1 WO 9816011A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- terminal
- coupled
- potential
- fuse
- transistor
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356008—Bistable circuits ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
- H03K3/356182—Bistable circuits using complementary field-effect transistors with additional means for controlling the main nodes
Definitions
- the present invention generally relates to fuse circuits, and more specifically to zero static power fuse circuit architectures.
- Fuse circuits are frequently used in a variety of semiconductor applications. For example, as the storage density of semiconductor devices such as memory de- vices, programmable logic devices, and the like continue to increase, the incidence of defective cells within any one device is likely to increase as well. Unless the defect can be corrected in some way, the particular defective semiconductor device becomes useless, thus lower- ing production yields.
- a common approach to correcting such defects is to provide a multitude of redundant cells within the device. When a defective cell is detected, one of the redundant cells can be used in its place.
- the circuitry that supports the redundant cells usually includes fusible elements which are selectively
- Fuse circuits are also used to facilitate programming of programmable logic devices (PLD) .
- PLD programmable logic devices
- logic cells in a PLD are fabricated to have a default logic level, whether it be a logic HI or a logic LO. This is accomplished by the presence of fusible links which tie the cells' outputs either to V cc or to ground.
- fuse circuitry in PLDs When a fuse in a cell is blown, the cell's logic level is reversed. Not unlike the circuitry used with redundant memory cells, fuse circuitry in PLDs also consume power.
- a prior art fuse circuit such as one shown in Fig. 5.
- a resistor R is coupled in series with a fuse F, between V cc and ground.
- the node between the resistor and the fuse is fed into an inverter to provide an output Q.
- the intact fuse ties the inverter input to groun d, so that Q is HI.
- a constant current is drawn from V cc to ground, through the resistor and the fuse F.
- the inverter input is coupled to V cc and Q goes LO.
- any one of a number of such fuse circuits either is blown or remains intact.
- the fuse circuits which remain intact will always draw current from V cc , the power being dissipated through the resistor R. These fuse circuits are inefficient, especially when used in smaller computing devices such as portable PCs where power is a premium. What is needed is a fuse circuit which can be used in semiconductor devices that use programmable logic levels, and which does not consume power whether the fuse circuit remains intact or is blown.
- the fuse circuit of the present invention includes a dual-triggered unidirectional latch means.
- a "dual-triggered” latch is a latch that can be triggered through either one of two inputs.
- the latch is "unidirectional" in that the first input can trigger the latch only by a momentary contact of the first input to ground, and the second input can trigger the latch only by a momentary contact of the second input to V cc .
- the fuse circuit includes the above latch means coupled with two series connected fuse element and capacitor pairs. A first logic level is provided by the fuse circuit when both fuse elements remain intact.
- the fuse circuit includes the above-described latch means coupled to a pull-up transistor at a first terminal of the latch means, and a fuse/capacitor combination coupled to the second terminal of the latch means.
- a pull-down transistor is used in place of the pull-up transistor of the second embodiment.
- the capacitors serve to block DC current during the steady state condition when the fuse elements are intact.
- a first logic level is provided without any power dissipation through the fuse circuit.
- the capacitors provide a momentary coupling to ground or V cc when the circuit is powered up. This momentary contact is sufficient to operate the latch means, which reverses the logic levels. Since the latch draws essentially no power and the capacitors block DC current, there is virtually no power consumed in steady state when the fuse element is blown. Thus, whether the fuse element is blown or remains intact, the fuse circuit of the present invention operates with no static power dissipation.
- Fig. 1 is a first embodiment of a zero power fuse circuit of the present invention.
- Fig. 2 shows a second embodiment of a zero power fuse circuit of the present invention.
- Fig. 3 illustrates a third embodiment of a zero power fuse circuit of the present invention.
- Fig. 4 is a table which defines a dual-triggered unidirectional latch in accordance with the present invention.
- Fig. 5 shows a prior art fuse circuit.
- a zero power fuse cir- cuit 10 of the present invention includes a latch means 50 having two terminals A, B. Coupled to the A terminal is a series combination of a first fuse element F 1 and a first capacitor C 1 .
- the fuse element F is coupled to V cc and the capacitor C 1 is coupled to ground.
- Terminal B of the latch means 50 has a similar series combination of a second fuse element F 2 and a second capacitor C 2 .
- the second fuse element F 2 is coupled to ground while the second capacitor C 2 is coupled to V cc .
- the output logic Q, Q of the zero power fuse circuit 10 can be obtained from terminal A and terminal B, respectively.
- latch means 50 The operation of latch means 50 is defined by the table shown in Fig. 4. As can be seen from the table under the RESPONSE column, when triggered, the latch responds by latching terminal A to ground GND and latching terminal B to V cc .
- the latch means is triggered in one of two ways, as shown under the ACTION column of the table: either by contacting A to ground or by contacting B to V cc . Note that only a momentary contact is needed to trigger the latch means; e.g. momentarily contacting terminal A to ground is sufficient to trigger the latch means 50.
- the table in Fig. 4 further shows that contacting A to V cc or contacting B to ground results in an undefined response, meaning that the response of the latch does not matter.
- the latch means 50 hereinafter is defined as a dual-triggered unidirectional latch.
- the latch means is “dual-triggered” in the sense that the latch means 50 can be triggered by contacting A to ground or by contacting B to V cc .
- the latch means 50 is "unidirectional" in that each terminal latches in one direction; i.e. terminal A will always latch to ground and terminal B will always latch to V cc , when the latch is triggered.
- the latch means 50 includes a P-channel MOS transistor 52 cross-coupled with an N-channel MOS transistor 54. More specifically, the drain of the PMOS transistor is coupled to V cc and the source of the NMOS transistor is coupled to ground.
- the gate of the PMOS transistor 52 is coupled to the drain of the NMOS transistor 54, and the gate of the NMOS transistor is coupled to the source of the PMOS transistor. It is noted that any latch means circuitry which behaves in the manner as set forth in the table of Fig. 4 will work equally well in the zero power fuse circuit of the present invention.
- terminal A of the latch means 50 is tied to V cc and so the output Q is HI.
- terminal B is tied to ground so that the output logic of Q is LO.
- the PMOS transistor 52 is non-conductive.
- the NMOS transistor 54 is non-conducting since terminal B is at ground potential. The latch, therefore, is not triggered when the fuses are intact.
- terminal A When both fuse elements F 1 , F 2 are blown, terminal A will be momentarily coupled to ground through capacitor C 1 on power-up, pulling the gate of the PMOS transistor 52 to ground. At the same time, terminal B will be momentarily coupled to V cc through capacitor C 2 , thus pulling the gate of the NMOS transistor 54 to V cc . As the PMOS transistor becomes conductive, the gate of the NMOS transistor is pulled to V cc through the PMOS transistor. Likewise, as the NMOS transistor starts to conduct, the gate of the PMOS transistor is pulled to ground through the NMOS transistor. Consequently, terminal A latches to ground and terminal B is latched to V cc .
- the capacitors C 1 and C 2 both serve to block DC current from V cc to ground, and so no power is consumed through the two fuse element/capacitor pairs. Similarly, since neither the PMOS transistor nor the NMOS transistor is conducting when the fuse elements F, , F 2 are intact, no power is drawn through the transistors.
- the zero power fuse circuit of Fig. 1 therefore is able to provide both a HI and a LO logic level without consuming power.
- a fuse element F is coupled between terminal B of the latch means 50 and ground.
- a capacitor C is coupled between V cc and terminal B.
- a PMOS pull-up transistor 20 includes a source terminal coupled to V cc and a drain terminal coupled to terminal A of the latch means 50. The gate of the PMOS transistor is coupled to terminal B.
- a fuse element F is coupled between V cc and terminal A of the latch means 50.
- a capacitor C is coupled between terminal A and ground.
- An NMOS pull-down transistor 22 is coupled between terminal B of the latch and ground, through the source and drain pins of the NMOS transistor respectively. The gate of the NMOS transistor 22 is coupled to terminal A of the latch.
- terminal A is tied to V cc , and so Q is HI. Since terminal A is at V cc , the NMOS transistor 22 is conductive, thus pulling both terminal B and Q LO. When the fuse element F is blown, terminal A is momentarily coupled to ground through the capacitor C. Referring to the table in Fig. 4, a momentary contact of A to ground has the effect of latching terminal A to ground and latc- hing terminal B to V cc . Thus, Q goes LO and remains LO, and Q goes HI and remains HI. As with the embodiments of Figs. 1 and 2, there is no current draw through the circuit 14 in steady state, and therefore no power loss.
- the transistors used in the embodiments of Figs. 1 - 3 it is desirable to fabricate the devices using similarly sized device geometries, e.g. channel regions having the same width-to-length (W/L) ratios.
- W/L width-to-length
- This has the advantage of facilitating device layout since all of the devices are of similar size and configuration.
- the capacitors shown in the embodiments of Figs. 1 - 3 are constructed in accordance with the same criteria.
- Sensitivity to process variations is minimized by designing with similarly sized devices. Variations in the process which affect the geometry of the device will equally affect all of the devices, and so will not adversely impact the final product.
- the W/L ratio of the channel regions of the transistor devices is 3/1, but this is not critical.
- the invention works equally well with other W/L ratios.
- transistor switching speed is not a factor in the present invention. It is only when the zero power fuse circuit is powered up that transistor switching may take place, and then only for a short time. However, once the steady state condition is achieved, there is no further switching required of the transistors since the task of the zero power fuse circuit is to provide a constant logic level. Thus, the operating speed of the zero power fuse circuit of the present invention is not a concern.
- the capacitors are fabricated with the same W/L ratio so that size uniformity among the devices can be maintained.
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10514028A JP2000502511A (en) | 1996-10-07 | 1997-09-30 | Zero power fuse circuit |
EP97909915A EP0867070A4 (en) | 1996-10-07 | 1997-09-30 | Zero power fuse circuit |
KR1019980702469A KR19990044703A (en) | 1996-10-07 | 1997-09-30 | Zero power fuse circuit |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/726,956 | 1996-10-07 | ||
US08/726,956 US5731734A (en) | 1996-10-07 | 1996-10-07 | Zero power fuse circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1998016011A1 true WO1998016011A1 (en) | 1998-04-16 |
Family
ID=24920728
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1997/017680 WO1998016011A1 (en) | 1996-10-07 | 1997-09-30 | Zero power fuse circuit |
Country Status (7)
Country | Link |
---|---|
US (1) | US5731734A (en) |
EP (1) | EP0867070A4 (en) |
JP (1) | JP2000502511A (en) |
KR (1) | KR19990044703A (en) |
CN (1) | CN1196838A (en) |
TW (1) | TW355837B (en) |
WO (1) | WO1998016011A1 (en) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5689455A (en) * | 1995-08-31 | 1997-11-18 | Micron Technology, Inc. | Circuit for programming antifuse bits |
US6445605B1 (en) | 1997-07-11 | 2002-09-03 | Micron Technology, Inc. | Circuit for programming antifuse bits |
US6903991B2 (en) * | 1995-08-31 | 2005-06-07 | Micron Technology, Inc. | Circuit for programming antifuse bits |
US6147546A (en) * | 1998-03-11 | 2000-11-14 | International Business Machines Corporation | Zero volt/zero current fuse arrangement |
US5999038A (en) * | 1998-09-24 | 1999-12-07 | Atmel Corporation | Fuse circuit having zero power draw for partially blown condition |
US6191641B1 (en) | 1999-02-23 | 2001-02-20 | Clear Logic, Inc. | Zero power fuse circuit using subthreshold conduction |
US6566968B2 (en) | 1999-12-13 | 2003-05-20 | Broadcom Corporation | Oscillator having multi-phase complementary outputs |
US20020055112A1 (en) * | 2000-08-26 | 2002-05-09 | Nila Patil | Methods for reducing complexity of nucleic acid samples |
US6781437B2 (en) * | 2001-07-11 | 2004-08-24 | Infineon Technologies Aktiengesellschaft | Zero static power programmable fuse cell for integrated circuits |
US6839298B2 (en) * | 2001-07-11 | 2005-01-04 | Infineon Technologies Aktiengesellschaft | Zero static power fuse cell for integrated circuits |
US20050100911A1 (en) * | 2003-08-06 | 2005-05-12 | Perlegen Sciences, Inc. | Methods for enriching populations of nucleic acid samples |
JP5160164B2 (en) * | 2007-08-06 | 2013-03-13 | ルネサスエレクトロニクス株式会社 | Fuse circuit |
TWM351546U (en) * | 2009-03-30 | 2009-02-21 | Cheng Uei Prec Ind Co Ltd | Circuit for acquiring battery-protected signals |
CN103199836A (en) * | 2013-03-18 | 2013-07-10 | 西安华芯半导体有限公司 | Integrated circuit power source turn-off switch |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4613959A (en) * | 1984-01-06 | 1986-09-23 | Thomson Components-Mostek Corportion | Zero power CMOS redundancy circuit |
US4837520A (en) * | 1985-03-29 | 1989-06-06 | Honeywell Inc. | Fuse status detection circuit |
US5440246A (en) * | 1994-03-22 | 1995-08-08 | Mosel Vitelic, Incorporated | Programmable circuit with fusible latch |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4598388A (en) * | 1985-01-22 | 1986-07-01 | Texas Instruments Incorporated | Semiconductor memory with redundant column circuitry |
JPS63168900A (en) * | 1987-01-06 | 1988-07-12 | Toshiba Corp | Semiconductor memory |
JP2741022B2 (en) * | 1987-04-01 | 1998-04-15 | 三菱電機株式会社 | Power-on reset pulse generation circuit |
US5258958A (en) * | 1989-06-12 | 1993-11-02 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
JP2900451B2 (en) * | 1989-11-30 | 1999-06-02 | ソニー株式会社 | Memory device |
JPH0468562A (en) * | 1990-07-10 | 1992-03-04 | Nec Corp | Code setting circuit |
JPH0474015A (en) * | 1990-07-13 | 1992-03-09 | Mitsubishi Electric Corp | Semiconductor integrated circuit |
US5051691A (en) * | 1990-09-13 | 1991-09-24 | Samsung Semiconductor, Inc. | Zero power dissipation laser fuse signature circuit for redundancy in vlsi design |
US5315177A (en) * | 1993-03-12 | 1994-05-24 | Micron Semiconductor, Inc. | One time programmable fully-testable programmable logic device with zero power and anti-fuse cell architecture |
US5457656A (en) * | 1994-08-17 | 1995-10-10 | United Microelectronics Corp. | Zero static power memory device redundancy circuitry |
-
1996
- 1996-10-07 US US08/726,956 patent/US5731734A/en not_active Expired - Lifetime
-
1997
- 1997-09-30 KR KR1019980702469A patent/KR19990044703A/en not_active Application Discontinuation
- 1997-09-30 WO PCT/US1997/017680 patent/WO1998016011A1/en not_active Application Discontinuation
- 1997-09-30 EP EP97909915A patent/EP0867070A4/en not_active Withdrawn
- 1997-09-30 JP JP10514028A patent/JP2000502511A/en active Pending
- 1997-09-30 CN CN97190782A patent/CN1196838A/en active Pending
- 1997-10-03 TW TW086114434A patent/TW355837B/en active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4613959A (en) * | 1984-01-06 | 1986-09-23 | Thomson Components-Mostek Corportion | Zero power CMOS redundancy circuit |
US4837520A (en) * | 1985-03-29 | 1989-06-06 | Honeywell Inc. | Fuse status detection circuit |
US5440246A (en) * | 1994-03-22 | 1995-08-08 | Mosel Vitelic, Incorporated | Programmable circuit with fusible latch |
Non-Patent Citations (1)
Title |
---|
See also references of EP0867070A4 * |
Also Published As
Publication number | Publication date |
---|---|
EP0867070A4 (en) | 1999-07-14 |
TW355837B (en) | 1999-04-11 |
US5731734A (en) | 1998-03-24 |
EP0867070A1 (en) | 1998-09-30 |
KR19990044703A (en) | 1999-06-25 |
CN1196838A (en) | 1998-10-21 |
JP2000502511A (en) | 2000-02-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR0147194B1 (en) | Semiconductor memory device | |
US5731734A (en) | Zero power fuse circuit | |
US6064229A (en) | Voltage translating buffer based on low voltage technology | |
KR100262936B1 (en) | Non-volatile memory which is programmable from a power source | |
US7605636B2 (en) | Power gating structure, semiconductor including the same and method of controlling a power gating | |
US4621346A (en) | Low power CMOS fuse circuit | |
US6205077B1 (en) | One-time programmable logic cell | |
US7030643B2 (en) | Output buffer circuits including logic gates having balanced output nodes | |
US6381181B1 (en) | Timing independent current comparison and self-latching data circuit | |
KR960702698A (en) | Electronic circuits (CMOS input with Vcc compensated dynamic threshold) | |
KR19980058197A (en) | Output pad circuit using control signal | |
KR100560343B1 (en) | Fuse circuit having zero power draw for partially blown condition | |
JP3497000B2 (en) | Semiconductor circuit | |
US6040734A (en) | Supply voltages switch circuit | |
EP0417895B1 (en) | Voltage level translation circuit | |
JP4620480B2 (en) | Semiconductor device | |
US6891419B2 (en) | Methods and apparatus for employing feedback body control in cross-coupled inverters | |
KR100464944B1 (en) | A fuse set of redundancy circuit in semiconductor memory device | |
EP0320779A2 (en) | Sense amplifier | |
US5212413A (en) | Stable, programmable low-dissipation reference circuit | |
US20030234665A1 (en) | Anti-fuse sense amplifier | |
US6230275B1 (en) | Circuit for powering down unused configuration bits to minimize power consumption | |
KR100275729B1 (en) | Semiconductor device having zapping circuit | |
KR0177772B1 (en) | Label defining circuit for unused i/o pin | |
JPH09161486A (en) | Semiconductor integrated circuit device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 97190782.X Country of ref document: CN |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1997909915 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1019980702469 Country of ref document: KR |
|
ENP | Entry into the national phase |
Ref document number: 1998 514028 Country of ref document: JP Kind code of ref document: A |
|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): CN DE GB JP KR |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWP | Wipo information: published in national office |
Ref document number: 1997909915 Country of ref document: EP |
|
REG | Reference to national code |
Ref country code: DE Ref legal event code: 8642 |
|
WWP | Wipo information: published in national office |
Ref document number: 1019980702469 Country of ref document: KR |
|
WWW | Wipo information: withdrawn in national office |
Ref document number: 1997909915 Country of ref document: EP |
|
WWW | Wipo information: withdrawn in national office |
Ref document number: 1019980702469 Country of ref document: KR |