WO1998007189A1

WO1998007189A1 - Semiconductor trench isolation structure having improved upper surface planarity

Info

Publication number: WO1998007189A1
Application number: PCT/US1997/009426
Authority: WO
Inventors: Fred N. Hause; Charles E. May; Sabhash Gupta
Original assignee: Advanced Micro Devices, Inc.
Priority date: 1996-08-13
Filing date: 1997-05-29
Publication date: 1998-02-19

Abstract

An isolation technique is provided for improving the overall planarity of a fill dielectric upper surface. The fill dielectric is one used in a shallow trench process, whereby the fill dielectric is deposited within shallow trenches used in isolating active devices formed in silicon mesas. The fill dielectric is planarized by selectively removing the fill dielectric prior to chemical-mechanical polish. The fill dielectric is removed in elevationally raised regions described as those which reside essentially above the silicon mesas. A mask material is used opposite that which forms the shallow trenches. The mask material protects the shallow trenches and exposes fill dielectric directly above the silicon mesas. The fill dielectric is removed using a dry isotropic etch process to remove as much of the elevationally raised fill dielectric as possible. Once the fill dielectric is selectively removed, CMP can be more optimally performed on the remaining upper surface to achieve a surface which is substantially planar across the entire semiconductor wafer.

Description

TITLE: SEMICONDUCTOR TRENCH ISOLATION STRUCTURE HAVING IMPROVED

UPPER SURFACE PLANARITY

BACKGROUND OF THE INVENTION

Field of the Invention

This invention relates to semiconductor fabrication and more particularly to an improved method of planarizing fill dielectric used in a shallow trench process. The improved method entails removing fill dielectric above active regions while retaining fill dielectric above field regions prior to chemical-mechanical polish (CMP). CMP applied to the selectively removed fill dielectric provides for a more globally planarized fill dielectric regardless of the underlying topography.

2. Description of the Relevant Art

The fabrication of an integrated circuit involves placing numerous devices in a single semiconductor substrate. Select devices are interconnected by a conductor which extends over a dielectric which separates or "isolates" those devices. Implementing an electrical path across a monolithic integrated circuit thereby involves selectively connecting isolated devices. When fabricating integrated circuits it must therefore be possible to isolate devices built into the substrate from one another. From this perspective, isolation technology is one of the critical aspects of fabricating a functional integrated circuit. A popular isolation technology used for an MOS integrated circuit involves the process of locally oxidizing silicon. Local oxidation of silicon, or LOCOS process involves oxidizing field regions between devices. The oxide grown in field regions are termed field oxide, wherein field oxide is grown during the initial stages of integrated circuit fabrication, before source and drain implants are placed in device areas or active areas. By growing a thick field oxide in isolation (or field) regions pre-implanted with a channel-stop dopant, LOCOS processing serves to prevent the establishment of parasitic channels in the field regions.

While LOCOS has remained a popular isolation technology, there are several problems inherent with LOCOS. First, a growing field oxide extends entirely across the field region and laterally as a bird's-beak structure. In many instances, the bird's-beak structure can unacceptably encroach into the device active area. Second, the pre-implanted channel-stop dopant oftentimes redistributes during the high temperatures associated with field oxide growth. Redistribution of channel-stop dopant primarily affects the active area periphery causing problems known as narrow-width effects. Third, the thickness of field oxide causes large elevational disparities across the semiconductor topography between field and active regions. Topological disparities cause planarity problems which become severe as circuit critical dimensions shrink. Lastly, thermal oxide growth is significantly thinner in small field (i.e., field areas of small lateral dimension) regions relative to large field regions. In small field regions, a phenomenon known as field-oxide-thinning effect therefore occurs. Field-oxide-thinning produces problems with respect to field threshold voltages, interconnect-to-substrate capacitance, and field-edge leakage in small field regions between closely spaced active areas

Many of the problems associated with LOCOS technology are alleviated by an isolation technique known as the "shallow trench process" Despite advances made to decrease bird's-beak, channel-stop encroachment and non-planarity, it appears that LOCOS technology is still inadequate for deep submicron MOS technologies The shallow trench process is better suited for isolating densely spaced active devices having field regions less than, e g , one micron in lateral dimension

The trench process involves the steps of etching a silicon substrate surface to a relatively shallow depth, e g , between 0.2 to 0 5 microns, ana then filling the shallow trench with a deposited dielectric (referred to henceforth as "fill dielectric^") Some trench processes include an interim step of growing oxide on trench walls prior to the trench being filled After the trench is filled, it is then planaπzed to complete the isolation structure The trench process eliminates bird^'s-beak and channel-stop dopant redistribution problems In addition, the isolation structure is fully recessed, offering at least a potential for a planar surface Still further, field-oxide thinning in narrow isolation spaces does not occur and the threshold voltage is constant as a function of channel width

While the trench isolation process has many advantages over LOCOS, it cannot in all instances achieve complete global planaπzation across the entire semiconductor topography The upper surface of fill dielectric in large isolation areas are generally at lower elevationai levels than the upper surface fill dielectric in small isolation areas The fill dielectric readilv deposits in small area trenches such that the elevation of the fill dielectric in a small area trench is greater than the elevation within a large area trench Accordingly, subsequent processing is needed to bring the small trench fill topography to the same elevationai level as the large trench area fill topography

Most researchers have focused upon fairly complex processes for planaπzing large and small area fill dielectrics Those processes generally involve rework of the fill dielectric A popular rework technique involves depositing a sacrificial layer across the fill dielectric topography and then removing the sacrificial layer at the same etch rate as the underlying dielectric Generally, the sacrificial laver is deposited as a low-viscosity liquid

Baking the liquid, or exposing it to ultraviolet light, causes the liquid to convert to solid form in a sol-gel reaction

Popular sacrificial materials include photoresist, polyimide or spin-on glass (SOG) I he sacrificial layers generally etch back in a plasma until the topmost regions of the fill dielectric are exposed The etch chemistry is then modified so that the sacrificial layer material and the underlying fill dielectric are etched at approximately the same rate The etch is continued until all of the sacrificial layer has been etched away, leaving a somewhat planar fill dielectric upper surface

The sacrificial etchback technique is generally valid only tor planaπzation of topographies having features spaced less than 10 μm (microns) apart For large regions between trenches, the step height will not be reduced, since the sacrificial layer thickness on top of such features will be the same as the thickness over the adjacent trench In an effort to eliminate the complex deposition and etch processes involved with using the sacrificial technique, many manufacturers have directed their attention to chemical-mechanical polishing (CMP). Application of a chemical slurry and an abrasive polishing pad across the entire semiconductor topography, allows planarization of that topography commensurate with the planaπty of the pad surface. Unfortunately, however, when force is applied to a pad. the pad will oftentimes conform to the unevenness of that topography. Thus, while high elevation areas, or peaks, receive substantial polishing, low elevationai areas (or valleys) are also abraded.

A better understanding of the problems inherent with CMP are illustrated in reference to Figs. 1 and 2. Fig I depicts a partial cross-section of a semiconductor topography 10 Topography 10 includes a substrate 12 which has been fashioned with a small area trench 14 and a large area trench 16 according to the trench isolation process. Trenches 14 and 16 define field areas between active regions, wherein active regions are defined as silicon mesas 18 which extend upward from an elevation equivalent to the trench base. Deposited across trenches 14/16 and silicon mesas 18 is a fill dielectric 20.

Fig. 2 illustrates a processing step subsequent to that shown in Fig. I Specifically, the upper surface of fill dielectric material 20 receives CMP The polishing pad inherently flexes or conforms under pressure to the upper surface of dielectric 20, causing the polishing pad to attack and remove dielectric 20 upper surface in large area trench 16, albeit to a lesser degree than the removal of dielectric 20 in small area trench 14 If dielectric in large area trench 16 is not sufficiently thick to withstand the attack, the dielectric upper surface will be removed below the desired planar elevation. Thus, a slight recess of dielectric 20 upper surface occurs at the conclusion of CMP That recess is shown as reference numeral 22. If not properly protected with sufficient overlying material, mesa upper surfaces, corner or sidewalls may also show erosion due to CMP

A need therefore exists in producing a process which can utilize the advantages of the shallow trench isolation technique but without the inherent problems associated with sacrificial etchback or CMP. A process must be formulated which can achieve complete global planarization of the fill dielectric surface above both large area trenches and small area trenches. The desired process must also be one which can planaπze fill dielectric regardless of the underlying silicon mesa area (i.e., achieve planarization in regions above mesas of either large of small area).

Global planarization is hereby defined as the degree by which planarization is achieved across an entire semiconductor wafer topography. That degree is quantifiable and is derived from a process which can planarize the fill dielectric upper surfaces across the entire wafer topography with relatively small elevationai disparity in the resulting fill dielectric upper surface.

Fabrication of high density integrated circuits require elevationai uniformity of the fill dielectric surface regardless of the elevationai disparity of underlying features. If some degree of global uniformity is not achieved, then step coverage and depth of focus problems may result. Further, uneven planarization may affect the electrical parameters within and below the fill area. For example, local thinning of the fill region may result in an inappropriate amount of dopant beneath the fill dielectric possibly resulting in field inversion. Thus, planarization is desired even if significant elevationai disparity occurs between raised mesas or recessed trenches. Planaπty is also needed if the underlying topological area entails large area trenches/mesas (e g , greater than 2 0 microns per side) or small area trenches/mesas (e g , less than 1 0 microns per side)

A need therefore exists for planaπzing a fill dielectric upper surface commensurate with the elevation of all other fill dielectric surfaces, including those which reside over silicon mesas or isolation trenches The desired process must be one which does not over etch the fill dielectric surface to an elevation lower than an adjacent mesa upper surface If overetching occurs, then the mesa upper surface, comer and a portion of the silicon mesa sidewall will be partially exposed Any exposure of the silicon mesa surface, corner or sidewall causes inappropriate fringing field effects and or parasitic sidewall conduction It is therefore important when choosing a planarization method, that the method not expose portions of the silicon mesa in the process

SUMMARY OF THE INVENTION

The problems outlined above are in large part solved by an improved shallow trench process of the present invention The shallow trench process hereof demonstrates substantially global planarization of fill dielectric above relatively large and small trench regions as well as large and small silicon mesas A silicon mesa upper surface corner and sidewall areas are protected during planarization of the fill dielectric while ensuring sufficient fill dielectric in regions above those critical areas

The improved shallow trench process hereof achieves substantially global planarization by using a masking step More specifically, fill dielectric in large and small area trenches are protected by a photoresist, leaving fill dielectric above active areas (silicon mesas) exposed Lxposure of fill material above the silicon mesas affords select removal of material only in elcvationallv raised regions Bv masking the recessed regions and exposing the raised regions target areas of fill dielectric are advantaeeousiv removed prior to chemical- mechanical polish (CMP)

Masking of the trench isolation regions is performed by generating a mask which is opposite the mask used in producing the trenches Instead of protecting silicon mesas usinu a shallow trench mask, the planaπzing (i e , generated) mask protects the trenches and more particularly the fill dielectric in those trenches Generation of the mask is therefore readily achieved as a reverse of the mask used in producing the shallow trench Alternatively, or in addition to reversing the trench mask, the planaπzing mask can be formed above large trench areas thereby avoiding use of a planaπzing mask above small trenches Etching the non-masked fill dielectric is performed using an isotropic etch Advantageously, the isotropic etch is a dry (or plasma) isotropic etch The dry isotropic etch proves beneficial in removing a larger quantity of fill dielectric in elevationally raised areas

The dry isotropic etch is chosen over a wet isotropic etch using, e g , HF, for several reasons First, relative to wet isotropic etch, dry isotropic etch is less likely to jeopardize the photoresist/fill dielectric juncture Second, dry isotropic etch is less likely to attack the fill dielectric "seam at the midline above spaced silicon mesas In some instances, wet etch causes separation of the photoresist from the fill dielectric upper surface This phenomenon is generally referred to as photoresist "lifting" and is most prevalent at the etch sidewall just beneath the photoresist Lifting of photoresist provides a conduit of etch along the fill dielectric surface, resulting in topological disparities once the photoresist is stripped Moreover etch along the fill dielectric surface can, in the extreme, progress toward the seam area If the etchant reaches the seam it can deleteπously etch at a faster rate along the seam and toward the underlying topography The faster etch rate along the seam can cause further topological disparity of the fill dielectric This disparity is readily apparent when comparing the fill dielectric surface above the seam to the surface laterally spaced from the seam For the above reasons, wet isotropic etch is to be avoided if topological uniformity of the fill dielectric is desired

Similar to wet isotropic etch, dry amsotropic etch should also be avoided Anisotropic etch leaves unduly large amounts of fill dielectric in elevationally raised areas, primarily above closely spaced silicon mesas Anisotropic etch does not sufficiently etch in lateral directions necessary to remove beneath the photoresist and along raised regions of fill dielectric surface If the etch step utilizes anisotropic etch, then the quantity of fill dielectric in elevationally raised regions is too great to be removed commensurate with fill dielectric in elevationally recessed regions The present CMP process thereby utilizes a dry isotropic etch which has the benefits of removing sufficient quantity of fill dielectric in raised regions but without the disadvantage of photoresist lifting or seam over etch Dry isotropic etch thereby serves to optimally condition the fill dielectric surface so that CMP can be globally applied To ensure CMP success in globally pianaπzmg the fill dielectric surface, large elevationally raised regions are intermittently fashioned using the dry isotropic etch step The smaller upper surfaces formed by the etch step are more susceptible to CMP removal than if the large areas remained The small areas do not unduly cause flexure of the CMP pad like large areas would The result of select, spaced removal using dry isotropic etch followed by CMP, provides a fill dielectric upper surface which is globally planaπzed regardless of the underlying topography It may be possible that if dry isotropic etch is optimally performed, then global planarization may be achieved in certain circumstances without having to perform CMP

Broadly speaking, the present invention contemplates a method for forming a planaπzed fill dielectric upper topography The method comprises removing portions of a semiconductor substrate to form a pair of isolation trenches within the semiconductor substrate A pair of isolation trenches are laterally spaced from each other by an active region A fill dielectric is then deposited within and between the pair of isolation trenches Thereafter, the fill dielectric is isotropically etched from a plasma source in areas above the active region A chemical-mechanical removal step is then applied to the fill dielectric remaining in the areas above the active region such that the fill dielectric upper surface is removed to an elevation level commensurate with the fill dielectric within the pair of isolation trenches The present invention further contemplates a method for forming a field dielectric The method comprises providing a silicon substrate having an active region bounded by a pair of field regions A trench is formed within the field region, and a fill dielectric is deposited within the trench and upon the active region At least a portion of the fill dielectric above the active region is isotropically removed while the fill dielectric within the trench is retained A CMP process comprising an abrasive pad and a chemical slurry, is applied to the fill dielectric above the active region so as to cause a resulting fill dielectric upper surface commensurate with the fill dielectric within the trench According to one embodiment, the fill dielectric comprises a chemical vapor deposited oxide. According to another embodiment, portions of the semiconductor substrate are removed to form the isolation trench or trenches using a photolithography spin-expose-develop-etch sequence. The trenches are preferably formed within the field regions to a depth between, e.g., 0.2 to 0.5 μm. Preferably, the fill dielectric is deposited within the trench to a thickness exceeding the depth of the trench.

Isotropic etching is defined as an etch step which can proceed in several directions at the same rate. Isotropic etching can thereby occur along three dimensions defined as being perpendicular and non-perpendicular to the fill dielectric upper surface. Thus, isotropic etching is one which can occur along a vertical and horizontal axes, and proceeds along vectors formed by these axes at substantially the same etch rate. According to one embodiment, isotropic etching can be designed to occur at a faster rate in a lateral direction than the rate in a direction perpendicular to the etch surface. Conversely, anisotropic etching is any etching that is not isotropic. Anisotropic etching proceeds primarily in one direction, e.g., along a vertical axis and essentially does not proceed along a horizontal axis. Thus, the etch rate of an anisotropic etch along, for example, a vertical axis is substantially greater than the etch rate along a horizontal axis.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which:

Fig. 1 is a partial cross-sectional view of a semiconductor topography having fill dielectric deposited upon and between silicon mesas formed according to a conventional shallow trench process;

Fig. 2 is a process subsequent to that of Fig. 1 , wherein the upper topography of fill dielectric is removed to uneven planarization levels according to a conventional planarization process;

Fig. 3 is a partial cross-sectional view of a semiconductor topography with photoresist applied across a topography according to an exemplary embodiment of the present invention;

Fig. 4 is a processing step subsequent to Fig. 3, wherein the photoresist is patterned and isolation trenches are formed into the semiconductor substrate leaving silicon mesas between the trenches;

Fig. 5 is a processing step subsequent to Fig. 4, wherein a fill dielectric is formed entirely across the isolation trenches and silicon mesas;

Fig. 6 is a processing step subsequent to Fig. 5, wherein the photoresist layer and underlying fill dielectric are selectively removed using a dry isotropic etch according to the present invention; Fig 7 is a processing step subsequent to Fig 6, wherein the fill dielectric topography is shown after the photoresist is removed,

Fig 8 is a processing step subsequent to Fig 7, wherein a CMP is applied to the fill dielectric topography,

Fig 9 is a processing step subsequent to Fig 5, wherein a photoresist layer and underlying fill dielectric are selectively removed using a dry anisotropic etch, and

Fig 10 is a processing step subsequent to Fig 9, wherein a CMP is applied to the fill dielectric topography resulting in less than preferred planarization of the fill dielectric upper surface

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling withm the spirit and scope of the present invention as defined by the appended claims

DETAILED DESCRIPTION OF THE INVENTION

Turning now to the drawings, Fig 3 is a partial cross-sectional view of a semiconductor topography 30 Topography 30 includes a substrate 32, upon which a protective layer 34 is formed Deposited across the entire protective layer is a photoresist layer 36 Substrate 32 is preferably made from a single crystal silicon Protective layer 34 comprises any layer which protects the silicon surface from etch materials and/or oxidation Preferably, protective layer 34 includes a nitrogen species, such as silicon nitride, or silicon nitride deposited upon an oxide Photoresist 36 includes any material which can selectively polymerize when exposed to ultraviolet light Topography 30 can include any topography from which an integrated circuit such as metal oxide semiconductor (MOS) is fashioned

Fig 4 illustrates a processing step subsequent to Fig 3 Specifically, a pattern is printed upon photoresist 36, and select regions are exposed and developed The polymerized regions of photoresist 36 are represented as reference numerals 38 Polymerized photoresist 38 protects the underlying material from etchant Some of the areas protected by photoresist 38 include active regions 40 Active regions 40 represent areas where transistors will be formed, and are generally designated in areas exclusive of field regions 46 Field regions are defined as regions of a semiconductor substrate which receive isolation trenches Field regions do not contain active devices All active devices (e g , transistors, etc ) are formed withm active regions 40, i e , withm silicon silicon mesas 44 The patterned photoresist allow etchant to remove between, e g , 0 2 to I 0 microns of substrate material 32 The removed reg'ons are designated as trenches 45 formed exclusively in field regions 46 What remains of substrate 32 after trenches 45 are formed is a spaced plurality of silicon silicon mesas 44 Silicon silicon mesas 44 reside exclusively in active regions 40 The lateral dimensions of silicon silicon mesas 44 are defined by the size and quantity of various devices placed therein Similarly, the lateral dimensions of trenches 45 depend upon substrate area and the amount of isolation needed between silicon silicon mesas 44 It is the upper surface of silicon mesas 44 which receive source and drain implants, as well as gate oxides and various other topographies useful in the formation of MOS devices Fig 5 illustrates a step subsequent to Fig 4, wherein a fili dielectric 50 is deposited across the upper topography of Fig 4 Fill dielectric 50 resides within trenches 45 as well as above the photoresist-stripped silicon mesas 44 According to one embodiment, fill dielectric 50 comprises an oxide The oxide is preferably deposited from a chemical vapor deposition (CVD) chamber which, if desired, can be plasma enhanced or pumped down to a low pressure The oxide material is suitably derived from a silane or tetraethyl orthosilicate (TEOS) source By doping the source material, a PSG or BPSG film can be produced, possiblv from a spin-on source

In large aspect-ratio spaces, a seam 52 readily appears Seam 52 is the result of deposited fill dielectric 50 meeting near the midline between small area trenches 45a Thus, seam 52 forms when fill dielectric 50 sidewalls meet as a result of a geometric tunction of the trench depth, trench width, fill thickness amount, and the fill conformality characteristic Careful attention must be paid to the location of seam 52 when performing subsequent etch operations

Fig 6 illustrates an isotropic etch according to a preferred embodiment of the present invention Isotropic etch is performed upon fill dielectric 50 in regions exposed to the etchant Thus, a photoresist 54 is used Photoresist 54 is selectively removed to expose fill dielectric 50 onlv in regions directly above silicon mesas 44 Accordingly, the mask used in patterning photoresist 54 is of opposite poiaπty to the mask used in forming trenches 45 Alternatively, photoresist 54 can be of opposite polarity to photoresist 36, whereby the same photomask used in forming trench 45 can be used to form openings 56

ITie side profile of polymerized photoresist 54, between openings 56, aligns directly above the sidewalls of silicon mesas 44 During a subsequent etch, fill dielectric 50 is removed at substantially the same rate in all directions beneath opening 56 such that sidewall 57 of fill dielectric 50 extends laterally from the silicon mesa sidewall Accordingly, the etch used in Fig 6 is an isotropic etch and, more specifically, an isotropic etch performed from a plasma source, often referred to as "glow discharge" The etch process is carried forth preferably in a fluorocarbon-containing plasma, using an etch gas comprising, e g , nitrogen-trifluoπde (NF₃) Other etch gases, such as SF₆ may also be used, for example If desired, oxygen or hydrogen may be added to the fluorocarbon material to change the etch rate or the selectivity to underlying films, such as silicon The etch chamber used in producing a dry etch plasma, resulting in an isotropic etch, is one which is purposefully configured not to involve substantial ionic bombardment The preferred etching process is therefore primarily chemical An etch configuration useful in producing such a result can be taken for example, from various barrel, downstream, non-charged parallel plate reactors Regardless of the etch species or the reactor configuration, the result is one whereby an isotropic etch is performed The isotropic etch demonstrates substantially uniform etch rate in all dimensions emanating from the exposed regions 56 The isotropic etch is chosen as a dry etch to prevent lifting of photoresist 54 in area 58 and to prevent attach upon seam 52

According to one embodiment, dry isotropic etch can be carried out in a LAM Corporation model 4520ι downstream plasma etcher with a 13 56 MHz RF source (downstream plasma systems with RF sources dissimilar from 13 56 MHz are likely to perform as well) The etchant gas is preferably NF₃ introduced at 100 to 900 seem, wherein NF, is mixed with He introduced at 100 to 500 seem The wall of the isotropic chamber is maintained at a temperature between 30-60°C during the etch process The paddle temperature (l e , the temperature of the receptacle upon which the wafer resides) is maintained between 60-100°C The etchant RF power is held approximately at 500 to 950 watts during times in which the process pressure was maintained between 1300 to 2100 mtorr Good etch uniformity (within 5% having a 3 delta variance) is achieved at an etch rate of approximately 4500 angstroms/minute as a result of the following parameters NF, flow of 500 seem. He flow of 200 seem, pressure of 1700 mtorr, wall temperature of 40°C, paddle temperature of 90°C. and RF power of 750 watts Fig 7 illustrates the resulting upper surface 60a of fill dielectric 50 after removal of photoresist 54 As shown, the dry etch species prevents photoresist separation from the fill dielectric and over etch along seam 52 The integrity of upper surface 60a directly above seam 52 is thereby retained so as not to exacerbate its preexisting topological disparity

Fig 8 illustrates a processing step subsequent to Fig 7, wherein chemical-mechanical polish (CMP) is applied to upper surface 60 by selectively removing fill dielectric 50 in raised regions using a pre-conditioning etch step CMP shown in Fig 8 is more effective in producing a more globally planaπzed fill dielectric surface Flexure of a CMP pad from raised regions of upper surface 60a is minimized by breaking up the raised surface area with the isotropic etch hereof Removing as much of the raised surface is possible without attacking seam 52 is thereby a primary objective of the present invention More importantly, removal along spaced intervals so as to separate the raised surface into a plurality of smaller area surfaces proves beneficial in optimizing CMP As a process, CMP is more attuned to removing small area, spaced surfaces rather than large area surfaces CMP proves useful in removing intermittently raised surfaces (I e raised surface above density-spaced silicon mesas 44 and the raised surface above small area trenches 45a)

Fig 8 illustrates substantially global planarization achieved by CMP CMP is continued for a pre- determined time duration Thus, time duration is deemed the end point etch determinant In a subsequent processing step (not shown) protective layer 34 can be removed to leave the upper surface of silicon mesas 44 intact More importantly, CMP does not expose the upper surface, corner or sidewall, of any silicon mesa 44 Problems involved in exposing those regions is thereby eliminated by the present process

Fig 9 illustrates a non-preferred anisotropic etch used in lieu of the isotropic etch shown in Fig 6 More specifically, Fig 9 illustrates a step subsequent to Fig 5, whereby exposed regions 56 of fill dielectric 50 are removed using a dry anisotropic etch as opposed to a dry isotropic etch The dry anisotropic etch results in leaving a greater portion of fill dielectric in raised regions Since anisotropic etch does not afford lateral spreading at an etch rate substantially equivalent to the vertical etch rate, fill dielectric 50 in regions above small area, closely spaced silicon mesas 44 remain The remaining fill dielectric in the raised regions make CMP more difficult

As shown in Fig 10, CMP applied after the processing step of Fig 9 results in less than complete global planarization In fact, the added fill material between closely spaced silicon mesas causes undue flexure of the CMP pad When the pad flexes, or when CMP is terminated after a set time period, sufficient amounts of fill dielectric remain above and between closely spaced silicon mesas 44 That fill dielectric cannot be removed using CMP since fill dielectric between sparsely spaced silicon mesas will be unduly removed Accordingly, while a anisotropic etch is preferred over conventional planarization processes, which do not use a pre-existing etch prior to CMP, anisotropic etch is not as preferred as dry isotropic etch Additionally, dry isotropic etch is preferred over wet isotropic etch and the photoresist lifting and seem etch problems associated therewith

It will be appreciated to those skilled in the art having the benefit of this disclosure that this invention is capable of applications with numerous types of MOS-processed circuits Furthermore, it is to be understood that the form of the invention shown and described is to be taken as presently preferred embodiments Various modifications and changes may be made to each and every processing step as would be obvious to a person skilled in the art having the benefit of this disclosure It is intended that the following claims be interpreted to embrace all such modifications and changes and, accordingly, specification and drawings are regarded in an illustrative rather than a restrictive sense

Claims

WHAT IS CLAIMED IS:

1 A method for forming a planaπzed fill dielectric upper topography, comprising

removing portions of a semiconductor substrate to form a pair of isolation trenches within the semiconductor substrate, wherein said pair of isolation trenches are laterally spaced from each other by an active region.

depositing a fill dielectric within and between said pair of isolation trenches;

isotropically etching from a plasma source said fill dielectric only in areas above the active region; and

chemical-mechanical removing said fill dielectric remaining in said areas above the active region to an elevation level commensurate with said fill dielectric within said pair of isolation trenches

The method as recited in claim 1 , wherein said depositing comprises chemical vapor depositing an oxide

3 The method as recited in claim 1. wherein said removing comprises exposing a pair of field regions within said semiconductor substrate and etching semiconductor substrate within said field regions to a depth between 0 2 to 0 5 μm

4 The method as recited in claim 3, wherein said depositing comprises chemical vapor depositing said fill dielectric to a thickness exceeding said depth

5 The method as recited in claim 1 , wherein said isotropically etching comprises exposing said fill dielectric only in said areas and removing the exposed said fill dielectric in two dimensions

6 The method as recited in claim 1 , wherein said isotropically etching comprises removing at a substantially equal etch rate said fill dielectric in a dimension perpendicular and non-perpendicuiar to the upper surface of said fill dielectric.

7 The method as recited in claim 1, wherein said plasma source comprises a dry etch chemical composition comprising nitrogen tπfluoπde.

8 The method as recited in claim 1 , wherein said chemical-mechanical removing comprises polishing

I I

9. A method for forming a field dielectric, comprising:

providing a silicon substrate having an active region bounded by a pair of field regions;

forming a trench within each of said field regions;

depositing a fill dielectric within said trench and upon said active region;

isotropically removing at least a portion of said fill dielectric above said active region while retaining said fill dielectric within said trench;

chemical-mechanical polishing said fill dielectric above said active region to an elevation level commensurate within said fill dielectric within said trench.

10. The method as recited in claim 9, wherein said silicon substrate comprises an upper surface, and wherein said forming comprises removing said silicon substrate to a depth between 0.3 to 0.5 μm below said upper surface.

1 1. The method as recited in claim 10, wherein said depositing comprises chemical vapor depositing said fill dielectric to a thickness exceeding said depth.

12. The method as recited in claim 10, wherein said isotropically etching comprises exposing said fill dielectric only above said active region and removing the exposed said fill dielectric along vectors comprising two dimensions.

13. The method as recited in claim 12, wherein said two dimensions comprise a first dimension perpendicular to an upper surface of said fill dielectric and a second dimension along said upper surface.

14. The method as recited in claim 12, wherein said fill dielectric is removed along said first dimension at an etch rate substantially equal to said fill dielectric removed along said second dimension.

15. The method as recited in claim 10, wherein said plasma source comprises a dry etch chemical composition comprising nitrogen trifluoride.

16. The method as recited in claim 10, wherein said chemical-mechanical polishing comprises applying an abrasive wheel and a chemical slurry to the entirety of said fill dielectric above said active region as well as above said trench.

17. The method as recited in claim 16, wherein said applying is continued for a time period sufficient to equalize an upper surface of said fill dielectric above the active region commensurate with an upper surface of said fill dielectric above the trench.