WO1998004043A1 - High resolution digital synchronization circuit - Google Patents

High resolution digital synchronization circuit Download PDF

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Publication number
WO1998004043A1
WO1998004043A1 PCT/US1997/012912 US9712912W WO9804043A1 WO 1998004043 A1 WO1998004043 A1 WO 1998004043A1 US 9712912 W US9712912 W US 9712912W WO 9804043 A1 WO9804043 A1 WO 9804043A1
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WO
WIPO (PCT)
Prior art keywords
clock
signal
digital
logic device
clock signals
Prior art date
Application number
PCT/US1997/012912
Other languages
French (fr)
Inventor
David J. Pritchard
Original Assignee
Honeywell Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Inc. filed Critical Honeywell Inc.
Publication of WO1998004043A1 publication Critical patent/WO1998004043A1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation

Definitions

  • a clock is just a signal oscillating between a high and low value.
  • Fig. 1 shows a clock signal, a trigger and a synchronized signal.
  • signals are synchronized to the clock by matching the clock at the rising edge of the clock signal when it changes from low to high.
  • a trigger is rarely sampled at precisely the rising edge of the clock signal.
  • the trigger doesn't synchronize with the clock until a clock signals' rising edge occurs.
  • the problem with this is a delay in synchronization occurs until the next clock rising edge appears. This delay, or ambiguity or jitter as it is also known, is about one clock period which is undesirable.
  • the first method uses high frequency circuits. With high frequency circuits, the rising edges of the clock signal are more frequent and the ambiguity is smaller and therefore, the delay is less. However, these high frequency circuits are very complex and very costly. Furthermore, the reliability of the circuit is less due to the stress of operating at high frequencies.
  • Another method of reducing ambiguity is to start the clock when it is desired to trigger.
  • the problem with this approach is that the clock is rarely stabilized to a time period when it is first turned on. A clock requires some time before the clock adjusts to the clock period desired. As a result, inaccurate readings are produced.
  • the present invention is a digital synchronization circuit including a clock, a delay line and a digital logic device.
  • the clock runs independently of the digital synchronization circuit and produces a first clock signal.
  • a delay line is connected to the clock and produces multiple clock signals delayed a predetermined amount from the first clock signal.
  • a trigger sends a signal to the digital logic device indicating when synchronization is desired.
  • the digital logic device which is connected to the delay line, selects one of the clock signals and produces a signal synchronized to the clock signal.
  • Fig. 1 shows timelines of a clock signal, a trigger signal and a synchronized signal.
  • Fig. 2 shows a the digital synchronization circuit with a clock and a trigger as inputs into the circuit.
  • Fig. 3 shows timelines of delayed clock signals and the equation used in the digital logic device to determine which clock signal to synchronize with.
  • Fig. 4 shows a detailed diagram of the digital synchronization circuit.
  • Fig. 2 shows a top level block diagram of the digital synchronization circuit 2.
  • the present invention includes a multiple output delay line 4, with (N/2) outputs and a delay of (clock period/N) between outputs, and a programmable digital logic device 6.
  • a clock 8 produces a clock signal input into the delay line 4 which produces multiple outputs that are timed with the clock 8 after a certain delay for each output. For example, the first clock signal input would be NO. A delay would occur after (clock period/N) ns which would then result in the output 1. N/2 delays would be created.
  • the logic device 6 inverts the signals to create N signals for a signal to synchronize with.
  • a trigger 10 is sent to the logic device 6.
  • the logic device 6 decides which signal to synchronize with which will be described later in more detail. As a result, the jitter would be significantly smaller since the delay line 4 creates N clock output edges for synchronization to take place.
  • Fig. 3 shows all the signals including the clock signal, the delay outputs and a trigger signal.
  • a 5 output delay line is used with a 2.5 ns delay between the outputs.
  • a signal is synchronized with a rising edge of one of the clock signals.
  • the first signal edge would be the clock 8 which is CO.
  • the 5 delay signals would then be C1-C4.
  • Each output is also inverted enabling the trigger signal to select an inverted signal of the clock 8 as well.
  • Creating the inversion of the signals C0-C4 produces even more edges for opportunities for synchronization to occur. These signals would be NC0-NC4. In this figure, ten different clock edges are created for synchronization to take place.
  • Fig. 4 shows a more detailed diagram of the logic involved in the logic device 6.
  • the delay line outputs 10 are inverted to increase the number of signals to synchronize with.
  • Inverters 12 are used to create these inverted outputs 14.
  • a sample of the delay line outputs 10 are stored in a latch 18.
  • the latched values 20 are used to select the delay line output with the closest edge to the trigger signal 16 and the delay line output to be synchronized with is then selected to produce the Clockout 22.
  • the delay line output to be selected is determined by Eq. 1.
  • the logic portion of Fig. 4 is the realization of Eq. 1 with the "»"s representing the AND logic 24 and the "+”s representing the OR logic 26.
  • the latched values 20, along with the delay line outputs 10 and inverted outputs 14, are input into the logic portion of the logic device 6 which determines which delay output is to be selected for synchronization and the signal Clockout 22 is then produced synchronized with the selected delay output.

Abstract

The digital synchronization circuit produces multiple clock signals delayed a predetermined amount from an independent clock's signal. When it is desired to synchronize a signal, the digital synchronization circuit determines the optical clock signal to synchronize to and produces a signal synchronized to that clock signal. A delay line is connected to the independent clock signal to produce said multiple clock signals. A digital logic device is connected to the delay line. In response to a trigger signal indicating that synchronization is desired, the digital logic device selects one of the multiple clock signals as the optimal clock signal and produces a signal synchronized to the selected clock signal. The digital logic is also supplied with inverted versions of said multiple clock signals and comprises logic AND gates and logic OR gates.

Description

HIGH RESOLUTION DIGITAL SYNCHRONIZATION CIRCUIT
BACKGROUND OF THE INVENTION In many practices it is desirable to sample a clock with a trigger and create a signal synchronized to the clock. As is known, a clock is just a signal oscillating between a high and low value. Fig. 1 shows a clock signal, a trigger and a synchronized signal. As is seen in Fig. 1 , signals are synchronized to the clock by matching the clock at the rising edge of the clock signal when it changes from low to high. A trigger is rarely sampled at precisely the rising edge of the clock signal. As a result, the trigger doesn't synchronize with the clock until a clock signals' rising edge occurs. The problem with this is a delay in synchronization occurs until the next clock rising edge appears. This delay, or ambiguity or jitter as it is also known, is about one clock period which is undesirable.
Two methods are used to solve this problem. The first method uses high frequency circuits. With high frequency circuits, the rising edges of the clock signal are more frequent and the ambiguity is smaller and therefore, the delay is less. However, these high frequency circuits are very complex and very costly. Furthermore, the reliability of the circuit is less due to the stress of operating at high frequencies.
Another method of reducing ambiguity is to start the clock when it is desired to trigger. The problem with this approach is that the clock is rarely stabilized to a time period when it is first turned on. A clock requires some time before the clock adjusts to the clock period desired. As a result, inaccurate readings are produced.
It would be desirable to have a synchronization method available that is accurate and affordable.
SUMMARY OF THE INVENTION The present invention is a digital synchronization circuit including a clock, a delay line and a digital logic device. The clock runs independently of the digital synchronization circuit and produces a first clock signal. A delay line is connected to the clock and produces multiple clock signals delayed a predetermined amount from the first clock signal. A trigger sends a signal to the digital logic device indicating when synchronization is desired. The digital logic device, which is connected to the delay line, selects one of the clock signals and produces a signal synchronized to the clock signal.
BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows timelines of a clock signal, a trigger signal and a synchronized signal.
Fig. 2 shows a the digital synchronization circuit with a clock and a trigger as inputs into the circuit.
Fig. 3 shows timelines of delayed clock signals and the equation used in the digital logic device to determine which clock signal to synchronize with.
Fig. 4 shows a detailed diagram of the digital synchronization circuit.
DETAILED DESCRIPTION OF THE PRESENT INVENTION The present invention reduces the ambiguity by a factor of N where the ambiguity becomes 1/N times the clock period. Fig. 2 shows a top level block diagram of the digital synchronization circuit 2. The present invention includes a multiple output delay line 4, with (N/2) outputs and a delay of (clock period/N) between outputs, and a programmable digital logic device 6. A clock 8 produces a clock signal input into the delay line 4 which produces multiple outputs that are timed with the clock 8 after a certain delay for each output. For example, the first clock signal input would be NO. A delay would occur after (clock period/N) ns which would then result in the output 1. N/2 delays would be created. The logic device 6 inverts the signals to create N signals for a signal to synchronize with. When a synchronized signal is desired, a trigger 10 is sent to the logic device 6. The logic device 6 decides which signal to synchronize with which will be described later in more detail. As a result, the jitter would be significantly smaller since the delay line 4 creates N clock output edges for synchronization to take place.
Looking at a time line in Fig. 3, in conjunction with Fig. 2, will clarify the operation of the present invention. Fig. 3 shows all the signals including the clock signal, the delay outputs and a trigger signal. As can be seen in Fig. 3, a 5 output delay line is used with a 2.5 ns delay between the outputs. In the present invention, a signal is synchronized with a rising edge of one of the clock signals. The first signal edge would be the clock 8 which is CO. The 5 delay signals would then be C1-C4. Each output is also inverted enabling the trigger signal to select an inverted signal of the clock 8 as well. Creating the inversion of the signals C0-C4 produces even more edges for opportunities for synchronization to occur. These signals would be NC0-NC4. In this figure, ten different clock edges are created for synchronization to take place.
As can be seen in Fig. 3, the outputs will significantly reduce the jitter by providing many outputs that a trigger can synchronize with. The selection of which output is selected for synchronization is determined by the equation: Clockout=Run-NCTO»CTl •C0+Run»CT0-NCTl •NC0+Run«NCT0«NCTl •CT2-C 1 +»R un«CT0»CTl-NCT2-NCl+Rιm«NCT0-NCTl*«NCT2«CT3*»C2+Run-»CT0-CTl«CT2-NC
T3»NC2+Run»NCT0-NCTl -NCT2»NCT3*»CT4»C3+Run«CT0«CTl-CT2*'CT3«NCT4-N C3+Run«NCT0«NCTl-NCT2«NCT3«NCT4-C4+Run-CT0-CTl »CT2«CT3-CT4-NC4
(Eq. 1) Note, that the "T"s in the symbols symbolize the time at which a trigger occurs. According to this equation if all the signals are "high" in a component of the equation (ex. Run»NCT0,CTl*'C0), then the Clockout, or the signal to be synchronized with will be the last element in that component (ex. CO). Fig. 3 shows one example of the present invention. A trigger 10 occurs and by going through the equation, a signal to be synchronized with is determined. The Run signal is of course "high" since a Clockout is desired, NCT0 is "high", CT1 is "high", and therefore, CO would be selected since all the signals have indicated that CO is the best signal to synchronize to. The rest of the signals would not be selected in the equation since they would all be "low". For example, the next component of the equation would have CT0 as a "low" and therefore, NCO would not be chosen. However, looking at the time lines, one might think that Cl should be chosen as the clock signal to synchronize to since it is closer to the trigger 10. This would not be the case, because it takes the logic about 3-5 ns to process and therefore, the rising edge of Cl would have already passed.
Fig. 4 shows a more detailed diagram of the logic involved in the logic device 6. First shown on the left hand side of Fig. 4 are the delay line outputs 10. As mentioned before, the delay line outputs 10 are inverted to increase the number of signals to synchronize with. Inverters 12 are used to create these inverted outputs 14. When the trigger 16 occurs, a sample of the delay line outputs 10 are stored in a latch 18. The latched values 20 are used to select the delay line output with the closest edge to the trigger signal 16 and the delay line output to be synchronized with is then selected to produce the Clockout 22.
As mentioned above, the delay line output to be selected is determined by Eq. 1. The logic portion of Fig. 4 is the realization of Eq. 1 with the "»"s representing the AND logic 24 and the "+"s representing the OR logic 26. The latched values 20, along with the delay line outputs 10 and inverted outputs 14, are input into the logic portion of the logic device 6 which determines which delay output is to be selected for synchronization and the signal Clockout 22 is then produced synchronized with the selected delay output.

Claims

CLAIMS The embodiments of the invention in which an exclusive property or right is claimed are defined as follows:
1. A digital synchronization circuit comprising: a clock producing a clock signal; a delay line connected to the clock creating a plurality of delayed clock signals; a digital logic device connected to the delay line wherein the digital logic device selects one of the clock signals and produces a signal synchronized to the selected clock signal; and a trigger connected to the digital logic device to control when to produce the synchronized signal.
2. The digital synchronization clock of claim 1 wherein half of the clock signals are inverse clock signals of the other half of the clock signals.
3. The digital synchronization clock of claim 1 wherein the selected signal is the clock signal calculated by logic in the digital logic device.
4. The digital synchronization clock of claim 1 wherein the digital logic device comprises of a plurality of AND logic and a plurality of OR logic.
5. A digital synchronization circuit comprising: a free running clock producing a first clock signal; a delay line connected to the clock creating a plurality of clock signals delayed a predetermined time from the first clock signal; a digital logic device having a plurality of inputs and an output wherein the plurality of delayed clock signals from the delay line are the plurality of inputs into the digital logic device, and wherein the digital logic device selects one of the clock signals and produces the output synchronized with the selected clock signal; and an asynchronous trigger connected to the digital logic device to control when to produce the synchronized output.
6. The digital synchronization clock of claim 5 wherein half of the clock signals are inverse clock signals of the other half of the clock signals.
7. The digital synchronization clock of claim 5 wherein the selected clock signal is the clock signal calculated by logic in the digital logic device.
8. The digital synchronization clock of claim 5 wherein the digital logic device comprises of a plurality of AND logic and a plurality of OR logic.
PCT/US1997/012912 1996-07-23 1997-07-23 High resolution digital synchronization circuit WO1998004043A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US68532896A 1996-07-23 1996-07-23
US08/685,328 1996-07-23

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1051022A2 (en) * 1999-05-07 2000-11-08 Synectix Limited Clock signal generator
WO2003098620A1 (en) * 2002-05-16 2003-11-27 Samsung Electronics Co., Ltd. Recording medium having high melting point recording layer, information recording method thereof, and information reproducing apparatus and method therefor
US7385543B2 (en) * 2006-06-19 2008-06-10 Agilent Technologies, Inc. Systems and methods for asynchronous triggering of an arbitrary waveform generator

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4386323A (en) * 1980-01-31 1983-05-31 U.S. Philips Corporation Arrangement for synchronizing the phase of a local clock signal with an input signal
US4443766A (en) * 1976-06-15 1984-04-17 The United States Of America As Represented By The Secretary Of The Air Force Precision digital sampler
WO1988005236A1 (en) * 1987-01-05 1988-07-14 Grumman Aerospace Corporation High speed data-clock synchronization processor
US5003561A (en) * 1988-10-13 1991-03-26 Siemens Aktiengesellschaft Process for the reception of a binary digital signal
US5046075A (en) * 1989-02-23 1991-09-03 Siemens Aktiengesellschaft Method and arrangement for adapting a clock to a plesiochronous data signal and for clocking the data signal with the adapted clock
DE19537342A1 (en) * 1994-10-07 1996-04-18 Mitsubishi Electric Corp Synchronisation circuit with external data signal and clock feed terminals

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4443766A (en) * 1976-06-15 1984-04-17 The United States Of America As Represented By The Secretary Of The Air Force Precision digital sampler
US4386323A (en) * 1980-01-31 1983-05-31 U.S. Philips Corporation Arrangement for synchronizing the phase of a local clock signal with an input signal
WO1988005236A1 (en) * 1987-01-05 1988-07-14 Grumman Aerospace Corporation High speed data-clock synchronization processor
US5003561A (en) * 1988-10-13 1991-03-26 Siemens Aktiengesellschaft Process for the reception of a binary digital signal
US5046075A (en) * 1989-02-23 1991-09-03 Siemens Aktiengesellschaft Method and arrangement for adapting a clock to a plesiochronous data signal and for clocking the data signal with the adapted clock
DE19537342A1 (en) * 1994-10-07 1996-04-18 Mitsubishi Electric Corp Synchronisation circuit with external data signal and clock feed terminals

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1051022A2 (en) * 1999-05-07 2000-11-08 Synectix Limited Clock signal generator
GB2349755A (en) * 1999-05-07 2000-11-08 Synectix Ltd Clock signal generator
EP1051022A3 (en) * 1999-05-07 2001-08-29 Synectix Limited Clock signal generator
GB2349755B (en) * 1999-05-07 2003-05-14 Synectix Ltd Clock signal generator
WO2003098620A1 (en) * 2002-05-16 2003-11-27 Samsung Electronics Co., Ltd. Recording medium having high melting point recording layer, information recording method thereof, and information reproducing apparatus and method therefor
US7385543B2 (en) * 2006-06-19 2008-06-10 Agilent Technologies, Inc. Systems and methods for asynchronous triggering of an arbitrary waveform generator

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