WO1997039484A1

WO1997039484A1 - Method of fabricating an interconnect structure comprising lamination of a porous dielectric membrane

Info

Publication number: WO1997039484A1
Application number: PCT/US1997/005555
Authority: WO
Inventors: C. Thomas Rosenmayer; David B. Noddin
Original assignee: W.L. Gore & Associates, Inc.
Priority date: 1996-04-12
Filing date: 1997-04-02
Publication date: 1997-10-23
Also published as: AU2437297A

Abstract

An integrated circuit element is provided, which may be an active or passive element, including a planar dielectric layer (12) laminated to the surface of conductive lines (15) and the semiconductor substrate (11) having a thickness of 5 micrometers, or less, and a dielectric constant less than 3.4. The dielectric layer (12) is preferably a fluoropolymer film coated or impregnated with a low ionic content resin. The preferred fluoropolymer film is expanded polytetrafluoroethylene and the preferred resin component is a low ionic content polymer having a low dielectric constant, high thermal stability, and low thermal expansion.

Description

TITLE OF THE INVENTION

METHOD OF FABRICATING AN INTERCONNECT STRUCTURE COMPRISING LAMINATION OF A POROUS DIELECTRIC MEMBRANE

FIELD OF THE INVENTION

The present invention relates to the fabrication of semiconductor devices More particularly, an integrated circuit element, and method of manufacture, is provided wherein a low dielectric constant insulation layer is disposed on an integrated circuit structure using a planar, solvent free dielectric layer

BACKGROUND OF THE INVENTION

Integrated circuits are created from a silicon wafer using various etching, doping and depositing steps that are well known in the art of fabricating integrated circuit devices. A silicon wafer may be comprised of a number of integrated circuit dies that each represent a single integrated circuit chip Ultimately, the chip may be packaged by transfer molding a plastic encasement around the chip with a variety of pin-out or mounting and interconnection schemes. An integrated circuit is comprised of many interconnected transistors and associated passive circuit elements that perform a function or functions These functions may be random access memory, central processing, communications, etc.

In the formation of integrated circuit structures, patterned conductive layers must be used to provide electrical interconnection between active and passive devices comprising the integrated circuit structure. Many integrated circuits now contain multiple levels of metallization for interconnections. The need to integrate more functions onto a chip has caused the semiconductor industry to search for ways to shrink, or scale, the size of individual transistors and other devices commonly integrated on a chip. The shrinkage of sizes in such integrated circuit structures includes shrinkage of the horizontal spacing between adjacent conductors on the same plane. Such shrinkage of feature size results in a corresponding rise in the impedance of the conductors, as well as an increase in capacitive coupling between conductors and the integrated circuit structure Such capacitive coupling increases both RC delay and cross¬ talk, both of which reduce the speed at which the circuit may be operated

As is well known, the capacitance between conductors of an integrated circuit structure is highly dependent on the insulator, or dielectric, used to separate them Conventional semiconductor fabrication commonly employs silicone dioxide as a dielectric, which has a dielectric constant of about 3 9 ' The lowest possible, or ideal, dielectric constant is 1 0, which is the dielectric constant of a vacuum, whereas air has a dielectric constant of less than 1 001 Therefore, the amount of capacitance formed between adjacent lines, either horizontally or vertically, of an integrated circuit structure, may be reduced by reducing the impedance of the lines This may be achieved by substituting a different insulation material having a lower dielectric constant, e g , using some insulation material other than the commonly used silicone dioxide (Sι0₂), or by somehow reducing the dielectric constant of the particular insulation mateπal being used, e.g , somehow reducing the dielectric constant of an Sι0₂ insulation layer For thin film multilayer materials, the ideal material would have a low dielectric constant, low thermal expansion, good physical properties such as high elongation and high fracture toughness, good adhesion, low water absorption, thermal stability to 400°C and low solvent absorption United States Patent No 5,393,712 discloses a process for forming low dielectric constant insulation layers on an integrated circuit structure This process compnses the steps of forming a composite layer, having one or more extractable materials and one or more matrix forming insulation materials over an integrated circuit structure on a semiconductor wafer, and selectively removing the extractable material from the matrix forming material without damaging the remaining matrix material, thereby leaving behind a porous matnx of the insulation material In one embodiment of the process disclosed in U S Patent No 5,393,712, the composite layer is formed from a gel The extractable material is removed by first dissolving it in a liquid which is not a solvent for the matrix-forming material to form a s. Jution This solution is then preferably removed from the matrix-forming material either by lyophiiizmg (freeze-drymg) or by raising the pressure and temperature above the critical point of the solution

In United States Patent No 5,461 ,003, a semiconductor device and method is disclosed that forms air gaps between metal leads of an integrated circuit structure to provide a composite having a low-dielectric constant of about 1 25 thereby reducing the capacitive coupling between conductors in the integrated circuit structure The method for forming air gaps between metal leads of a semiconductor device comprises the steps of depositing a metal layer on a substrate, etching the metal layer to form metal leads, depositing a disposable solid layer between the metal leads, depositing over the disposable solid layer and the metal leads a porous dielectric layer, and removing the disposable solid layer through the porous dielectric layer to form air gaps between the metal leads beneath the porous dielectric layer Although such known processes for forming low dielectric constant insulation layers on an integrated circuit structure may operate with varying degrees of success in certain applications, they are replete with a multiplicity of shortcomings which detract from their usefulness For example, non-value added process steps are required to form the low dielectric constant layers, such as polymer extraction and dielectric planarization In addition, for air-gap or porous dielectric materials, the thermal conductivity is poor which results in reliability problems if the device gets too hot Also, the process steps which are taught in these references are relatively complex in nature and effect integrated circuit structure yields if not performed accurately The foregoing illustrates limitations known to exist in the present processes for forming low dielectric constant insulation layers on integrated circuit structures Thus, it is apparent that it would be advantageous to provide an improved process directed to overcoming one or more of the limitations set forth above Accordingly, a suitable alternative is provided including features more fully disclosed hereinafter

SUMMARY OF THE INVENTION

In one embodiment of the present invention, an improved method for forming an integrated circuit structure is provided wherein air gaps are formed between metal leads by using a planar, solvent free dielectric layer

In an alternate embodiment of the present invention, an integrated circuit element is provided comprising at least one base substrate, or multilayer base substrate, having an integrated electric circuit disposed thereon The integrated electric circuit is covered by a planar dielectric layer The dielectric layer is comprised of a porous polymer matrix layer which may contain within at least some of its pores or which may have disposed on a surface thereof as a coating, an additional dielectric mateπal The additional dielectric material may also be contained within substantially all of the pores of the porous polymer matrix layer The dielectric polymer coating may be disposed ad_jacent the electric circuit

The planaπty of the applied dielectric layer is less than 200 nm over 2 0 mm The dielectric layer has a dielectric constant of less than 3 9, and may have a dielectric constant of less than 2 0 The dielectric layer has a thickness of 5 micrometers, or less, and may have a thickness of 2 0 micrometers, or less

In an alternate embodiment of the present invention, a multiple layer integrated circuit is provided comprising a p'urality of integrated circuit elements bonded together In a presently preferred embodiment of the present invention, the dielectric layer is comprised of a porous, expanded polytetrafluoroethylene (ePTFE) membrane having a thickness of 5 micrometers, or less, and a dielectric constant of less than 3 0

The base substrate may be comprised of silicon, gallium arsenide, or ceramic, for example

The dielectric layer may be applied so as to produce an air gap dielectric between closely spaced conductors of the integrated electric circuit in a manner which does not require an extraction step to remove a filler material

The dielectric layer may also be impregnated with inorganic materials such as silicon dioxide, boron nitride, aluminum nitride, aluminum oxide, or silicon nitride

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing summary, as well as the following detailed description of a preferred embodiment of the invention, will be better understood when read in conjunction with the appended drawings For purposes of illustrating the invention, there is shown in the drawings an embodiment which is presently preferred It should be understood however that the invention is not limited to the precise arrangement and instrumentality shown In the drawings Figure 1 is a schematic cross-sectional view of an integrated circuit according to the present invention

Figure 2 is an scanning electron photomicrograph (SEM) cross-section of a 0 7 μm ePTFE membrane - cyanate ester composite dielectric layer disposed between two silicon wafers,

Figure 3 is an SEM cross-section of a 0 6 μm ePTFE membrane - TFE- PDD copolymer composite dielectric layer disposed between two silicon wafers

Figure 4 ts an SEM cross-section of a 4 0 μm ePTFE membrane dielectric layer disposed between two silicon wafers, and Figure 5 is an SEM cross-section of a 2 0 μM ePTFE membrane - cyanate ester composite dielectric layer disposed between a patterned silicon wafer and a metal foil

DETAILED DESCRIPTION OF THE INVENTION

As best seen by reference to Figure 1 , an integrated circuit element is provided generally at 10, which may be an active or passive element The integrated circuit element is comprised of at least one substrate 1 1 and a planar dielectric layer 12 having a thickness of 5 micrometers, or less, and a dielectric constant of less than 3 9 The dielectric layer is preferably a fluoropolymer film which is either coated or impregnated with a low ionic content resm A metal surface 13 may be disposed on a surface of the dielectric layer 1 1 A preferred fluoropolymer film is expanded, porous polytetrafluoroethylene membrane A preferred resin component is a low-ionic content polymer having a low dielectric constant, high thermal stability, and low thermal expansion Examples of such resins are polyimide, benzocyclobutene, cyanate ester, polyarylether, parylene, fluorinated versions of the preceding, PFA, FEP, LCP, or TFE-PDD Air gaps 14 are formed between conductive tracers 15 As the term is used herein expanded porous polytetrafluoroethylene

(PTFE) shall mean a membrane which may be prepared by any number of known processes, for example, by stretching or drawing processes, by papermaking processes by processes in which filler materials are incorporated with the PTFE resin and which are subsequently removed to leave a porous structure or by powder sintering processes Preferably the porous polytetrafluoroethylene membrane is porous expanded polytetrafluoroethylene membrane having a microstructure of interconnected nodes and fibrils as described in U S Patent Nos 3 953,566 4 187 390, and 4 110 392 which are incorporated herein by reference, and which fully describe the preferred material and processes for making them Also the expanded porous polytetrafluoroethylene membrane may have a microstructure which is comprised substantially of fibrils, as descπbed in U S Patent 5,476,589 incorporated herein by reference

As the terms is used herein, "planaπty" is defined as the maximum vertical deviation from flatness over a given length All products according to the invention have planaπty less than 200 nm over 2 0 mm

In a preferred embodiment of the present invention, the dielectric layer may be made from a polytetrafluoroethylene (PTFE) fine powder that has a low amorphous content and a degree of crystallization of at least 98% This PTFE fine powder is made into a paste by uniformly mixing it with an extrusion aid of a mineral spirit, naphtha, or other such lubricant This paste is then molded into the shape dictated by the intended use of the finished product by a molding method that imparts shear deformation, such as extrusion molding or calender molding It is usually molded into the form of a tape by extrusion The polytetrafluoroethylene used herein is a coagulated dispersion or fine powder polytetrafluoroethylene Several such resins that have been used demonstrate that the various commercially available fine powders from the several suppliers of such resins are suitable in the process Some such resins can tolerate more extrusion aid than others and still yield products within the range of permeability desired Some such resins suitable for use are Fluon®

CD-123 and Fluon CD-1 available from ICl Americas, Ine , although there is some batch to batch variability which alters how much they can be expanded E I duPont de Nemours and Co , Ine , also manufactures Teflon® fine powders that are suitable for use The coagulated dispersion powders are lubricated with a hydrocarbon extrusion aid, preferably an odorless mineral spirit such as Isopar K (made by Exxon Corp ) The lubricated powder is compressed into cylinders and extruded in a ram extruder to form tapes Two or more layers of tape can be stacked together and compressed between two rolls The tape or tapes are compressed between rolls to an appropriate thickness, e g 5 to 40 mils or so The wet tape is stretched transversely to 1 5 to 5 times its original width The extrusion aid is driven off with heat The dried tape is then expanded longitudinally between banks of rolls in a space heated to a temperature that is below the polymer melting point (327°C) The longitudinal expansion is such that the ratio of speed of the second bank of rolls to the first bank is

10-100 to 1 The longitudinal expansion is repeated at a 1-1 5 to 1 ratio

Next, the tape, after the longitudinal expansion, is expanded transversely at a temperature that is less than 327°C to at least 1 5 times and preferably to 6 to 15 times the input width of the original extrudate while restraining the membrane from longitudinal contraction While still under constraint the membrane is preferably heated to above the polymer melting point (327°C) and then cooled

This process provides an open or porous, yet strong structure having a high air permeability In contrast to conventional liquid spinning or chemical vapor processes for applying a dielectric layer to a wafer substrate, the present invention provides a dielectric layer which is applied to a wafer substrate as a film or membrane The dielectric layer may contain a resin at least partially penetrating into the pores or void spaces of the ePTFE This provides a high degree of flexibility in resin selection Dielectric layer thicknesses may range from about a maximum of 5 micrometers to about less than 2 micrometers The thickness of the dielectric layer is a function of the ePTFE membrane which acts as a scaffolding The ePTFE membrane permits very thin films to be cast without pinholes These films are then placed onto the wafer substrate and cured with heat and pressure, preferably in an autoclave or vacuum hot press as described in more detail hereinafter

In accordance with the teachings of the present invention, yields of the dielectric resin material may be improved to at least 50%, and possibly greater than 80%, as compared to about 5% yields with the conventional spinning processes This of course results in tremendous cost savings compared to the conventional spinning processes Potentially, even more significant cost savings can be obtained resulting from the reduction in processing steps which are presently employed by conventional methods to create air gaps within an integrated circuit element The dielectric layers produced in accordance with the teachings of the present invention can be imaged well through a metal mask using laser ablation techniques or reactive ion etching The films planaπze well as a result of a pressing configuration which uses the inorganic substrate as one flat surface and a highly polished caul plate as another

In accordance with the present invention an integrated circuit element may be made by initially coating and/or impregnating the dielectric layer with a resin solution, or with molten resin Thereafter the solution is partially cured and/or dried The ratio of resm to solvent may be varied in order to produce the correct degree of loading A low solids content solution may be used in order to provide a minimum degree of loading, for example to just coat the fibrils of the ePTFE membrane comprising the dielectric layer Additionally or alternatively, an inorganic material such as silicon dioxide, boron nitride, aluminum nitride, aluminum oxide, or silicon nitride may be introduced into the ePTFE dielectric layer by blending with the resm prior to its introduction into the membrane

Alternatively, the resin may be introduced into the ePTFE dielectric layer prior to the expansion process step of the ePTFE In this situation, the resm would typically be a thermoplastic in the form of small particles or powder The amount and type of resin added may be varied in order to optimize the final properties of the dielectric material Additionally or alternatively, an inorganic material such as silicon dioxide, boron nitride, aluminum nitride, aluminum oxide, or silicon nitride in powder form may be introduced into the ePTFE dielectric layer prior to the expansion process Also, alternatively, the ePTFE may be used without resin additions of any kind, or these additions may be made to the base wafer prior to the lamination of the ePTFE sheet

The dielectric layer may be laminated to the base substrate by any suitable process, such as by an autoclave or a vacuum hot press process, for example The autoclave process utilizes a pressurized gas to create a hydrostatic compressive force This method has the benefit of a very uniform stress field, which is helpful in preventing brittle parts, such as silicon base wafers, from fracturing In this method it is necessary to use a flexible, gas-tight membrane bag around the parts to be laminated A suitable autoclave process in accordance with the present invention is a modified process of the type described in detail in U S Patent 5 034 801 incorporated herein by reference Unlike the process taught by U S Patent 5 034 801 the autoclave process employed in the present invention does not cause resm to fill the gaps between narrowly disposed conductive traces of the integrated electric circuit In order to accomplish this, the autoclave lamination process described in U S Patent

5,034,801 must be modified to account for three main variables namely pressure, temperature, and dwell time Dwell time is the amount of time at the maximum temperature and pressure selected for the process The selection of the appropriate values for each of these variables is dependent on the material to be laminated The pore size, pore volume, resin type and resin loading are all important in determining the lamination process variables

The vacuum hot press process is a conventional process which is used in the iamination of printed circuit boards The press applies a unidirectional force to the parts to be laminated, rather than an isostatic force in the case of the autoclave The main advantage to this method is high throughput Typically, several layers of parts to be laminated can be stacked together This process is also suitable for automation since no bag is required A limitation of this process is that the lamination pressure is only uniform if the parts to be laminated are soft or ductile, or have exactly uniform thickness and if the press itself is dimensionally true The latter is not usually the case because of the distortions induced by the temperature and pressure gradients in the press In order to over come this limitation, it is typical to use a press pad A press pad is typically a very soft, high temperature material such as silicone rubber The mechanical compliance of the soft material helps to create a uniform stress field However, when very stiff, brittle base wafers are used with a conventional press pad, there is still a stress concentration around the periphery of the wafer This stress concentration can cause the fracture of brittle substrates Thus, the use of a vacuum hot press is generally avoided with such substrates However, unexpectedly, and in accordance with the teachings of the present invention, this stress field may be minimized by using a press pad which is slightly smaller in dimension than the dimension of the base wafer For example when laminating a 150 mm diameter wafer it has been discovered that a press pad with a diameter of 140-148 mm is suitable The selection of process variables is very much the same as in the autoclave method An important feature of the present invention is the ability to efficiently and effectively form an air gap dielectric 14 (Figure 1 ) The air gap dielectric provides the lowest possible dielectric constant between parallel conductors 15 in the integrated electric circuit In order to provide such a structure, neither the ePTFE dielectric layer, nor the resm can be allowed to flow into the sub-haif micron gaps that separate adjacent conductors, as best seen by reference to Figure 1

Since the dielectric layer thickness and the thickness of the conductive traces on the integrated circuit are roughly equivalent, the dielectric layer must be compressed by about 50 percent so that the dielectric layer can contact the substrate in areas not occupied by metal lines In order to allow for such compression, the dielectric layer must have at least 50 percent void space In addition, the lamination process must be controlled such that the dielectric polymer contained within the porous matrix is not allowed to flow into these gaps The pressure, temperature, and dwell time must be optimized such that the dielectric adheres properly to the substrate without flowing into the gaps

In addition to the lamination of the dielectric layer, it may also be advantageous to provide a metallization 13 on a top surface of the dielectric layer 12 This metallized surface is necessary to provide a subsequent level of interconnections for the integrated circuit The metallized surface may be laminated to the dielectric layer concurrent with the lamination of the dielectric layer to the base wafer It is also possible to apply the metallized surface to the dielectric layer prior to laminating the dielectric layer to the base wafer, such as by physical vapor deposition, chemical vapor deposition, plating, or lamination The prior application of metal to the dielectric layer has the advantage of permitting quality inspections prior to the lamination of the dielectric/metal combination to the base wafer

Without intending to limit the scope of the present invention, the apparatus and method of production of the present invention may be better understood by referring to the following examples

Example 1

A 1 5 μm ePTFE membrane having a microstructure comprised substantially of fibrils was impregnated with a 50% cyanate ester/methyl ethyl ketone (MEK) solution The MEK was allowed to evaporate leaving the b- stage cyanate ester resm within the microstructure of the ePTFE membrane The composite of ePTFE membrane and resm was placed between two polished silicon wafers and laminated in a vacuum hot press at 175 psi and 225° C The resulting laminate was cross-sectioned and examined in an SEM Figure 2 shows a resultant dielectric layer thickness of about 0 7 microns

Example 2

A 1 5 μm ePTFE membrane having a microstructure comprised substantially of fibrils was impregnated with a 1 % TFE-PDD obtained from E I duPont de Nemours and Co under the tradename Teflon® AF solution The solvent was allowed to evaporate, leaving the TFE-PDD resin within the microstructure of the ePTFE membrane The composite of ePTFE membrane and resin was placed between two polished silicon wafers and laminated in a vacuum hot press at 175 psi and 225° C The resulting laminate was cross- sectioned and examined in an SEM Figure 3 shows a resultant dielectric layer thickness of about 0 6 microns

Example 3

An unfilled 1 5 μm ePTFE membrane, having a microstructure comprised substantially of fibrils, was placed between two silicon wafers and laminated in a vacuum hot press at 200 psi and 385^βC Figure 4 shows a resultant dielectric layer thickness of about 4 0 microns

Example 4, The cyanate ester/ePTFE membrane of Example 1 was placed between a silicon wafer with 0 65 μm high patterned metal features and Cu/polyimide/Cu foil The combination was then laminated in accordance with the teachings of Example 1 Figure 5 shows a planar structure with dielectric thickness between metal features of about 2 0 microns

Claims

CLAIMS:

Having described the invention, what is claimed is

1 An integrated circuit element comprising at least one base substrate, said substrate having disposed on at least one surface at least two parallel conductive traces, said conductive traces defining a gap therebetween, and at least one dielectric layer defined by a membrane which is laminated to said base substrate over said conductive traces

2 The invention of claim 1 , wherein said dielectric layer has a thickness less than 5 micrometers

3 The invention of claim 1 , wherein said dielectric layer has a thickness less than 2 micrometers

4 The invention of claim 1 , wherein said dielectric layer has a dielectric constant of less than 3 0

5 The invention of claim 1 , wherein said dielectric layer has a dielectric constant of less than 2 0

6 The invention of claim 1 , wherein the dielectric layer is defined by an expanded porous polytetrafluoroethylene membrane

7 The invention of claim 6, wherein said expanded porous polytetrafluoroethylene membrane has a microstructure comprised substantially of fibrils

8 The invention of claim 1 wherein the dielectric layer is coated with a dielectric polymer

9 The invention of claim 1 , wherein the dielectric layer is at least partially impregnated with a dielectric polymer 10 The invention of claim 1 wherein the dielectric layer is substantially impregnated with a dielectric polymer

1 1 The invention of claim 1 wherein the dielectric layer has a planaπty of less than 200 nm over 2 0 mm

12 The invention of claims 8, 9, or 10 wherein said dielectric polymer is selected from a group consisting of thermosetting polymers low ionic content thermosetting polymers and thermoplastics

13 The invention of claim 1 , wherein a metallized surface is disposed on a planar surface of the dielectric layer

14 The invention of claim 1 , wherein said gap is not filled by said dielectric layer

15 The invention of claim 1 , wherein said dielectric layer is at least partially impregnated with an inorganic material

16 The invention of claim 15, wherein said inorganic material is selected from a group consisting of silicon dioxide, boron nitride, aluminum nitride, aluminum oxide, and silicon nitride

17 A method of forming an integrated circuit element comprising the steps of providing a wafer substrate, providing a solvent free dielectric layer defined by a porous membrane, and laminating the porous membrane on a predetermined surface of the wafer substrate

18 The method of claim 17, wherein said wafer substrate is backed by a press pad having a width dimension smaller than that of said wafer substrate