WO1997036319A1 - A method for producing a semiconductor device by the use of an implanting step and a device produced thereby - Google Patents
A method for producing a semiconductor device by the use of an implanting step and a device produced thereby Download PDFInfo
- Publication number
- WO1997036319A1 WO1997036319A1 PCT/SE1997/000534 SE9700534W WO9736319A1 WO 1997036319 A1 WO1997036319 A1 WO 1997036319A1 SE 9700534 W SE9700534 W SE 9700534W WO 9736319 A1 WO9736319 A1 WO 9736319A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- semiconductor layer
- grown
- junction
- conductivity type
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 64
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000010410 layer Substances 0.000 claims abstract description 104
- 239000002019 doping agent Substances 0.000 claims abstract description 25
- 239000002344 surface layer Substances 0.000 claims abstract description 21
- 239000012535 impurity Substances 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims description 34
- 238000002513 implantation Methods 0.000 claims description 8
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 230000006378 damage Effects 0.000 claims description 3
- 238000000407 epitaxy Methods 0.000 claims description 3
- 230000000875 corresponding effect Effects 0.000 claims 1
- 230000008901 benefit Effects 0.000 description 9
- 230000005684 electric field Effects 0.000 description 6
- 238000000137 annealing Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 230000000903 blocking effect Effects 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000005280 amorphization Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910052729 chemical element Inorganic materials 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002674 ointment Substances 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000009827 uniform distribution Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/1608—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/931—Silicon carbide semiconductor
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Recrystallisation Techniques (AREA)
- Electrodes Of Semiconductors (AREA)
- Thyristors (AREA)
Abstract
A method for producing a semiconductor device comprising a step a) of implanting an impurity dopant of a first conductivity type into said semiconductor layer (1) being doped according to a second opposite conductivity type for forming a first type doped surface layer (2) surrounded, except for the top surface thereof, by second conductivity type doped regions (3) of said semiconductor layer for forming a pn-junction (4) at the interface thereto. A highly doped additional semiconductor layer (5) is grown on top of said surface layer (2) for forming a contact layer allowing a low resistance ohmic contact to be established to the device so created.
Description
A method for producing a semiconductor device by the use of an implanting step and a device produced thereby
TECHNICAL FIELD OF THE INVENTION AND PRIOR ART
The present invention relates to a method for producing a semiconductor device having a semiconductor layer with a pn- junction therein, comprising a step a) of implanting an im¬ purity dopant of a first conductivity type, one of a) n and b) p, into said semiconductor layer being doped according to a second opposite conductivity type for forming a first type doped surface layer surrounded, except for the top surface thereof, by second conductivity type doped regions of said semiconductor layer for forming a pn-junction at the inter- face thereto, as well as a semiconductor device produced by carrying out such a method.
Such an ion implantation technique may be used for produc¬ tion of all types of semiconductor devices, and all semicon- ductor devices having a pn-junction created by such an im¬ plantation step are comprised inspite of the presence of several further pn-junctions. Examples of such devices are different types of diodes, transistors and thyristors, and this technique allows the formation of a planar structure which is favourable in several respects, particularly for solving the passivation problem. A very high, if not the highest, electric field occurs in reverse bias of a semicon¬ ductor device, having a blocking pn- unction, in the insula¬ tor very close to the pn-junction. In mesa structured de- vices the intersection of the pn-junction with the interface to the passivating insulator is at the lateral mesa walls
where the surface conditions are hard to control. In addi¬ tion the crystallographic orientation of the interface changes gradually around the mesa. These problems do not oc¬ cur in planar structures obtainable by ion implantation. However, one technological difficulty is the requirement of highly doped contact layers necessary for the formation of low resistance ohmic contacts. With ion implantation the maximum doping concentration is limited by the amorphization of the material. Thus, the maximum doping concentration ob- tainable by the ion implantation is considerably lower than in said mesa structures, so that the passivation problem is solved, but this has been made at the cost of a degraded contact layer of the device so created.
This overall problem is particularly pronounced in using a method defined in the introduction for the production of semiconductor devices having SiC as said semiconductor layer, since such production techniques are more developed for some other material, especially for Si, so that the pre- sent invention is particularly occupied with solving this problem for the production of semiconductor devices of SiC, where the advantages of such a planar structure is consider¬ ably greater than for especially Si due to the inherent characteristics of SiC with the ability to hold up to five times higher voltages in the blocking state of a semiconduc¬ tor device made of SiC than one made of Si, which make such devices well suitable for high power applications. However, it is only possible to benefit from this excellent property of SiC to a small extent would a mesa structure pn-junction be used. Inspite of these particular advantages of the im¬ plantation technique in devices made of SiC, the invention is not in any way restricted to the use of SiC as semicon¬ ductor layer.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a method of the type mentioned in the introduction through which the overall problem discussed above may be solved.
This object is in accordance with the invention obtained by providing such a method with a step b) following upon step a) and in which a highly doped additional semiconductor layer of said first conductivity type is epitaxially grown on top of said surface layer for forming a contact layer al¬ lowing a low resistance ohmic contact to be established to the device so created.
By combining this so called re-growth step with the implan¬ tation step it will be possible to take advantages of the preferred characteristics of each of said technique, so that it will be possible to locate the intersection of the pn- junction with the interface to the insulator where the sur- face conditions are easy to control and by the step of epi¬ taxial growth a contact layer allowing a low resistance oh¬ mic contact to be established to the device may also be ob¬ tained. Such an epitaxially grown contact layer can be doped much higher than an implanted layer (normally more than one order of magnitude).
According to a preferred embodiment of the invention said method is characterized by one of a) in step b) said addi¬ tional semiconductor layer is grown on top of said surface layer with lateral walls thereof being surrounded by the surface contour of said surface layer with a distance there¬ between for separating the pn-junction from said contact layer, and b) in step b) said additional semiconductor layer is grown on top of said semiconductor layer and after that structured so that lateral walls thereof are surrounded by the surface contour of said surface layer with a distance
therebetween for separating the pn-junction from said con¬ tact layer. In this way the preferred device structure with a separation of said pn-junction from the contact layer may be obtained. Thanks to this characteristic it will be possi- ble to keep the high electric field obtained at the surface across said pn-junction in the reverse bias state of a semi¬ conductor device so created away from said lateral walls of the contact layer for preventing problems with leakage cur¬ rents, breakdowns and destruction of the device. In addition it would be possible to cover the pn-junction where it reaches the surface with an insulating passivation layer to prevent the semiconductor device from breaking down at the surface near the pn-junction.
According to another preferred embodiment of the invention said contact layer is given a lower surface contour corre¬ sponding to a coverage of the main part of said surface layer. This will make it possible to obtain large currents in the on-state of the device and a substantially uniform distribution of the electrical field lines over said pn- junction.
According to another preferred embodiment of the invention said distance separating said pn-junction from said contact layer is selected so as to prevent the depletion region of said junction under the intended reverse bias of the semi¬ conductor device so created from reaching said contact layer. The advantage of such a design is as already men¬ tioned that no high electric field will occur at said lat- eral walls of the contact layer.
According to a further preferred embodiment of the invention said contact layer is in step b) epitaxially grown with a doping concentration above lO1^ cm~3, and according to a still more preferred embodiment of the invention above IO20 cm ~3, so that in this way by combining the epitaxial growth
with the implantation technique a considerably higher doping concentration of the layer intended to serve as contact layer may be obtained than should no such step be utilised.
According to another preferred embodiment of the invention said semiconductor layer, into which it is implanted in step a) is made of SiC. Such a method is especially well suited for the production of a semiconductor device having such a semiconductor layer of SiC, since it will then be possible to have a low resistance ohmic contact thereto and still fully benefit from the property of SiC to withstand high voltages in the blocking state of such a device by said pla¬ nar structure obtained for said pn-junction.
According to another preferred embodiment of the invention said contact layer is in step b) grown by epitaxy of SiC and impurity dopants. This is of course preferred when said semiconductor layer is made of SiC, since it makes it possi¬ ble to grow a contact layer of a good order on said surface layer.
According to another preferred embodiment of the invention said first conductivity type dopants implanted in step a) and grown into the additional semiconductor layer in step b) are of p-type. The implantation technique is, especially for SiC as said semiconductor layer, furthest developed for ac¬ ceptors, but it is emphasised that the invention is not in any way restricted to the use of p-type dopants as said first conductivity type dopants, and in fact this technique has also been successfully used for donors.
According to another preferred embodiment of the invention Al is used as impurity dopant in said additional semiconduc¬ tor layer, and said contact layer is in step b) grown by epitaxy of SiC and this impurity dopant. It has turned out that very high doping concentrations with a good order of
the layer grown may be obtained by using Al as impurity dopant for the epitaxial growth of SiC.
According to another preferred embodiment of the invention said additional semiconductor layer is grown by Chemical Va¬ pour Deposition, which is a preferred and the most common technique for epitaxial growth of semiconductor layers.
According to another preferred embodiment of the invention being a development of that previously mentioned, said addi¬ tional semiconductor layer is grown by heating said semicon¬ ductor layer at such a high temperature that the impurity dopants implanted in step a) are made electrically active and implantation damages are reduced. Thus, no separate annealing step is necessary, but the impurity dopants implanted in step a) will automatically become electrically active during the Chemical Vapour Deposition growth of said contact layer.
According to another preferred embodiment of the invention, in which said semiconductor layer and said additional semi¬ conductor layer are made of SiC, said temperature is higher than 1500°C, which will ensure a good annealing of said sur¬ face layer created by the implantation step.
Another object of the present invention is to provide a semiconductor device having a good ohmic contact and a pn- junction formed by the planar structure, and this object is in accordance with the invention obtained by providing a semiconductor device according to the independent appended device claim. The advantages thereof are the same as dis¬ cussed for the corresponding method claims.
Further preferred features and advantages of the invention will appear from the following description and the other de¬ pendent claims.
BRIEF DESCRIPTION OF THE DRAWINGS
With reference to the appended drawings, below follows a specific description of a preferred embodiment of the inven¬ tion cited as an example.
In the drawings:
Fig 1-4 illustrates very schematically the most important steps in a method for producing a semiconductor de¬ vice according to a preferred embodiment of the in¬ vention.
DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT OF THE INVENTION
The method of which the most important steps are illustrated in Figs. 1-4, does of course also comprise several further steps of conventional type, such as masking, demasking, pas¬ sivation and so on, but these have nothing to do with the inventional idea and have therefore been left out for the sake of clearness. Furthermore, the figures are very sche¬ matic and does not show for instance passivation layers or masking layers, which may be there. Furthermore, only the semiconductor layer into which it is implanted has been shown in the figures, but the semiconductor device created by this method will almost always have further layers there¬ under or therebeside.
It is started with a semiconductor layer 1, which in this case is made of SiC and is low doped with n-type impurity dopants for forming a drift layer of the device to be pro¬ duced.
In a step a) the surface of the SiC semiconductor layer 1 is exposed to a bombardment of ions of p-type, such as for in¬ stance aluminium or boron. The energy used for the bombard¬ ment of said surface by the ions is preferably in the range of 100 KeV - 300 KeV. A thin surface layer 2 having a thick¬ ness in the region of tenth of μm with a concentration of dopants between lO^-^-lO1^ cm~3 is in this way created. These dopants are still not electrically active after this implan¬ tation step, and the semiconductor layer has to be heated to a temperature above 1500°C for obtaining such activation of the p-type dopants. It is evident that a suitable mask has been used, for instance of gold, for obtaining the lateral limitation of the surface layer 2 shown in Fig. 1. The layer 3 of the semiconductor layer 1 located thereunder will ac- cordingly be n-type doped, so that a pn-junction 4 is formed at the interface between the two layers 2 and 3. Thus, a planar pn-junction is formed in this way.
In a second step a thin highly doped additional semiconduc- tor layer 5 is epitaxially grown on top of the semiconductor layer 1, and this is accomplished by using the so called Chemical Vapour Deposition technique, during which the semi¬ conductor layer 1 is heated at a temperature above 1500°C, through which the impurity dopants implanted in said surface layer 2 will be made electrically active. This high tempera¬ ture is also needed for cracking the precursor gases used for the epitaxial growth of SiC of the layer 5. In this way a highly doped epitaxial layer of SiC may be grown. This layer may have a doping concentration above IO2-1 crrT^ and more exactly a concentration of approximately IO2-*- c ~3 may be obtained, which is well more than one order of magnitude higher than may be obtained by the implantation technique. Preferably aluminium is used as impurity dopant grown into said additional semiconductor layer 5, but also other ele- ments are conceivable.
After said step of epitaxial growth said additional semicon¬ ductor layer 5 is structured by for instance RIE, so that it receives the lateral extension shown in Fig 3 with lateral walls 6 thereof surrounded by the surface contour 7 of the surface layer 2 with a distance therebetween for separating the pn-junction 4 from the layer 5.
It is illustrated in Fig. 4 how the depletion region 8 cre¬ ated at both sides of said pn-junction 4 will not reach the contact layers 5 when the semiconductor device so created is reverse biased. Accordingly, no high electric field will occur at said lateral walls 6, and the area of the pn- interface, at which a high electric field is present, will be located entirely in the semiconductor material, so that the advantages of a high field strength material like SiC can be utilized.
The drift layer 3 of such a device will take the main part of the voltage in the blocking state of such a semiconductor device, and this has preferably also at least a highly doped substrate layer directly under the drift layer 3 or with other layers therebetween for forming a good ohmic contact at the opposite side of the device to said contact layer 5.
The invention is of course not in any way restricted to the preferred embodiment described above, but many possibilities to modifications thereof would be apparent to a man with or¬ dinary skill in the art without departing from the basic idea of the invention.
It may for instance be mentioned that although the dopants in said surface layer and said contact layer are of the same conductivity type, it is well possible to have different dopants in these two layers.
When it is said that the semiconductor device has a semicon¬ ductor layer of SiC it does not necessarily mean that the semiconductor device has SiC as the only semiconductor mate¬ rial, but only the region in which the implantation takes place and in which a pn-junction is formed has then to be of SiC and the device may have hetero-character should this be desired.
Furthermore, the pn-junction will in practise move a little bit into the semicondutor layer when this is heated during the step of epitaxial growth through diffusion of the im¬ planted dopants, although this has not been illustrated in the figures.
The definition "layer" is to be interpreted broadly and com¬ prises all types of volume extensions and shapes.
All definitions concerning the material of different layers of course also include inevitable impurities as well as in- tentional doping.
Although annealing is automatically obtained by the CVD regrowth step an additional annealing step may be carried out in combination with the regrowth. For instance, first an annealing step above 1700°C is carried out for 30 min and then is the temperature reduced to 1550-1620°C and the growth is performed.
Claims
1. A method for producing a semiconductor device having a semiconductor layer (1) with a pn-junction therein, compris- ing a step a) of implanting an impurity dopant of a first conductivity type, one of a) n and b) p, into said semicon¬ ductor layer (1) being doped according to a second opposite conductivity type for forming a first type doped surface layer (2) surrounded, except for the top surface thereof, by second conductivity type doped regions (3) of said semicon¬ ductor layer for forming a pn-junction (4) at the interface thereto, characterized by a step b) following upon step a) and in which a highly doped additional semiconductor layer (5) of said first conductivity type is epitaxially grown on top of said surface layer for forming a contact layer allow¬ ing a low resistance ohmic contact to be established to the device so created.
2. A method according to claim 1, characterized by one of
a) in step b) said additional semiconductor layer (5) is grown on top of said surface layer (2) with lateral walls (6) thereof being surrounded by the surface contour (7) of said surface layer with a distance therebetween for sepa- rating the pn-junction (4) from said contact layer, and
b) in step b) said additional semiconductor layer (5) is grown on top of said semiconductor layer (1) and after that structured so that lateral walls (6) thereof are sur- rounded by the surface contour (7) of said surface layer with a distance therebetween for separating the pn-junc¬ tion (4) from said contact layer.
3. A method according to claim 2, qharacterized in that said contact layer (5) is given a lower surface contour corre- sponding to a coverage of the main part of said surface layer (2).
4. A method according to claim 2 or 3, characterized in that said distance separating said pn-junction (4) from said con¬ tact layer (5) is selected so as to prevent the depletion region (8) of said junction under the intended reverse bias of the semiconductor device so created from reaching said contact layer.
5. A method according to any of claims 1-4, characterized in that said contact layer (5) is in step b) epitaxially grown with a doping concentration above lO1^ cm~3.
6. A method according to any of claims 1-5, characterized in that said contact layer (5) is in step b) epitaxially grown with a doping concentration above 10 ^ cm~3.
7. A method according to any of claims 1-6, characterized in that said semiconductor layer (1), into which it is im¬ planted in step a), is made of SiC.
8. A method according to any of claims 1-7, characterized in that said contact layer (5) is in step b) grown by epitaxy of SiC and impurity dopants.
9. A method according to any of claims 1-8, characterized in that said first conductivity type dopants implanted in step a) and grown into the additional semiconductor layer (5) in step b) are of p-type.
10. A method according to claim 8, characterized in that Al is used as impurity dopant in said additional semiconductor layer (5) .
11. A method according to any of claims 1-10, characterized in that said additional semiconductor layer (5) is grown by Chemical Vapour Deposition (CVD) .
12. A method according to claim 11, characterized in that said additional semiconductor layer (5) is grown while heat¬ ing said semiconductor layer (1) at such a high temperature that the impurity dopants implanted in step a) are made electrically active and implantation damages are reduced.
13. A method according to claims 7, 8 and 12, characterized in that said temperature is higher than 1 500 °C .
14. A method according to any of claims 1-13, characterized in that in step a) the implantation is carried out for ob¬ taining a doping concentration in said surface layer (2) of 1015-1019 cm"3.
15. A semiconductor device having a semiconductor layer with a pn-junction (4) therein formed by carrying out the method according to any of claims 1-14.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP53433597A JP4691224B2 (en) | 1996-03-27 | 1997-03-26 | Method of manufacturing a semiconductor device using an implantation step and device manufactured by this method |
| DE69736891T DE69736891T2 (en) | 1996-03-27 | 1997-03-26 | METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT WITH AN IMPLANTING STEP |
| EP97915824A EP0890187B1 (en) | 1996-03-27 | 1997-03-26 | A method for producing a semiconductor device by the use of an implanting step |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| SE9601175-4 | 1996-03-27 | ||
| SE9601175A SE9601175D0 (en) | 1996-03-27 | 1996-03-27 | A method of producing a semiconductor device by using an implanting step and a device produced thereby |
| US08/636,952 US5674765A (en) | 1996-03-27 | 1996-04-24 | Method for producing a semiconductor device by the use of an implanting step |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO1997036319A1 true WO1997036319A1 (en) | 1997-10-02 |
Family
ID=26662560
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/SE1997/000534 WO1997036319A1 (en) | 1996-03-27 | 1997-03-26 | A method for producing a semiconductor device by the use of an implanting step and a device produced thereby |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US5674765A (en) |
| SE (1) | SE9601175D0 (en) |
| WO (1) | WO1997036319A1 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SE9700215L (en) * | 1997-01-27 | 1998-02-18 | Abb Research Ltd | Process for producing a SiC semiconductor layer of the 3C polytype on top of a semiconductor substrate layer utilizes the wafer bonding technique |
| SE9701724D0 (en) * | 1997-05-09 | 1997-05-09 | Abb Research Ltd | A pn diode of SiC and a method of production thereof |
| JP4935741B2 (en) * | 2008-04-02 | 2012-05-23 | 三菱電機株式会社 | Method for manufacturing silicon carbide semiconductor device |
| JP6042658B2 (en) * | 2011-09-07 | 2016-12-14 | トヨタ自動車株式会社 | Method for manufacturing SiC semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4775882A (en) * | 1986-11-19 | 1988-10-04 | Rockwell International Corporation | Lateral bipolar transistor |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4945394A (en) * | 1987-10-26 | 1990-07-31 | North Carolina State University | Bipolar junction transistor on silicon carbide |
| US4947218A (en) * | 1987-11-03 | 1990-08-07 | North Carolina State University | P-N junction diodes in silicon carbide |
| US5270554A (en) * | 1991-06-14 | 1993-12-14 | Cree Research, Inc. | High power high frequency metal-semiconductor field-effect transistor formed in silicon carbide |
-
1996
- 1996-03-27 SE SE9601175A patent/SE9601175D0/en unknown
- 1996-04-24 US US08/636,952 patent/US5674765A/en not_active Expired - Lifetime
-
1997
- 1997-03-26 WO PCT/SE1997/000534 patent/WO1997036319A1/en active IP Right Grant
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4775882A (en) * | 1986-11-19 | 1988-10-04 | Rockwell International Corporation | Lateral bipolar transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| SE9601175D0 (en) | 1996-03-27 |
| US5674765A (en) | 1997-10-07 |
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