WO1997024725A1 - High performance universal multi-port internally cached dynamic random access memory system, architecture and method - Google Patents
High performance universal multi-port internally cached dynamic random access memory system, architecture and method Download PDFInfo
- Publication number
- WO1997024725A1 WO1997024725A1 PCT/IB1996/000794 IB9600794W WO9724725A1 WO 1997024725 A1 WO1997024725 A1 WO 1997024725A1 IB 9600794 W IB9600794 W IB 9600794W WO 9724725 A1 WO9724725 A1 WO 9724725A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- data
- dram
- serial
- buffers
- interface
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
Abstract
Description
Claims
Priority Applications (11)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP50793497A JP3699126B2 (en) | 1995-12-29 | 1996-08-12 | High performance universal multiport internal cache dynamic random access memory system, structure and method |
KR1019980705020A KR100328603B1 (en) | 1995-12-29 | 1996-08-12 | General purpose multi-port internal cached DRAM system, architecture and method |
DE69610714T DE69610714T2 (en) | 1995-12-29 | 1996-08-12 | SYSTEM, ARCHITECTURE AND METHOD WITH HIGH PERFORMANCE FOR A UNIVERSAL MULTIPORT DYNAMIC DIRECT ACCESS MEMORY WITH INTERNAL CACHE MEMORY |
AU65295/96A AU721764B2 (en) | 1995-12-29 | 1996-08-12 | High performance universal multi-port internally cached dynamic random access memory system, architecture and method |
DK96925929T DK0870303T3 (en) | 1995-12-29 | 1996-08-12 | System, architecture and high performance approach for a universal multiport dynamic storage with random access with inte |
AT96925929T ATE197101T1 (en) | 1995-12-29 | 1996-08-12 | HIGH PERFORMANCE SYSTEM, ARCHITECTURE AND METHODS FOR A UNIVERSAL MULTIPORT DYNAMIC RANDOM ACCESS MEMORY WITH INTERNAL CACHE MEMORY |
EP96925929A EP0870303B1 (en) | 1995-12-29 | 1996-08-12 | High performance universal multi-port internally cached dynamic random access memory system, architecture and method |
IL12513596A IL125135A (en) | 1995-12-29 | 1996-08-12 | Dram architecture |
CA002241841A CA2241841C (en) | 1995-12-29 | 1996-08-12 | High performance universal multi-port internally cached dynamic random access memory system, architecture and method |
HK99103219A HK1018342A1 (en) | 1995-12-29 | 1999-07-27 | High performance universal multi-port internally cached dynamic random access memory system, architecture and method |
GR20010400081T GR3035261T3 (en) | 1995-12-29 | 2001-01-17 | High performance universal multi-port internally cached dynamic random access memory system, architecture and method |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/581,467 US5799209A (en) | 1995-12-29 | 1995-12-29 | Multi-port internally cached DRAM system utilizing independent serial interfaces and buffers arbitratively connected under a dynamic configuration |
US08/581,467 | 1995-12-29 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO1997024725A1 true WO1997024725A1 (en) | 1997-07-10 |
WO1997024725A9 WO1997024725A9 (en) | 1997-10-09 |
Family
ID=24325313
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IB1996/000794 WO1997024725A1 (en) | 1995-12-29 | 1996-08-12 | High performance universal multi-port internally cached dynamic random access memory system, architecture and method |
Country Status (15)
Country | Link |
---|---|
US (2) | US5799209A (en) |
EP (1) | EP0870303B1 (en) |
JP (1) | JP3699126B2 (en) |
KR (1) | KR100328603B1 (en) |
CN (1) | CN1120495C (en) |
AT (1) | ATE197101T1 (en) |
AU (1) | AU721764B2 (en) |
CA (1) | CA2241841C (en) |
DE (1) | DE69610714T2 (en) |
DK (1) | DK0870303T3 (en) |
GR (1) | GR3035261T3 (en) |
HK (1) | HK1018342A1 (en) |
IL (1) | IL125135A (en) |
TW (1) | TW318222B (en) |
WO (1) | WO1997024725A1 (en) |
Cited By (8)
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WO1999005604A1 (en) * | 1997-07-28 | 1999-02-04 | Nexabit Networks, Llc | Multi-port internally cached drams |
FR2779843A1 (en) * | 1998-06-16 | 1999-12-17 | Busless Computers | Serial multi port memory component comprising RAM memory bank assemblies for use in computer |
WO2000030421A1 (en) * | 1998-11-12 | 2000-05-25 | Nexabit Networks, Inc. | Electronic circuit board |
WO2000058840A1 (en) * | 1999-03-26 | 2000-10-05 | Nexabit Networks, Inc. | Ampic dram system |
AU760297B2 (en) * | 1997-04-30 | 2003-05-08 | Canon Kabushiki Kaisha | Memory controller architecture |
CN100390755C (en) * | 2003-10-14 | 2008-05-28 | 中国科学院计算技术研究所 | Computer micro system structure comprising explicit high-speed buffer storage |
CN1573723B (en) * | 2003-05-15 | 2010-05-05 | 三星电子株式会社 | Method and apparatus for communication via serial multi-port |
WO2011094218A2 (en) * | 2010-01-29 | 2011-08-04 | Mosys, Inc. | Hierarchical multi-bank multi-port memory organization |
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JP3733699B2 (en) * | 1997-06-20 | 2006-01-11 | ソニー株式会社 | Serial interface circuit |
US5918074A (en) * | 1997-07-25 | 1999-06-29 | Neonet Llc | System architecture for and method of dual path data processing and management of packets and/or cells and the like |
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KR100261218B1 (en) * | 1997-12-08 | 2000-07-01 | 윤종용 | Pin assignment method of semiconductor memory device & semiconductor memory device inputing packet signal |
US6622224B1 (en) * | 1997-12-29 | 2003-09-16 | Micron Technology, Inc. | Internal buffered bus for a drum |
US6085290A (en) * | 1998-03-10 | 2000-07-04 | Nexabit Networks, Llc | Method of and apparatus for validating data read out of a multi port internally cached dynamic random access memory (AMPIC DRAM) |
US6138219A (en) * | 1998-03-27 | 2000-10-24 | Nexabit Networks Llc | Method of and operating architectural enhancement for multi-port internally cached dynamic random access memory (AMPIC DRAM) systems, eliminating external control paths and random memory addressing, while providing zero bus contention for DRAM access |
US6003121A (en) * | 1998-05-18 | 1999-12-14 | Intel Corporation | Single and multiple channel memory detection and sizing |
US6112267A (en) * | 1998-05-28 | 2000-08-29 | Digital Equipment Corporation | Hierarchical ring buffers for buffering data between processor and I/O device permitting data writes by processor and data reads by I/O device simultaneously directed at different buffers at different levels |
US6122680A (en) * | 1998-06-18 | 2000-09-19 | Lsi Logic Corporation | Multiple channel data communication buffer with separate single port transmit and receive memories having a unique channel for each communication port and with fixed arbitration |
US6237130B1 (en) * | 1998-10-29 | 2001-05-22 | Nexabit Networks, Inc. | Chip layout for implementing arbitrated high speed switching access of pluralities of I/O data ports to internally cached DRAM banks and the like |
US6272567B1 (en) * | 1998-11-24 | 2001-08-07 | Nexabit Networks, Inc. | System for interposing a multi-port internally cached DRAM in a control path for temporarily storing multicast start of packet data until such can be passed |
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US7117275B1 (en) | 1999-01-04 | 2006-10-03 | Emc Corporation | Data storage system having separate data transfer section and message network |
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EP0340668A2 (en) * | 1988-05-06 | 1989-11-08 | Hitachi, Ltd. | Multi-processor system having a multi-port cache memory |
EP0471932A2 (en) * | 1990-07-27 | 1992-02-26 | International Business Machines Corporation | Virtual multi-port ram |
US5450355A (en) * | 1993-02-05 | 1995-09-12 | Micron Semiconductor, Inc. | Multi-port memory device |
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- 1995-12-29 US US08/581,467 patent/US5799209A/en not_active Expired - Lifetime
-
1996
- 1996-08-12 CN CN96180069A patent/CN1120495C/en not_active Expired - Fee Related
- 1996-08-12 KR KR1019980705020A patent/KR100328603B1/en not_active IP Right Cessation
- 1996-08-12 IL IL12513596A patent/IL125135A/en not_active IP Right Cessation
- 1996-08-12 CA CA002241841A patent/CA2241841C/en not_active Expired - Fee Related
- 1996-08-12 AU AU65295/96A patent/AU721764B2/en not_active Ceased
- 1996-08-12 DK DK96925929T patent/DK0870303T3/en active
- 1996-08-12 JP JP50793497A patent/JP3699126B2/en not_active Expired - Fee Related
- 1996-08-12 EP EP96925929A patent/EP0870303B1/en not_active Expired - Lifetime
- 1996-08-12 AT AT96925929T patent/ATE197101T1/en not_active IP Right Cessation
- 1996-08-12 DE DE69610714T patent/DE69610714T2/en not_active Expired - Lifetime
- 1996-08-12 WO PCT/IB1996/000794 patent/WO1997024725A1/en active IP Right Grant
- 1996-09-14 TW TW085111239A patent/TW318222B/zh not_active IP Right Cessation
-
1998
- 1998-07-06 US US09/110,929 patent/US6108725A/en not_active Expired - Lifetime
-
1999
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-
2001
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Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
AU760297B2 (en) * | 1997-04-30 | 2003-05-08 | Canon Kabushiki Kaisha | Memory controller architecture |
WO1999005604A1 (en) * | 1997-07-28 | 1999-02-04 | Nexabit Networks, Llc | Multi-port internally cached drams |
JP2001511559A (en) * | 1997-07-28 | 2001-08-14 | ネグザビット・ネットワークス,リミテッド・ライアビリティー・カンパニー | Multi-port internal cache DRAM |
AU748133B2 (en) * | 1997-07-28 | 2002-05-30 | Nexabit Networks, Llc | Multi-port internally cached drams |
FR2779843A1 (en) * | 1998-06-16 | 1999-12-17 | Busless Computers | Serial multi port memory component comprising RAM memory bank assemblies for use in computer |
WO2000030421A1 (en) * | 1998-11-12 | 2000-05-25 | Nexabit Networks, Inc. | Electronic circuit board |
WO2000058840A1 (en) * | 1999-03-26 | 2000-10-05 | Nexabit Networks, Inc. | Ampic dram system |
CN1573723B (en) * | 2003-05-15 | 2010-05-05 | 三星电子株式会社 | Method and apparatus for communication via serial multi-port |
CN100390755C (en) * | 2003-10-14 | 2008-05-28 | 中国科学院计算技术研究所 | Computer micro system structure comprising explicit high-speed buffer storage |
WO2011094218A2 (en) * | 2010-01-29 | 2011-08-04 | Mosys, Inc. | Hierarchical multi-bank multi-port memory organization |
WO2011094218A3 (en) * | 2010-01-29 | 2011-11-24 | Mosys, Inc. | Hierarchical multi-bank multi-port memory organization |
US8547774B2 (en) | 2010-01-29 | 2013-10-01 | Mosys, Inc. | Hierarchical multi-bank multi-port memory organization |
US9030894B2 (en) | 2010-01-29 | 2015-05-12 | Mosys, Inc. | Hierarchical multi-bank multi-port memory organization |
Also Published As
Publication number | Publication date |
---|---|
CA2241841C (en) | 1999-10-26 |
EP0870303A1 (en) | 1998-10-14 |
US5799209A (en) | 1998-08-25 |
TW318222B (en) | 1997-10-21 |
AU6529596A (en) | 1997-07-28 |
DE69610714D1 (en) | 2000-11-23 |
CA2241841A1 (en) | 1997-07-10 |
ATE197101T1 (en) | 2000-11-15 |
US6108725A (en) | 2000-08-22 |
GR3035261T3 (en) | 2001-04-30 |
DK0870303T3 (en) | 2001-02-26 |
KR100328603B1 (en) | 2002-10-19 |
AU721764B2 (en) | 2000-07-13 |
JP3699126B2 (en) | 2005-09-28 |
HK1018342A1 (en) | 1999-12-17 |
KR19990076893A (en) | 1999-10-25 |
IL125135A0 (en) | 1999-01-26 |
EP0870303B1 (en) | 2000-10-18 |
JP2000501524A (en) | 2000-02-08 |
CN1120495C (en) | 2003-09-03 |
IL125135A (en) | 2002-12-01 |
DE69610714T2 (en) | 2001-05-10 |
CN1209213A (en) | 1999-02-24 |
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