WO1997023832A1

WO1997023832A1 - An apparatus and method for adapting fibre channel transmissions to an industry standard data bus

Info

Publication number: WO1997023832A1
Application number: PCT/US1996/020232
Authority: WO
Inventors: Charles Edward Nogales; William Glenn Sooy
Original assignee: Unisys Corporation
Priority date: 1995-12-21
Filing date: 1996-12-20
Publication date: 1997-07-03
Also published as: US5809328A

Abstract

The present invention is an apparatus for adapting transmissions between an industry standard data bus of a host computer (10) having a host memory (13) and a fibre channel (14) coupled between said host computer (10) and a peripheral storage subsystem (16) having at least one disk drive (17-20), which apparatus comprises an interface logic (28) coupled between the industry standard bus and a local bus (33, 34) of the apparatus; a buffer memory (30) coupled to the local bus (33, 34); a multiplexor/control device (35) coupled to the local bus (33, 34) and being disposed for transmitting therethrough address and data; a fibre channel controller (31) disposed for formatting header and data structures that meet fibre channel protocol, which controller is coupled to the multiplexor/control (35); a gigabit link module (32) disposed for converting the header and data structures from a parallel format to a serial format and being coupled between the fibre channel controller (31) and the fibre channel (14); a microprocessor (22) disposed for providing service requests from the host to read and write data from the host memory (13) to and from the peripheral storage subsystem (16) via the buffer memory (30), the microprocessor (22) is coupled to a processor bus (25, 26); and, a bus control device (27) coupled between the processor bus (25, 26) and the local bus (33, 34) for providing service requests of the interface logic (28), the fibre channel controller (31) and the microprocessor (22), and for arbitrating control of the local bus (33, 34).

Description

TITLE: AN APPARATUS AND METHOD FOR ADAPTING FIBRE CHANNEL TRANSMISSIONS TO AN INDUSTRY STANDARD DATA BUS

FIELD OF THE INVENTION:

The present invention generally relates to an electronic apparatus and method of operation that provides an interface connection from an industry standard Peripheral Component Interconnect (^"PCI") bus to a very high speed serial channel defined herein as Fibre Channel.

BACKGROUND OF THE INVENTION:

Greater demands are being made in architecture, performance and implementation across the entire spectrum of computer systems, from supercomputers to PC's. Such demands are dictated by emerging data-intensive applications that require extremely high data rates. Demands for greater interconnection flexability are also being made. Today, high-performance workstations and intelligent mass storage systems are providing an alternative to the supercomputers used for such data- intensive applications in the past.

It is not uncommon today to cluster a number of workstations together, each operating independently, and linking them to mass storage and display subsystems. Moreover, desktop workstations need to access supercomputers from a distance, such as from a nearby building or across the street. Such developments are bringing about fundamental changes in the way that high- performance computers and peripherals need to be connected. Computers are becoming faster and capable of handling larger amounts of data. However, the network interconnnects between computers and I/O devices are not keeping pace and are not able to run at the high speeds necessary.

Many systems applications face a communications and I/O bottleneck, which is the result of the limited transmission speed of the prior art interconnect technologies. Fibre channel interconnects can help alleviate this problem by providing cost effective, high¬ speed interconnects between clustered workstations and massive, intelligent storage systems.

For example, a prior art fast SCSI parallel link from a disk drive to a workstation can transmit data at 160 megabits/sec, but it is restricted in length and requires the disk drive to be located no more than a few feet from the computer. In contrast, a quarter-speed Fibre Channel link transmits information at 200 megabits/sec over a single, compact optical cable pair up to 10 kilometers in length. It is noted that full speed Fibre Channel links transmit information at 800 Megabits/second. Note that the term ^"fibre" is used herein as a generic term, which can indicate either an optical or a metallic cable. Fibre channel is the general name of an integrated set of standards being developed by the American National Standards Institute (ANSI) which defines new protocols for flexible information transfer.

SUMMARY OF THE INVENTION:

It is therefore an object of the present invention to provide an apparatus that has high-bandwidth utilization with distance insensitivity.

It is another object of the apparatus of the present invention to support multiple cost/performance levels, from small systems to supercomputers.

Yet another object of the apparatus of the present invention is to provide the ability to carry multiple existing interface command sets, while preserving current driver software.

The present invention is an apparatus for adapting transmissions between an industry standard data bus of a host computer having a host memory and a fibre channel coupled between said host computer and a peripheral storage subsystem having at least one disk drive, which apparatus comprises an interface logic coupled between the industry standard bus and a local bus of the apparatus; a buffer memory coupled to the local bus; a multiplexor/control device coupled to the local bus and being disposed for transmitting therethrough address and data; a fibre channel controller disposed for formatting header and data structures that meet fibre channel protocol, which controller is coupled to the multiplexor/control; a gigabit link module disposed for converting the header and data structures from a parallel format to a serial format and being coupled between the fibre channel controller and the fibre channel; a microprocessor disposed for providing service requests from the host to read and write data from the host memory to and from the peripheral storage subsystem via the buffer memory, the microprocessor is coupled to a processor bus; and, a bus control device coupled between the processor bus and the local bus for providing service requests of the interface logic, the fibre channel controller and the microprocessor, and for arbitrating control of the local bus.

The foregoing and other objects, features and advantages of this invention will become apparent from the following more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawings in which like reference numerals refer to the same components throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS:

FIG. 1 is an overall block diagram of a system that employs the apparatus of the present invention.

FIG. 2 is a block diagram of the apparatus of the present invention. FIGS. 3A and 3B combined form a flow chart that illustrates the steps of the method of operation.

FIG. 4 is a diagram of a command control block (CCB) .

DESCRIPTION OF A PREFERRED EMBODIMENT: Referring now to FIG. 1, an overall block diagram of a system employing the present invention is shown wherein a terminal 10 is coupled to a file server 11. The file server 11 includes a fibre channel adapter (FCA) 12, which includes the apparatus of the present invention, and a memory 13. The FCA 12 is coupled to a fibre channel 14 having another end thereof coupled to a translater buffer 15 within a disk subsystem 16. The disk subsystem 16 includes fibre channel compatable disk drives 17 through 21.

With reference to Fig. 2, the apparatus of this invention is illustrated in block diagram form and is divided into two sections: a processor section and a local bus section. The processor section includes a microprocessor 22 (also referred to herein as processor 22), a RAM 23 used as an instruction memory, an EEPROM 24 used as a flash memory, an address bus 25 and a data bus 26 (which is sometimes collectively referred to herein as processor bus 25/26). In one embodiment that was built, an Intel 80960 was used as the microprocessor 22, which is available from Intel Corporation, Santa Clara, CA. Reference is made to a text book entitled "Microcontrollers" by Kenneth Hintz and Daniel Tabak for techniques in programming microprocessors, such as the Intel 80960.

The local bus section includes the local bus controller 27 (which is also coupled to the processor bus 25/26), a PCI bus interface logic 28 (which is also coupled to a PCI bus 29), a buffer memory 30 and a fibre channel (or "FC") controller 31. A gigabit link module 32 ("GLM") is coupled between the fibre channel 13 and the FC controller 31 by means of a parallel data bus 37. A local bus, comprising a data bus 33 and an address bus 34 (hereinafter sometimes collectively referred to as local bus 33/34), connects the bus control 27 with the PCI interface logic 28 and the buffer memory 30. The local bus 33/34 is the path for moving data between the buffer memory 30 and the devices on the fibre channel 13 via a multiplexor/control 35, the FC controller 31 and the GLM 32. The processor 22 has access to the local bus 33/34 for communication with the resources connected thereto.

Selection of the processor bus 25/26 for use by the processor 22 to communicate with its resources is by means of an address region decode. The processor 22 divides its four gigabyte address space into sixteen 256Mbyte regions using the four most significant address bits. Additionally, the fifth most significant address bit is used to select the upper or lower half of a region within the buffer memory 30. The following table illustrates the memory map for the microprocessor used in one embodiment.

MEMORY MAP

(ADDRESS RANGE FOR REGIONS)

RESERVE© "^■> 00000000 960 INTERNAL RAM 000003FF

PCI REGISTERS 08000000 08000133

RESERVED 10000000 EXPANSION ROM 1FFFFFFF

PCI HOST MEMORY 20000000 2FFFFFFF

DATA BUFFER 90000000 (BOOOOOOO) (512 KB) 9007FFFF (B007FFFF)

TACHYON REGISTERS A0000000 (WORD ONLY) A00001EC

CONTROL REGISTERS D0000000 (WORD ONLY) D000003C

CONTROL STORE E0000000 (512 KB) E007FFFF

FLASH MEMROY FFFC0000 (256 KB) FFFFFFFF

The processor 22 is isolated from the local bus 33/34 to improve performance. Since the microprocessor 22 is the only bus master on the processor bus 25/26, instruction fetches and ^"data" transfers to the control store 24 are free of contention from local bus 33/34 activity. When access to one of the resources on the local bus 33/34 is required, the processor 22 becomes one of three bus masters arbitrating for use of the local bus 33/34. The bus control 27 (which is a PLD) controls accesses to the local bus 33/34 and attempts to provide "fair" access to each of the three bus masters by using a least-recently-used arbitration scheme. The bus control 27 does not provide control of bus latency. Once an agent becomes the bus master, its length of ownership and therefore the latency for other agents, is determined by the type of transfer and programmable parameters (under microcode control), as well as access to the PCI bus 29. Resources on the processor bus 25/26 are not accessible by a PCI bus master or local bus master. When granted access to the local bus 33/34, the processor address bus 25 is driven onto the local address bus 34 by means of tri-state drivers, and the processor data bus 26 is extended to the local data bus 33 by means of tri- state transceivers. In one embodiment that was built, the bus control 27 includes a programmable logic device (PLD), such as a Mach 445 manufactured by Advanced Micro Devices, Inc., of Sunnyvale, CA. The PLD within the bus control 27 is programmed in accordance with the program set forth in Appendix A hereof.

By means of the local bus 33/34, the processor

22 has access to the buffer memory 30, registers within the PCI interface logic 28, and registers within the FC Controller 31 and other agents coupled to the PCI bus 29.

Each of these resources is defined as a separate processor region and the characteristics of those address regions are detailed in memory configuration registers of the processor (which are loaded by the microcode stored therein) .

The multiplexor/control 35 contains bi¬ directional registers and buffers and a programmable logic device ("PLD"), which has two major functions. First, the FC controller 31 has a multiplexed (i.e., shared address and data) I/O bus 36. The multiplexor/control 35 controls the separation and merging of the bus 36 with the local bus 33/34, depending upon the direction of data flow and upon which bus master (i.e., processor 22, PCI interface logic 28 or FC controller 31) is in control. The PLD receives information from the bus master and generates signals that control the bi-directional registers and buffers which carry out the separation/merging of the bus 36 with the local bus 33,34. Also, the PLD converts control signals from the bus master to signals understood by the target device (e.g., the buffer memory 30), or one of the other bus masters (e.g., processor 22 or PCI interface logic 28). The PLD within the multiplexor/control 35 in one embodiment that was built is as a Mach 220, which is availablle from Advanced Micro Devices, Inc.of Sunnyvale, CA. This PLD is programmed in accordance with the program set forth in Appendix B hereof.

When the FC controller 31 is the bus master, it can provide a single address followed by up to eight words of data. The intent of this operation is to read/write data at the original address, and the following seven sequential addresses. Other elements in the design require an address for each word of data. The PLD contains a counter that stores and increments the original address supplied by the FC controller 31. By using the local bus 33/34, each of the three bus masters (the processor 22, the PCI interface logic 28, and the FC controller 31) has access to several resources. The processor can extend its data bus 25 to the local bus 33/34 by means of the bus control logic 27 to gain access to registers within the PCI interface logic 28; PCI memory 13, registers within the FC controller 31, as well as the buffer memory 30. A PCI bus master can access registers within the PCI interface logic 28; buffer memory 30, and the internal registers within the FC controller 31. Additionally, the FC controller 31 can access the internal registers of the PCI Interface Logic 28, PCI memory 13 or buffer memory 30.

A PCI bus master can communicate with the processor 22 via mailbox and doorbell registers which are part of the PCI Interface Logic 28, or by transfeering information to a designated area in the buffer memory 30.

The FC controller 31 manages the protocol for sending and receiving information on the fibre channel 14. To achieve this, the processor 22 and the FC controller 31 share data structures and data buffers that are maintained in the buffer memory 30. The FC controller 31 provides a connection between the GLM 32 and local bus 33/34 via the address/data bus 36 and the multiplexor/control 35.

The processor 22 can access the buffer memory 30 by using either addresses in processor region 9 or 11; wherein the memory configuration registers define region 9 as little endian and region 11 as big endian. The term "endian" refers to the sequence in which a multi- byte word is transferred. For example, "little endian" means that the least significant byte is transferred first with the most significant byte being transferred last. The term ^"big endian" refers to the transfer of the most significant byte first, etc. This allows the processor to move information between two locations in the buffer memory (potentially the same location) and change the byte ordering at the same time. This ability to change endianess, by reading from one region and writing to another is useful when dealing with commands or status information. It is also useful when reading from or writing to disk drives that may be formatted differently.

A specific example of endianness occurs at the PCI interface logic 28. The PCI bus is in little endian format and the FC controller 31 assumes/supplies data in big endian format. In order to provide compatible data between the two systems, a byte swap is performed at the

PCI interface 28 to the local bus 33/34. Thus, the PCI interface logic 28 provides the PCI bus 29 to local bus

33/34 interface. The logic 28 can function as either a bus master or target on both the PCI 29 and the local bus

33/34. In one embodiment a PCI 9060, which is available from PLX Technology, Inc. of Mountain View, CA, was used for the logic 28. The PCI 9060 has four sets of internal registers and operates in three modes: The register access mode, the DMA mode and the Pass-Through mode.

The buffer memory 30 is constructed as a 512 KB by 9 block of SRAM and is accessible by the local bus 33/34. It serves several purposes: first it contains queues which are common to the microprocessor 22 and the FC controller 31; second, it can be used for temporary data storage and it can be used for communication between the PCI interface logic 28 and the microprocessor 22. In one embodiment, an HP Tachyon chip, which is available from Hewlett Packard Company of Palo Alto, CA, was used for the FC Controller 31. This chip performs as an interface between the GLM 32 and the multiplexor control 35. For this function it uses internal configuration registers, and operates from queues maintained in the buffer memory 30. On the GLM interface side, 8 bits of raw data are encoded into 10 bit code words for transmission purposes. This encoding schem is described by Widner et al in "A DC Balanced Partitioned Block, 8B/10B Transmission Code" in the IBM Journal of Research and Development, Volumn 27, 1983, pp446-451. The purpose for this encoding is to maximize the number of binary data transmissions. The high transmission data rate improves the ability of the receiver to stay locked in synchronism with the transmitter. A decoding operation is performed on receipt of 10 bit code words to 8 bit data bytes. / / / / / / / / / / / / / / / / The FC Controller 31 also implements a protocol for organizing data frames of the code words for transmitting and receiving, which protocol is disclosed in U.S. Patent No. 5,260,933, entitled ACKNOWLEDGEMENT PROTOCOL FOR SERIAL DATA NETWORK WITH OUT-OF-ORDER DELIVERY, by G.L. Rouse. The Fibre Channel Specifications used in building one embodiment of the present invention include the following ANSI Standards:

Fibre Channel FC-PH X3Tll/Project Rev. 4.3

Physical & 755D

Signalling

Interface

Fibre Channel FC-AL X3Tll/Projcet Rev. 4.5

Arbitrated 960D

Loop

Fibre Channel FCP X3T10 Rev. 012

Protocol for /X3.2

SCSI 69- 199X

In summary, the operation of the Fibre Channel Apparatus of the present invention is illustrated in FIGS. 3A and 3B. The sequence begins when the host (i.e., the file server 11) has an operation to perform (as depicted by a block 45). The driver (host code) writes preliminary information into the mailboxes and doorbell registers, which are part of the PCI Controller 28 (block 46). The act of writing to the doorbell register causes an interrupt to the microprocessor 22 to be generated (block 47). Next, the microprocessor 22 interrogates the information in the mailboxes to determine what action is required, to what device and where in the host memory 13 a command control block (CCB) is stored (block 48) . Using a direct memory access (DMA) controller, which is part of the PCI Interface Logic 28, the processor 22 moves the CCB from the host memory 13 to the buffer memory 30 (block 49). From codes within the CCB, the processor 22 determines what operation is to be performed (i.e, is it a write or a read operation), how much data is to be transferred (block 50), and where in the host memory 13 data is located (for a write operation) or to be stored (read operation) (block 51) .

At this juncture, it is determined if the command is a read or a write operation (decision diamond 52). For a write data operation, the processor 22 sets up shared data structures in the buffer memory 30 (block 53), which describes the operation and the data location for the FC Controller 31. Using the DMA controller within the PCI Interface Logic 28, the processor 22 moves the write data from the host memory 13 to the buffer memory 30 (block 54), and then informs the FC Controller 31 that a command and data are available by writing to registers within the FC Controller 31 (block 55). In preparation for the data transfer, the FC Controller 31 reads the shared data structures from the buffer memory 30, and then transfers data from the buffer to the GLM 32 (block 56), which performs a parallel to serial conversion (block 57). The data is subsequently transmitted over the Fibre Channel 14 to a disk drive for storage.

For a read data operation, a branch is taken from the diamond 52 to the flow chart illustrated in FIG. 3B as denoted by a connector ^"A". The processor 22 sets up shared structures in the buffer memory 30 that describe the operation and data destination for the FC controller 31 (block 58); and, then informs the FC Controller that a command is available by writing to registers therein (block 59). In preparation for the data transfer, the FC Controller 31 reads the shared data structures from the buffer memory 30 (block 60), and then transfers data from a disk drive over the fibre channel 14 via the GLM 32 (block 61) (which performs a serial to parallel conversion-block 62) to the buffer memory 30. Using the DMA controller within the PCI Interface Logic 28, the processor 22 directs moving of the read data from the buffer memory 30 to the host memory 13 (block 63).

FIG. 4 illustrates the organization of the command control block (CCB) into a command part and meta data (information about data) part, such as the location of the data in the host memory 13, for example, and the length of the data block.

While the invention has been particularly shown and described with references to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therin without departing from the spirit and scope of the invention as defined by the appended claims.

APPENDΓXA

"MACROS

FLASH MACRO {( {REGION = ^ΛbF) & A27 )}; CSTORE MACRO {( (REGION = ^ΛhE) & !A27 )}; CREG MACRO {( (REGION — ^ΛhD) & !A27 )};

RES_C MACRO {( (REGION = ^ΛhC) )}; "RESERVED

BEDB2 MACRO {( (REGION — ^ΛhB) & A27 )}; "BIG ENDIAN DATA BUFFER 2 - NOT

USED

BEDB1 MACRO {( (REGION = ^ΛhB) & !A27 )}; "BIG ENDIAN DATA BUFFER 1 TAC2 MACRO {( (REGION — ^ΛhA) & A27 )}; TACH. 2 - NOT USED TAC1 MACRO {( (REGION — ^ΛhA) & !A27 )}; "TACH. 1

LEDB2 MACRO {( (REGION = ^Λh9) & A27 )}; "LITTLE ENDIAN DATA BUFFER 2 - NOT USED LEDB1 MACRO {( (REGION = ^Λh9) & !A27 )}; "LITTLE ENDIAN DATA BUFFER 1

RES 3 MACRO {( (REGION <= ^Λh8)

& (REGION >= ^Λh3) ) } ; "RESERVED PCIMEM MACRO {( (REGION = ^Λh2) )}; "PCI MEMORY

EXPROM MACRO (( (REGION = ^Λhl) )}; "EXPANSION ROM PLXREG MACRO {( (REGION — ^Λh0) & A27 )}; "PLX REG

RES_0 MACRO {( (REGION — ^Λh0) & !A27 )}; "RESERVED

DB2 MACRO {( BEDB2 # LEDB2 )}; "DATA BUFFER 2 - NOT USED DBl MACRO {( BEDB1 # LEDB1 )}; "DATA BUFFER 1 FC2 MACRO {( TAC2 # DB2 )}; "FIBRE CHANNEL 2 - NOT USED FC1 MACRO (( TAC1 # DBl )}; "FIBRE CHANNEL 1

PCIACC MACRO {( PLXREG # PCIMEM )};

TACHOK MACRO {( DBl # PCIMEM )}; PLXOK MACRO {( DBl # EXPROM # TACl )};

TBREQ MACRO {(((TREQ = ^Λhl) )

# (( TREQ = ^Λh2) & PAFULLJ )}; uPBREQ MACRO {( !EXTREQ_)};

T_TARGET MACRO {(((BCS.FB = uPWAIT)&TACl )

# ((BCS.FB = PLXWAIT)& TACl ))};

P_TARGET MACRO {( ((BCS.FB = uPMST ) & PCIACC & !EXTBGNT_.FB ) # ((BCS.FB = uPWATT ) & PCIACC )

# ((BCS.FB = TACMST ) & PCIACC )

# ((BCS.FB -= TACTURN) & PCIACC )

# ((BCS.FB = TACWAIT) & PCIACC ) )};

EQUATIONS

"ENABLE OUTPUTS WHEN TSJ IS HI

MASTERS.OE = TS_ ; "3 TARGETS.OE = TS_ ; "2

BCS.OE = TS_ ; "4 "SPARE.OE = TS_ ;

[ BTERM_ , PRDYTN_, PBOFF , PLOCK_ , PPAR2D_, DPAR2P_ , TBG_ , LERR_ ].OE = TS_ ; [ PRDYERR_, PECLK , PEINT_, RDY2uP_, TRETRY_, LCHD2uP_, TTNT_, NMI_ ].OE = TS ; [ TESTPT ].OE = TS_ ;

"ENABLE OUTPUTS WHEN TSJ IS HI AND TACH. IS THE MASTER

TRDY_.OE = ( TS_ & !TBM_ ); "DEFAULT FEEDBACK = .PIN

"ENABLE OUTPUTS WHEN TS ' IS HI AND TACH. IS THE MASTER OR THE BUS IS IDLE

BLAST_.OE = (( TS_ & !TBM_ )

# ( TS_ & (BCS.FB — IDLE )));

"ENABLE OUTPUTS WHEN TSJ IS HI AND TACH. IS NOT THE BUS MASTER AVCS_.OE = ( TS_ & TBM_ ); "AV.CS/ IS ACTIVE FOR 1 CLK

"ENABLE OUTPUTS WHEN TSJ IS HI AND PLX IS NOT THE BUS MASTER ADS_.OE - ( TS_ & IPBGNT ); "ADS/ IS ACTIVE FOR 1 CLK

"CLOCK AND RESET BCS.CLK = CLK ; BCS.AR = IRESET

[ PE1NT_, DBSEL_, PCIRSEL_, RDY2uP_, PRDYIN_, LERR_, PRDYERR_, PBOFF J.CLK = CLK

[ PEINT_, DBSEL_, PCIRSEL_, RDY2uP_, PRDYIN_, LERR_, PRDYERR_, PBOFF J.AR = !RESET_ ;

[ AVCS_,TINT_,NMI_,LCHD2uP_,EXTBGNT_J.CLK= CLK ; [AVCS_,TTNT_,NMI_,LCHD2uP_,EXTBGNT_J.AR = !RESET_; [PRDY2T,EOBl,EOB2, INTCNT,ERRCNT,USRCNT,ADSl,BLASTl,LTBRl,LTBROJ.CLK= CLK ; "NODES

[PRDY2T,EOBl,EOB2,INTCNT,ERRCNT,USRCNT, ADSl,BLASTl,LTBRl,LTBROJ.AR = !RESET_;

EXTBGNT_.D = ( (BCS.FB = uPMST ) # (BCS.FB = uPWAIT )); PBGNT = ( (BCS.FB = PLXMST ) # (BCS.FB — PLXWATT));

TBM_ = !( (BCS.FB = TACMST ) # (BCS.FB = TACTURN) # (BCS.FB — TACWATT );

TBG_ = ! ( (BCS.FB = TACMST ) # (BCS.FB = TACTURN) # (BCS.FB = TACWATT));

PRDY2T.D = ( ( !TBM_ & PCIMEM & !PRDYOUT_ & WRT ) "LATCH FIRST PLX READY (DIRECT WRT) - NOT USED

# ( !TBM_ & PCIMEM & PRDY2T.Q & AVCS_.PIN )); "HOLD

"DRIVEN WHEN TACH. IS THE MASTER "TACH. ONLY NEEDS 1 CLK LONG RDY TRDY_ = !(( (BCS.FB = TACWATT) & !DBSEL_.FB & !WRT ) "ACC TO DB

# ( (BCS.FB = TACWATT) & !DBSEL_.FB & WRT & EOB ) "DELAY RDY UNTIL LAST DATA XFER

# ( (BCS.FB == TACWATT) & PCIMEM & !WRT & !PRDYOUT_ ) "DIRECT MASTER RD

# ( (BCS.FB = TACWATT) & PCIMEM & WRT & !PRDYOUT_ ) "DIRECT MASTER WRT

" # ( (BCS.FB = TACWATT) & PAFULL_ & WRT & EOB & PRDY2T.Q ) DIRECT MASTER WRT - DELALY RDY

UNTIL PLX FIFO IS EMPTY # ( (BCS.FB = TACWATT) & !LERR_.FB )); "ILLEGAL ACC

"TACH 2PLXREG = LOCAL ERROR

BLASTl.D = (( (BCS.FB = TACWATT) & PRDYOUT_ & PCIMEM & (TREQ = ^Λh3) ) "SET

# ( BLASTl. Q & PRDYOUT . )); "HOLD UNTIL PLX IS RDY

"DRIVEN WHEN TACH. IS THE MASTER BLAST_ = !(( (BCS.FB = TACWATT) & PCIMEM & (TREQ = ^Λh3) ) "DIRECT MASTER ACCESS

# ( BLAST1.Q ));

PC1RSEL_.D = (( (BCS.FB = uPMST ) & PLXREG & !EXTBGNT_.FB )

# ( (BCS.FB =^■=^■ uPWAJ ) & PLXREG & RDY2uP .FB )

# ( (BCS.FB = uPWAIT ) & PLXREG & BLAST_.PIN )); "TACH 2 PLXREG = LOCAL ERROR

DBSEL_.D = (( (BCS.FB — uPMST ) & DBl & !EXTBGNT_.FB )

# ( (BCS.FB — uPWAIT ) & DBl & BLAST_.PIN )

# ( (BCS.FB = uPWAIT ) & DBl & !BLAST_.PTN & !WRT ) "HOLD DURNING

READS

# ( (BCS.FB = PLXMST ) & DBl & !ADS_.PIN )

# ( (BCS.FB = PLXWATT) & DBl & BLAST_.PTN )

# ( (BCS.FB = TACMST ) & DBl & !AVCS_.PIN ) # ( (BCS.FB = TACWATT) & DBl & !AVCS_.PIN ) "STREAM

# ( (BCS.FB = TACTURN) & DBl )

# ( (BCS.FB = TACWATT) & DBl & !EOB )); "PLX IS THE BUS MASTER PRDYTN_.D = (( (BCS.FB = PLXMST ) & DBl & !ADS_.PIN ) "ACC. TO DB

# ( (BCS.FB = PLXWATT) & !DBSEL_.FB & BLAST_.PIN )

# (( BCS.FB = PLXMST ) & EXPROM & !ADS_.PIN ) "ACC. TO EXPROM

# ( (BCS.FB = PLXWATT) & TACl & !TRDY_.PIN ) "ACC. TO TACH.

# ( (BCS.FB = PLXWATT) & TACl & (ERRCNT.Q = ^Λh7)) "TACH. ERROR

# ( (BCS.FB — PLXWATT) & !LERR_.FB )); "ILLEGAL ACC

BTERM_ = 1 ; PLOCK_ - 1 ;

PBOFF.D = 0 ; "PLX WILL RELEASE BUS IF PBOFF = 1, DURING DMA'S. "IE. REQUEST BY uP/TACH

- (( PBUSREQ & !TBR1_ )

# ( PBUSREQ & !TBR0_ )

# ( PBUSREQ & !EXTREQ_ ));

"REM: DURING DIRECT MASTER ACCESSES, THE uP OR TACH. " IS THE BUS MASTER - NOT PLX

TRETRY = 1 ; "READS ONLY

AVCS_.D = (( (BCS.FB = uPMST ) & TACl & !EXTBGNT_.FB ) "DRIVEN WHEN TACH. IS THE TARGET ϋ ( (BCS.FB = PLXMST ) & TACl & !ADS_ )); "PLX 2TACH

ADS 1.D = (( (BCS.FB = uPMST ) & PLXREG & !EXTBGNT_.FB ) # ( (BCS.FB = uPMST ) & PCIMEM & !EXTBGNT_.FB ));

ADS_ = J(( ADS1.FB ) "DRIVEN WHEN PLX IS NOT THE BUS MASTER " # ( (BCS.FB = TACWATT) & IAVCS .PIN ) STREAMING

# ( (BCS.FB = TACMST ) & !AVCS .PIN )); "TACH 2PLXREG (LOCAL.ERR)

RDY2uP .D = (( (BCS.FB = uPMST ) & DBl & !EXTBGNT_.FB & WRT ) "DELAY READ RDY 1 CLK

# ( (BCS.FB = uPWAIT ) & DBl )

# ( (BCS.FB — uPWAIT ) & PCIACC & !PRDYOUT_ ) # ( (BCS.FB = uPWAIT ) &. TACl & !TRDY_.PIN ) if ( (BCS.FB — uPWAIT ) & TACl & (ERRCNT.Q — ^Λh7) )); "TACH. ERROR DPAR2P_ = (( PBGNT & WRT ) # ( PJTARGET & IWRT ));

PPAR2D_ = !(( PBGNT & WRT ) # ( PJTARGET & !WRT ));

LCHD2uP_.D = (( (BCS.FB — uPWAIT ) & !WRT & PLXREG & IPRDYOUT ) "SET

# ( (BCS.FB = uPWAIT ) & !WRT & TACl & ITRDY .PIN ) "SET

# ( (BCS.FB — uPWAIT ) & !LCHD2uP_.FB ) "HOLD

# ( (BCS.FB = 11 ) & !LCHD2uP_.FB )); "HOLD

PECLK = (( !TBM_ & !WRT & !TRDY_ & CLK ) "MODEL GIVES 15 ns DELAY, ie. 1 ns HOLD, REAL

# ( T TARGET & WRT & ITRDY & CLK ));

PEINT_.D = (( !PE_ ) "SET (D2T.PE) - WILL NOT BE SET EF

# ( !PEINT_.FB & CLRPE_ )); "RDY ERROR IS DET. (LAST WORD )

LERR_.D = (( !TBM_ & IAVCS .PIN & ITACHOK ) "TACH. ILLEGAL ACCESS

# ( !TBM_ & !LERR_.FB ) "HOLD

# ( PBGNT & !ADS_.PIN & IPLXOK ) "PLX ILLEGAL ACCESS

# ( PBGNT & !LERR_.FB ) "HOLD

# ( !TBM_ & PBUSREQ & PCIMEM ) "POTENTIAL DEAD LOCK

" ACCESS TO DB " ACCESS TO PLXREG "NO WAY TO BACKOFF TACH

# ( lEXTBGNT .FB & PBUSREQ & PCIMEM )); "POTENTIAL DEAD LOCK

" ACCESS TO DB " ACCESS TO PLXREG " ACCESS TO TACH "NO WAY TO BACKOFF uP (BTERM )

EOB1.D = ( EOB );

EOB2.D = ( EOB & IEOB1.Q );

PRDYERR_.D = ( PRDYOUT_ & !TBM_ & PCIMEM & IWRT & IEOB1 ); "CHECK FOR RDYS WHILE TACH.

"IS READING FROM PCI MEMORY TNTCNT.D = (( !TIRQ_ & [0,0,0] ) "LOAD

# ( INTCNT = ^Λh7) & !TTNT_.FB & (INTCNT.Q +1) )); "COUNT TO 7 AND STOP

TTNT_.D = (( !TIRQ_ )

# (! (INTCNT = ^Λh7) & !TTNT_.FB ));

ERRCNT.D = (( ITAC1 & [0,0,0J ) "LOAD

# ( TERR_& [0,0,0] ) "LOAD

# ( (BCS.FB = uPWAIT ) & TACl & !TERR_ & !(ERRCNT.Q — ^Λh7) & (ERRCNT.Q +1)) "COUNT

# ( (BCS.FB = PLXWATT) & TACl & !TERR_ & !(ERRCNT.Q = ^Λh7) & (ERRCNT.Q +1)) "COUNT

# ( TACl &!TERR_& (ERRCNT.Q = ^Λh7)& (ERRCNT.Q ) )); "HOLD

USRCNT.D = (( !USERO_ & [0,0,0] ) "LOAD # ( !(USRCNT = ^Λh7) & !NMI_.FB & (USRCNT.Q +1) )); "COUNT TO 7 AND STOP

NMI_.D = (( !SERR_ )

# (!USERO_ ) # (! (USRCNT == ^Λh7) & !NMI_.FB ));

LREQ.D = (( TREQ & !AVCS_.PIN ) # ( LREQ.Q& AVCS_.PIN));

"TESTPT =PEINT_.FB&TERR_&(TIRQ_&TINT_) ; PRDYERR_.FB & LERR_.FB ARE PART OF INTO TESTPT = PEINT_.FB & TERR_ ; "PRDYERR_.FB & LERR_.FB ARE PART

OF INTO

STATE DIAGRAM BCS "LOCAL BUS CONTROL STATE MACHINE

STATE IDLE: "STATE 0 - IDLE

CASE ( uPBREQ ): uPMST ;

( luPBREQ & PBREQ ): PLXMST ;

( luPBREQ & IPBREQ & TBREQ ): TACMST ; ( luPBREQ & IPBREQ & ITBREQ ): TDLE ;

ENDCASE;

STATE uPMST: "STATE C - uP IS THE BUS MASTER

CASE ( !EXTBGNT_.FB ): uPWAIT ; " ( EXTBGNT_.FB ): uPMST ; "

ENDCASE; STATE uPWAIT: "STATE D - uP IS THE BUS MASTER

CASE

( BLAST_.PDM # RDY2uP_.FB ): uPWAIT ; "WATT FOR PLX TACH. RDY ( !BLAST_.PTN & !RDY2uP_.FB ): II ; "uP DMAS ARE MULΗ-BURSTS, NOT ONE OWNERSHIP

ENDCASE;

STATE II: "STATE E - IDLE 1 - WHERE TO NEXT ?

CASE

( PBREQ ): PLXMST ;

( IPBREQ & TBREQ ): TACMST ;

( uPBREQ & IPBREQ & ITBREQ ): uPMST ; ( luPBREQ & IPBREQ & ITBREQ ): IDLE ;

ENDCASE;

STATE PLXMST: "STATE 4 - PLX IS THE BUS MASTER

CASE ( ADS_.PIN ): PLXMST ;

( !ADS_.P1N ): PLXWATT;

ENDCASE; STATE PLXWATT: "STATE 5 - PLX IS THE BUS MASTER

CASE ( PBREQ ): PLXWATT; "WATT FOR PLX TO GIVE UP THE BUS

( IPBREQ ): 12 ; "PLX DMA'S CAN BE ONE OWNERSHIP, MULΗ-BURSTS

ENDCASE;

STATE 12: "STATE 6 - IDLE 2 - WHERE TO NEXT ? CASE

( TBREQ ): TACMST ;

( uPBREQ & ITBREQ ): uPMST ;

( luPBREQ & PBREQ & ITBREQ ): PLXMST ; ( luPBREQ & IPBREQ & ITBREQ ): IDLE ;

ENDCASE;

STATE TACMST: "STATE 8 - TACHYON IS THE BUS MASTER

CASE ( AVCS_.PTN ): TACMST ; ( !AVCS_.PIN & WRT ): TACWATT; ( !AVCS_.PTN & IWRT ): TACTURN;

ENDCASE;

STATE TACWATT: "STATE 9 - TACHYON IS THE BUS MASTER

CASE ( IEOB & AVCS_.PIN ): TACWATT;

( EOB & I AVCS_.PIN & IWRT ): TACTURN; "CONT. READ STREAMING - DIR

MST ( EOB & !AVCS_.PIN & WRT ): TACWATT; "CONT. WRITE STREAMING - DTR

MST

( EOB & AVCS_.PIN & (TREQ — LREQ) ): TACWATT; "WATT FOR TACH TO GTVE-uP

THE BUS

( EOB & AVCS_.PIN & !(TREQ = LREQ) & ITERR ): TACWATT; "IGNORE REQ CHANGE, IF T.ERROR IS TRUE

( EOB & AVCS_.PIN & ItTREQ = LREQ) & TERR_ ): 13 ; ENDCASE; STATE TACTURN: "STATE A - TACHYON IS THE BUS MASTER GOTO TACWATT;

STATE 13 : "STATE B - IDLE 3 - WHERE TO NEXT ?

CASE

( uPBREQ ): uPMST ;

( luPBREQ & PBREQ ): PLXMST ;

( luPBREQ & IPBREQ & TBREQ ): TACMST ; ( luPBREQ & IPBREQ & ITBREQ ): IDLE ;

ENDCASE;

APPENDIXB

"MACROS LOAD MACRO {( !TBM_ & !AVCS_ )};

RDRDY MACRO {( !TBM_ & ILT2 & !TRDY_ )}; "TACH. READS - WATT FOR 1ST RDY

EQUATIONS

"ENABLE OUTPUTS D? TS IS HI:

XLEN.OE = TS_ ; "3

[ ADD2T_, DATA2T_, T2ADD, T2DATA_, HLDADD_, LD , ENPE , EOB , CNTEN ].OE = TS_ ;

"ENABLE OUTPUTS IF TS/¹ IS HI AND TACH. IS THE TARGET (1 CLK)

AOE - TS_ & TBM_ & !AVCS_ ;

A.OE = AOE ; "5 DEFAULT FEEDBACK = PIN

TYPE.OE = AOE ; "3 "ENABLE OUTPUTS EF TS/" IS HI AND TACH. IS THE MASTER

BOE = TS & ITBM

B42.0E = BOE ; "3 DEFAULT FEEDBACK = PIN

BEN.OE = BOE ; "4

WRT.OE = BOE ; "

"CLOCK AND RESET

[ B42, CNTEN, XLEN, EOB, T2ADD J.CLK = CLK ; [ B42, CNTEN, XLEN, EOB, T2ADD J.AR = IRESET

[ LTIN, TURN, ENPEl, EOBl, EOB2, D2T1, D2T2, T2D1, T2D2, HLDADD J.CLK = CLK ; "NODES [ LTIN, TURN, ENPEl, EOBl, EOB2, D2T1, D2T2, T2D1, T2D2, HLDADD J.AR = !RESET_ ;

LTIN.D = (( TYPE & !AVCS_ ) "SET

# ( LTTN.Q & AVCS_ & !TBM_ ) "HOLD # ( TBM_ )); "RESET TO HI

TURN.D = (( TBM_ & I AVCS_ & IWRT ) "READ FROM TACH # ( !TBM_ & !AVCS_ & IT2 )); "TACH. READS

WRT = (( T2 & I AVCS_ ) "DRIVEN WHEN TACH. IS THE MASTER # ( LT2 & AVCS_ )); BEN3 = 0; "DRIVEN WHEN TACH. IS THE MASTER

BEN2 = 0;

BEN1 = 0;

BENO = 0;

A4 = B4; "DRIVEN WHEN TACH. IS THE TARGET

A3 = B3;

A2 = B2;

Al = !(BEN = 0);

AO = !(BEN = 0);

T2 = WRT; "DRIVEN WHEN TACH. IS THE TARGET

Tl = !(BEN = 0);

TO = !(BEN = 0);

ADD2T_ = !( TBM_&!AVCS_); "ONE CLK ONLY

D2T1.D = (( !TBM_ & !AVCS_ & !T2 ) "TACH. READS

# ( !TBM_ & TURN.Q )

# ( !TBM_& IWRT.COM & D2T1.Q & IEOB.FB ) "HOLD

# ( !TBM_ & IWRT.COM & D2T1.Q & lEOBl.Q )); "HOLD

D2T2.D - (( TBM_& WRT & !AVCS_ ) "WRITE TO TACH.

# ( TBM_ & WRT & D2T2.Q & TRDY_ )); "HOLD UNTIL TACH. IS RDY

DATA2T_ = !( D2T1.Q#D2T2.Q);

T2ADD.D = !TBM_ ;

T2D1.D = ((!TBM_& T2 & !AVCS_ ) "TACH. WRITES

# ( !TBM_ & WRT.COM & T2D1.Q & IEOB.FB )); "HOLD

T2D2.D = (( TBM_&!WRT & !AVCS_ ) "READ FROM TACH.

# ( TBM_ & IWRT & T2D2.Q & TRDY_ )); "HOLD UNTIL TACR IS RDY

T2DATA_ = !( T2D1.Q # T2D2.Q );

HLDADD.D = (( !TBM_ & !AVCS_ )

# ( !TBM_ & AVCS_ & IEOB2.Q & HLDADD.Q ));

HLDADD_ = !(( !TBM_ & !AVCS_ ) # ( HLDADD.Q )); ENPE1.D = ( !DATA2T_ );

"74833 ASYNC CLR/ ENPE = ( !DATA2T_ TACH. READS or WRITES TO TACH.

# ENPEl Q ); "HOLD/DONT CLR FOR 1 CLK (PE -> LATCH)

LD = ( LOAD );

CNTEN.D = (( LOAD & T2 & !(!T1 & ITO ) ) "SET FOR TACH. WRITES >1

# ( RDRDY & IEOB.FB & !(!LT1 & ILTO) ) "SET FOR TACR READS >1, WHEN 1ST RDY IS RECEIVED

# ( CNTEN.FB & IEOB.FB )); "HOLD

"DRIVEN WHEN TACH. IS THE MASTER B42.D = (( LOAD & A42.PIN ) "LOAD # ( ILOAD & ILT2 & IRDRDY & ICNTEN.FB & IEOB.FB & (B42.FB ))

"HOLD

# ( ILOAD & ILT2 & RDRDY & !(!LT1 & ILTO) & ICNTEN.FB & IEOB.FB & (B42.FB +1)) "COUNT - 1ST READ

# ( ILOAD & ILT2 & CNTEN.FB & IEOB.FB & (B42.FB +1)) "COUNT

# ( ILOAD & LT2 & ICNTEN.FB & IEOB.FB & (B42.FB )) "HOLD

# ( ILOAD & LT2 & CNTEN.FB & IEOB.FB & (B42.FB +1))); "COUNT

XLEN.D = (( LOAD & IT1 & ITO & LEN1 ) "LD - 1 WORD XFER

# ( LOAD & IT1 & TO & LEN2 ) "LD - 2 WORD XFER

# ( LOAD & Tl & ITO & LEN4 ) "LD - 4 WORD XFER

# ( LOAD & Tl & TO & LEN8 ) "LD - 8 WORD XFER # ( ILOAD & ILT2 & IRDRDY & ICNTEN.FB & IEOB.FB & (XLEN.FB ))

"HOLD

# ( ILOAD & ILT2 & RDRDY & !(!LT1 & ILTO) & ICNTEN.FB & IEOB.FB & (XLEN.FB -1)) "COUNT - 1ST READ

# ( ILOAD & ILT2 & CNTEN.FB & IEOB.FB & (XLEN.FB -1)) "COUNT

# ( ILOAD & LT2 & ICNTEN.FB & lEOB.FB & (XLEN.FB )) "HOLD

# ( ILOAD & LT2 & CNTEN.FB & lEOB.FB & (XLEN.FB -1))); "COUNT

EOB.D = !(( TBM_ )

# ( LOAD & T2 & !T1 & ITO ) "LD - 1 WORD XFER # ( !TBM_ & AVCS_ & (XLEN.FB = 0) & ILT2 & (ILTl & ILTO) & !TRDY_ ) # ( !TBM_ & AVCS_ & (XLEN.FB — 1) & ILT2 & (ILTl & LTO) & RDRDY )

# ( !TBM_ & AVCS_ & (XLEN.FB = 1) & ILT2 & ( LTI & ILTO) )

# ( !TBM_ & AVCS_ & (XLEN.FB = 1) & ILT2 & ( LTI & LTO) )

# ( !TBM_ & AVCS_ & (XLEN.FB = 1) & LT2 )

# ( !TBM_ & AVCS_ & (XLEN.FB = 0) )); "HOLD UNTIL TACH. GIVES UP THE BUS

EOB1.D = ( EOB.FB );

EOB2.D = ( EOB.FB & lEOBl.Q );

Claims

1. An apparatus for adapting transmissions between an industry standard data bus of a host computer having a host memory and a fibre channel coupled between said host computer and a peripheral storage subsystem having at least one disk drive, said apparatus comprising: a. an interface logic having a first input/output terminal coupled to said industry standard bus and a second input/output terminal coupled to a local bus of said apparatus; b. a buffer memory having input/output terminals coupled to said local bus; c. a multiplexor/control device having a first set of input/output terminals coupled to said local bus and a second set of input/output terminals disposed for transmitting therethrough address and data; d. a fibre channel controller disposed for formatting header and data structures that meet fibre channel protocol, having a first input/output terminal coupled to said second set of input/output terminals of said multiplexor/control device and a second input/output terminal; e. a gigabit link module disposed for converting said header and data structures from a parallel format to a serial format and having a first input/output terminal coupled to said second input/output terminal of said fibre channel controller and a second input/output terminal coupled to said fibre channel; f. a microprocessor disposed for providing service requests from said host to read and write data from said host memory to and from said peripheral microprocessor having address and data input/output terminals coupled to a processor bus; and, g. a bus control device coupled between said process bus and said local bus for providing service requests of said interface logic, said fibre channel controller and said microprocessor and to arbitrate control of said local bus.

2. An apparatus as in Claim 1 wherein said interface logic includes a first set of registers disposed for receiving requests from said host and a second set of registers disposed for receiving instructions from said microprocessor.

3. An apparatus as in Claim 1 wherein said multiplexor/control includes bi-directional registers and buffers disposed for merging address and data on said local bus before transmission to said fibre channel controller during a write to disk operation, and for separating address and data received from said gigalink module during a read from disk operation.

4. An apparatus as in Claim 1 wherein said fibre channel controller implements a protocol for organizing data frames for transmitting and receiving data.

5. An apparatus as in Claim 1 wherein a non- volatile memory is coupled to said processor bus for providing a permanent storage of a microcode for operation of said microprocessor.

6. An apparatus as in Claim 1 wherein a volatile random-access memory is coupled to said processor bus for providing memory for said microprocessor. subsystem coupled thereto, a method for adapting fibre channel transmissions between said file server and said storage subsystem to an industry standard data bus of said file server, said method comprising the steps of: a. receiving a command control block from said file server, said block containing information as to type of command and information as to location in a memory of said file server of data to be transferred; b. determining type of said command, and if a write command; c. storing said data in a buffer memory; d. moving said data from said buffer memory, through a fibre channel controller and to a gigabit link module; and, e. converting in said gigabit link module said data from a parallel format to a serial format for transmission over a fibre channel.

8. The method as in Claim 10 further including the step of formatting in said fibre channel controller said data into header and data structures that meet fibre channel protocol. 9. The method as in Claim 7 wherein said command is a read command further including the steps of: a. receiving from said storage subsystem via said fibre channel read data; b. converting in said gigabit link module said read data from a serial format to a parallel format for receipt and transmission to said server; c. moving said read data from said gigabit link module through said fibre channel controller to said buffer memory; and, d. transferring said read data from said buffer memory to said memory in said file server. the step of de-formatting said read data from header and data structures into address and data.

11. The method as in Claim 10 further including the step of multiplexing said de-formatted read data onto an address and data bus, resspectively.

12. In a file server having a peripheral storage subsystem coupled thereto, a method for adapting fibre channel transmissions between said file server and said storage subsystem to an industry standard data bus of said file server, said method comprising the steps of: a. receiving a command control block from said file server, said block containing information as to type of command and information as to location in a memory of said file server of data to be transferred; b. determining type of said command, and if a write command; c. storing said data in a buffer memory; d. moving said data from said buffer memory, through a fibre channel controller and to a gigabit link module; e. converting in said gigabit link module said data from a parallel format to a serial format for transmission over a fibre channel; f. if said command is a read command, receiving from said storage subsystem via said fibre channel read data; g. converting in said gigabit link module said read data from a serial format to a parallel format for receipt and transmission to said server; h. moving said read data from said gigabit link module through said fibre channel controller to said buffer memory; and, buffer memory to said memory in said file server.

13. The method as in Claim 12 further including the step of formatting in said fibre channel controller said data into header and data structures that meet fibre channel protocol.

14. The method as in Claim 12 further including the step of de-formatting said read data from header and data structures into address and data.

15. The method as in Claim 12 further including the step of multiplexing said de-formatted read data onto an address and data bus, resspectively.