WO1997023092A1 - Image recording and reproduction apparatus and interface circuit for use in such an apparatus - Google Patents
Image recording and reproduction apparatus and interface circuit for use in such an apparatus Download PDFInfo
- Publication number
- WO1997023092A1 WO1997023092A1 PCT/IB1996/001380 IB9601380W WO9723092A1 WO 1997023092 A1 WO1997023092 A1 WO 1997023092A1 IB 9601380 W IB9601380 W IB 9601380W WO 9723092 A1 WO9723092 A1 WO 9723092A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- mode
- packet
- recording
- buffer
- synchronization
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40052—High-speed IEEE 1394 serial bus
- H04L12/40058—Isochronous transmission
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B27/00—Editing; Indexing; Addressing; Timing or synchronising; Monitoring; Measuring tape travel
- G11B27/002—Programmed access in sequence to a plurality of record carriers or indexed parts, e.g. tracks, thereof, e.g. for editing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B27/00—Editing; Indexing; Addressing; Timing or synchronising; Monitoring; Measuring tape travel
- G11B27/02—Editing, e.g. varying the order of information signals recorded on, or reproduced from, record carriers
- G11B27/031—Electronic editing of digitised analogue information signals, e.g. audio or video signals
- G11B27/032—Electronic editing of digitised analogue information signals, e.g. audio or video signals on tapes
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B27/00—Editing; Indexing; Addressing; Timing or synchronising; Monitoring; Measuring tape travel
- G11B27/10—Indexing; Addressing; Timing or synchronising; Measuring tape travel
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40052—High-speed IEEE 1394 serial bus
- H04L12/40071—Packet processing; Packet format
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40052—High-speed IEEE 1394 serial bus
- H04L12/40117—Interconnection of audio or video/imaging devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B2220/00—Record carriers by type
- G11B2220/90—Tape-like record carriers
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/765—Interface circuits between an apparatus for recording and another apparatus
Definitions
- Image recording and reproduction apparatus and interface circuit for use in such an apparatus.
- the invention relates to a digital image signal recording and reproduction apparatus and a packet communication interface circuit for use in such an apparatus.
- a recording VCR records an image signal by synchronizing to the reproduction timing of a reproducing VCR i.e. to frame timing.
- the reproduction VCR outputs a synchronizing signal which represents a frame timing of the reproduction VCR to the recording VCR for realizing the synchronization.
- the recording VCR recognizes a transmission timing of a frame based on the synchronization signal and records the image signal for every one frame unit.
- a digital image signal is transmitted (a Digital VCR is used) via a digital interface, for example, a bus which corresponds to IEEE 1394 standard.
- the reproducing VCR transmits packets containing image signal data. At least some of the packets contain synchronization information, for example in the form of a clock counter value of the bus clock counter of a IEEE1394 standard bus, the clock counter value being sampled from the bus clock counter at an instant in time which is in a fixed relation to instant the beginning of the frame is read from the reproducing VCR.
- the recording VCR receives the packets from the reproducing VCR and records the image signal data from the packets.
- the recording VCR retrieves the synchronization information from the packets and synchronizes the recording mechanism, such as the scanning head, to this synchronization information.
- the invention provides a digital image signal recording and reproduction apparatus comprising a connection for a digital packet communication bus; a receiving circuit for receiving a packet from the communication bus; a synchronizing buffer for storing synchronization information selected from the packet; a transmission buffer for storing signal data; an internal circuit for switching the recording and reproduction apparatus at least between a first mode and a second mode, the image recording and reproduction apparatus storing received signal data from the packet in the transmission buffer for recording in the first mode, the image recording and reproduction apparatus storing reproduced signal data in the transmission buffer for transmission via the communication bus in the second mode, the image recording and reproduction apparatus synchronizing recording and reproduction timing, in the first and second mode respectively, both according to the synchronization information received from the packet and stored in the synchronization buffer.
- the digital image signal recording and reproduction apparatus can be used both as a recording VCR and as a reproduction VCR synchronized to another VCR for mixing the contents of two video cassettes.
- two reproduction VCRs and one recording VCR are used. Synchronization must be provided between all of the reproducing VCRs mutually and the recording VCR. For example transmission of a synchronization signal from a first reproduction VCR to a second reproduction VCR is provided. Thus, the second reproduction VCR performs reproduction by synchronizing with the first reproduction VCR. In this case, the second reproduction VCR does not perform reproduction under control of its own timing but performs reproduction in an external synchronism reproduction mode in which the second reproducing VCR performs reproduction in synchronism with the first reproduction VCR.
- the digital image signal recording and reproduction apparatus In the first mode the digital image signal recording and reproduction apparatus is able to function as a recording VCR, synchronizing to a reproduction VCR, and recording digital image signal data received from the reproduction VCR.
- the digital image signal recording and reproduction apparatus In the second mode, the digital image signal recording and reproduction apparatus is able to function as a second reproduction VCR, synchronizing to a first reproduction VCR and reproducing image signal data from an inserted video cassette.
- the same transmission buffer is used for signal data.
- both the first reproducing VCR and the second reproducing VCR can synchronize to the recording VCR, when the recording VCR transmits packets providing synchronization information about its recording mechanism, and receives packets with image signal data from the first and second reproducing VCR.
- the digital image signal recording and reproduction apparatus has an embodiment in which the internal circuit is arranged for switching the image signal recording and reproduction apparatus at least between the first mode, the second mode and a third mode, the image signal recording and reproduction apparatus generating reproduction timing autonomously in the third mode, storing reproduced signal data in the transmission buffer in the third mode and transmitting a further packet via the bus comprising the reproduced signal data and synchronization information representing the autonomously generated timing in the third mode.
- the digital image signal recording and reproduction apparatus operates as a reproducing VCR which issues both image signal data and synchronization information.
- this reproducing VCR can be used in combination with a further reproducing VCR.
- the digital image signal recording and reproduction apparatus has an embodiment in which the internal circuit is arranged for switching the image signal recording and reproduction apparatus at least between the first mode, the second mode and a fourth mode, the image signal recording and reproduction apparatus generating recording timing autonomously in the fourth mode, storing received signal data from the packet in the transmission buffer for recording in the fourth mode, and transmitting a further packet via the bus comprising synchronization information which is stored in the transmission buffer and represents the autonomously generated recording timing in the fourth mode.
- the digital image signal recording and reproduction apparatus operates as a recording VCR which issues synchronization information.
- this recording VCR can be used in combination with any number of reproducing VCRs, which can synchronize their reproduction timing to one recording VCR.
- the synchronization buffer may be substantially smaller than the transmission buffer, thus saving memory capacity. Only one transmission buffer needs to be provided used either for reproduction or for recording, independently of whether the apparatus transmits or receives packets containing synchronization information.
- the required interface circuitry can be incorporated in a single integrated circuit.
- FIG. 1 is an arrangement drawing of apparatuses using a shared bus
- Fig. 2 shows the arrangement of a packet
- Fig. 3 is a conceptual drawing of a packet communication apparatus according to the invention.
- Fig. 4 is a block diagram of a conventional full duplex interface circuit
- Figure 1 shows an apparatus arrangement containing a first reproduction VCR 1 , a second reproduction VCR 2, a recording VCR 3 and an editor 4 mutually connected via a bus 5.
- the contents of two video cassettes (VC) are mixed onto one video cassette, using two reproduction VCRs 1 , 2 and one recording VCR 3.
- the VCRs 1, 2, 3 are logically connected to each other by the editor 4.
- the editor 4 is an apparatus for mixing the image signals which are outputted by the reproduction VCRs 1 , 2. Editing choice from the image signal of different VCRs 1 , 2 changes in frame units, therefore frames from different reproduction VCRs 1 , 2 and the recording VCR should start at substantially the same instant in time.
- the second reproduction VCR 2 performs reproduction by synchronizing with the first reproduction VCR 1.
- the second reproduction VCR 2 does not perform reproduction under control of its own timing but performs reproduction in an external synchronism reproduction mode in which the second reproducing VCR 2 performs reproduction in synchronism with the first reproduction VCR 1.
- the recording VCR 3 performs recording in synchronism with the first reproduction VCR 1.
- the bus 5 corresponds for example to the IEEE 1394 standard and connects all of the apparatuses, i.e. VCRs 1 , 2, 3 and the editor 4 to each other by the bus (shared bus).
- a packet which is used on the packet communication bus 5 is the same as, for example a packet 6 in Fig. 2.
- This packet 6 contains sequentially a packet header 7, a header CRC (Cyclic Redundancy Code) 8, a payload 9 and a data CRC 10.
- the bus interface circuit 21 comprises a transmission circuit 22, a receiving circuit 23, a transmission buffer 24, a synchronizing buffer 25 and an external synchronizing controller (ESC) 26.
- the transmission circuit 22 is a general communication interface for realizing an electrical interface between the transmission buffer 24 or the synchronization buffer 25 and the shared bus 5 and for transmitting a packet which is stored in the transmission buffer 24 or the synchronization buffer 25 to the shared bus 5.
- the receiving circuit 23 is a communication interface for electrically interfacing between the transmission buffer 24, and the synchronizing buffer 25 and the shared bus 5 and for storing the CIP header 12 which is included in the packet 6.
- the transmission buffer 24 is a memory (random access memory) which stores the packet 6 from the receiving circuit 23 or from the internal circuit 27.
- the synchronizing buffer 25 is a memory (random access memory) which stores the CIP header
- a data volume of the packet 6 is, for example 492 bytes.
- a memory which has a storing capacity of at least 492 bytes is used.
- the synchronizing controller 26 is, for example a circuit which is activated when an internal circuit receives from the reproduction VCR 1 an instruction starting the external synchronizing operation mode.
- the controller 26 is realized by, for example microprocessor which performs an operation selecting the CIP header 12 from the packet 6.
- the operation selecting the CIP header 12 only from the packet 6 is, for example, realized by selecting the mark and thus the header by arranging a compactor for searching the mark.
- the selection of the CIP header 12 can be realized.
- the internal circuit 27 activates the external synchronizing controller 26. After the activation, under control of the external synchronizing controller 26, the CIP header 12 is selected from the packet 6 of the reproducing VCR 1 which is received via the shared bus 5. The selected CIP header 12 is stored in the synchronizing buffer 25.
- the internal circuit 27 recognizes the synchronizing information from the CIP header 12 in the synchronizing buffer 25, and realizes the reproduction for the packet 6 which is stored in the transmission buffer 24.
- the stored packet 6 will be transmitted to the recording VCR 3 via the shared bus 5.
- the recording VCR 3 operates in the external synchronizing control mode, in the same way as the reproducing VCR 2, a construction as shown in Fig. 3 is arranged on the recording VCR 3.
- the external synchronizing controller 26 stores the CIP header 12 in the synchronizing buffer 25, at the same time, the internal circuit 27 recognizes the synchronizing information from the CIP header 12 which is stored in the synchronizing buffer 25, and records the packet 6 which is stored in the transmission buffer 24 in synchronism with the reproduction VCRs 1 , 2.
- the transmission buffer 24 is used for storing the packet 6 to be transmitted, but in the recording VCR 3, the transmission buffer 24 is used for storing the packet 6 to be recorded.
- the CIP header 12 is selected from the packet 6 and said packet is stored in the synchronizing buffer 25. Furthermore, by said operation, an operation in the external synchronizing operation mode is performed on the basis of synchronizing information which is included in the CIP header 12.
- the receiving full duplex circuit comprises a receiving part 15 which receives the packet 6 which is outputted for example by the reproduction VCR 1 via the shared bus 5 and a transmitting part 16 which transmits the packet 6 to the shared bus 5.
- the receiving part 15 is provided with a receiving circuit 17 which realizes an electrical interface to the shared bus and a receiving buffer 18 which comprises a memory circuit for memorizing a packet 6 which is received by the receiving circuit 17.
- the transmission part 16 is provided with a transmission circuit 19 for realizing the electrical interface to the shared bus 5 and a transmission buffer 20 which comprises a memory circuit for memorizing temporarily the packet to be transmitted.
- the receiving buffer 18 and the transmission buffer 20 are connected to a microprocessor for computing and generating a packet, or to a circuit and a construction for driving the video cassette (not shown).
- a reproducing operation which is synchronized with the reproduction VCR 1 is performed by recognizing the synchronizing signal from the packet 6 of the reproduction VCR 1 which is stored in the receiving buffer 18.
- reproduction in a timing which corresponds to a frame timing of the reproduction VCR 1, reproduction is performed and the packet 6 which contains a reproduced image information is stored in a transmission buffer.
- the packet 6 which is stored in the transmission buffer 20 is transmitted via the shared bus 5 to the editor 4 via the transmission circuit 19.
- the packet communication apparatus comprises a receiving circuit for receiving a packet which has a data and an identification data for using synchronization of a packet transmission, a transmission buffer for storing the packet which is received by the receiving circuit, a synchronization buffer for storing the identification data which is contained in the packet and a synchronizing data selection means for realizing, by selecting the identification data from the packet, a step for storing the selected identification data to the synchronization buffer.
- data in accordance with synchronizing information which is selected from the received packet is stored in a synchronization buffer.
- a capacity of the synchronizing buffer is smaller than a capacity for storing the packet because the buffer needs to store only data according to the synchronizing information. Thus, two buffers which have a capacity for storing a packet, respectively are not needed.
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AT96939261T ATE207273T1 (en) | 1995-12-15 | 1996-12-06 | IMAGE RECORDING AND PLAYBACK APPARATUS AND INTERFACE CIRCUIT FOR USE WITH SUCH APPARATUS |
EP96939261A EP0830782B1 (en) | 1995-12-15 | 1996-12-06 | Image recording and reproduction apparatus and interface circuit for use in such an apparatus |
DE69616046T DE69616046T2 (en) | 1995-12-15 | 1996-12-06 | IMAGE RECORDING AND PLAYBACK AND INTERFACE CIRCUIT FOR USE WITH THIS DEVICE |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7/347701 | 1995-12-15 | ||
JP34770195 | 1995-12-15 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1997023092A1 true WO1997023092A1 (en) | 1997-06-26 |
Family
ID=18392000
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IB1996/001380 WO1997023092A1 (en) | 1995-12-15 | 1996-12-06 | Image recording and reproduction apparatus and interface circuit for use in such an apparatus |
Country Status (6)
Country | Link |
---|---|
US (1) | US6075916A (en) |
EP (1) | EP0830782B1 (en) |
KR (1) | KR100485460B1 (en) |
AT (1) | ATE207273T1 (en) |
DE (1) | DE69616046T2 (en) |
WO (1) | WO1997023092A1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1999017547A1 (en) * | 1997-09-29 | 1999-04-08 | Synctrix, Inc. | System and apparatus for connecting a number of professional video devices using an atm switch |
EP1292139A1 (en) * | 2000-06-09 | 2003-03-12 | Sharp Kabushiki Kaisha | Recorder/player apparatus |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4530048A (en) * | 1982-06-04 | 1985-07-16 | Alpha Microsystems | VCR backup system |
US4636858A (en) * | 1984-10-30 | 1987-01-13 | The United States Of America As Represented By The Secretary Of The Air Force | Extracting digital data from a bus and multiplexing it with a video signal |
US5301026A (en) * | 1991-01-30 | 1994-04-05 | Samsung Electronics Co., Ltd. | Picture editing apparatus in a digital still video camera system |
EP0618560A1 (en) * | 1993-03-29 | 1994-10-05 | Koninklijke Philips Electronics N.V. | Window-based memory architecture for image compilation |
EP0687113A2 (en) * | 1994-05-31 | 1995-12-13 | Matsushita Electric Industrial Co., Ltd. | Data transmission system |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
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AT376302B (en) * | 1980-01-22 | 1984-11-12 | Philips Nv | CYLINDRICAL CAPACITIVE TACHOGENERATOR |
NL8105799A (en) * | 1981-12-23 | 1983-07-18 | Philips Nv | SYSTEM FOR THE TRANSFER OF A TELEVISION IMAGE INFORMATION BY AN ERROR-PROTECTIVE CODE, IMAGER WITH DEVICE FOR GENERATING SUCH A PROTECTIVE CODE, AND THE DISPLAYING COVERING THE COATING OF THE COURTICTION IN THE COURSE OF THE COURTICLE. |
NL8303566A (en) * | 1983-10-17 | 1985-05-17 | Philips Nv | DEVICE FOR FILLING A CASSETTE WITH A LENGTH MAGNETIC TAPE. |
US5544176A (en) * | 1990-02-13 | 1996-08-06 | Canon Kabushiki Kaisha | Information recording apparatus which eliminates unnecessary data before recording |
US5481543A (en) * | 1993-03-16 | 1996-01-02 | Sony Corporation | Rational input buffer arrangements for auxiliary information in video and audio signal processing systems |
US5596564A (en) * | 1993-10-08 | 1997-01-21 | Matsushita Electric Industrial Co., Ltd. | Information recording medium and apparatus and method for recording and reproducing information |
US5511000A (en) * | 1993-11-18 | 1996-04-23 | Kaloi; Dennis M. | Electronic solid-state record/playback device and system |
DE69430293D1 (en) * | 1993-12-16 | 2002-05-08 | Koninkl Philips Electronics Nv | Device for coding and decoding with a memory organized in pages (paged memory) |
-
1996
- 1996-12-06 DE DE69616046T patent/DE69616046T2/en not_active Expired - Fee Related
- 1996-12-06 WO PCT/IB1996/001380 patent/WO1997023092A1/en active IP Right Grant
- 1996-12-06 KR KR1019970705612A patent/KR100485460B1/en not_active IP Right Cessation
- 1996-12-06 AT AT96939261T patent/ATE207273T1/en active
- 1996-12-06 EP EP96939261A patent/EP0830782B1/en not_active Expired - Lifetime
- 1996-12-12 US US08/764,832 patent/US6075916A/en not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4530048A (en) * | 1982-06-04 | 1985-07-16 | Alpha Microsystems | VCR backup system |
US4636858A (en) * | 1984-10-30 | 1987-01-13 | The United States Of America As Represented By The Secretary Of The Air Force | Extracting digital data from a bus and multiplexing it with a video signal |
US5301026A (en) * | 1991-01-30 | 1994-04-05 | Samsung Electronics Co., Ltd. | Picture editing apparatus in a digital still video camera system |
EP0618560A1 (en) * | 1993-03-29 | 1994-10-05 | Koninklijke Philips Electronics N.V. | Window-based memory architecture for image compilation |
EP0687113A2 (en) * | 1994-05-31 | 1995-12-13 | Matsushita Electric Industrial Co., Ltd. | Data transmission system |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1999017547A1 (en) * | 1997-09-29 | 1999-04-08 | Synctrix, Inc. | System and apparatus for connecting a number of professional video devices using an atm switch |
EP1292139A1 (en) * | 2000-06-09 | 2003-03-12 | Sharp Kabushiki Kaisha | Recorder/player apparatus |
EP1292139A4 (en) * | 2000-06-09 | 2004-11-10 | Sharp Kk | Recorder/player apparatus |
US7295768B2 (en) | 2000-06-09 | 2007-11-13 | Sharp Kabushiki Kaisha | Recording and reproducing apparatus |
USRE43897E1 (en) | 2000-06-09 | 2013-01-01 | Sharp Kabushiki Kaisha | Recording and reproducing apparatus |
Also Published As
Publication number | Publication date |
---|---|
DE69616046D1 (en) | 2001-11-22 |
ATE207273T1 (en) | 2001-11-15 |
KR19980702217A (en) | 1998-07-15 |
US6075916A (en) | 2000-06-13 |
EP0830782A1 (en) | 1998-03-25 |
KR100485460B1 (en) | 2006-08-31 |
EP0830782B1 (en) | 2001-10-17 |
DE69616046T2 (en) | 2002-06-20 |
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