WO1997013191A1 - Address transformation in a cluster computer system - Google Patents
Address transformation in a cluster computer system Download PDFInfo
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- WO1997013191A1 WO1997013191A1 PCT/US1996/015937 US9615937W WO9713191A1 WO 1997013191 A1 WO1997013191 A1 WO 1997013191A1 US 9615937 W US9615937 W US 9615937W WO 9713191 A1 WO9713191 A1 WO 9713191A1
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- address field
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- processor
- memory
- bits
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/0284—Multiple user address space allocation, e.g. using different base addresses
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
Definitions
- This invention relates to the art of data processing and, more particularly, to addressing in a cluster computer system employing multiple clusters, each cluster having multiple processors, each processor being incapable of directly addressing all information stored in the total main memory.
- CPUs central processing units
- improvements must take into account the command structure and the word length which often must remain the same as used in the predecessors to a "new" CPU . This is particularly true in the case of systems running under proprietary software operating systems.
- the fundamental reason for this constraint is the often enormous investment in software which a user may have.
- there may be represented three decades of software development in a given user system and a user typically wishes to merely load its old software on a new, improved hardware system and experience immediate higher performance results
- CPU designers go to great lengths to maintain compatibility with earlier CPUs in a given operating system family.
- an exemplary system which includes an external memory space (e.g., main memory) a power of two larger than the internal memory space which is inherently directly addressable by an address field generated/interpreted by the individual processors, by dividing the pr ocessors into multiple clusters with multiple processors in each.
- Each CPU in a cluster of processors four on a single multiprocessor board in the example, is assigned a cluster number which is set, for example, by a two-bit number (thus identifying four clusters).
- each CPU is assigned a two-bit number (thus identifying four CPUs) setting which CPU it is m its cluster.
- the two two-bit numbers are concatenated to provide each CPU with a unique four-bit identification number in the system.
- the cluster number is sent, along with an internal address which includes an indicator bit specifying private/shared classification, from a requesting cluster to an address translator.
- the indicator bit is used to control the set up of the transformation.
- each CPU can inherently directly address one gigabyte (30 bit address field identified as bits 0-29 with bit 0 being the most significant), the available external space is two gigabytes and the length of the external space address field is 32 bits (bits 0-31 , capable of specifying four gigabytes), bit 0 of the internal address is used as the indicator. If bit 0 is a "0", the cluster member is requesting information from its private area of external space; conversely, if it is a " 1 ", the cluster member is addressing information in the shared regions of external space.
- the cluster number is copied into bits 1 , 2 of the external address
- bits 1 , 2 of the internal address are copied into bits 3, 4 of the external address
- the lower order address bits 3-29 of the internal address are copied directly to bits 5-31 of the external address.
- the resulting external address points to the specified private region m external space. If, however, the indicator bit 0 in the internal address is a "1" indicating a call to a shared region of external space, then a different transformation takes place. CN0, CN 1 are ignored. Bit 1 of the internal address is copied to bit 1 of the external address while bits 2, 3 of the external address are each forced to logic "1 ". The resulting external address points to the specified shared region in external space.
- bits 1 , 2 of the external address are copied into positions CN0, CN1 of the internal address
- the external address indicator bits are bits 3, 4. If one or the other or both are "0", then an address from the private space of one of the clusters is indicated. Bit 0 of the internal address is forced to "0", and bits 3, 4 of the external address are copied to bits 1 , of the internal address. The lower order bits 5 - 31 of the external address are copied directly to bits 3 - 29 of the internal address.
- the developed internal address fully identifies an information block in external memory as that of the private space reserved to the cluster identified by CN0, CN 1 .
- bits 3, 4 of the external address are "1 ", then the external space is known to be shared. Bit 0 of the internal address is forced to "1 ", bits 1 , 2 of the external address are copied to bits 1 , 2 of the internal address, and the lower order address bits are copied as before. The resulting internal address identifies an information block in external memory that is available to all the clusters.
- FIG. 1 is a high level block diagram of a cluster computer system in which the present invention may be practiced
- FIG. 2 is a block diagram of the system shown in FIG. 1 illustrating more detail of the individual clusters and CPUs;
- FIG. 3 is an exemplary representation of the allocation of internal address space as allocated to the individual multi-processor clusters and external space representing the address space of a main memory device;
- FIG. 4 is an exemplary transformation diagram illustrating an embodiment of the invention in which each CPU is inherently capable of addressing one gigabyte of information, and a main memory device in communication with all the CPUs is capable of storing two gigabytes of information,
- FIG 5 is a representation of the two types of addresses, internal and external, which are transformed according to the invention.
- FIG 6 is a simplified logic diagram illustrating the apparatus within an address translator component of each CPU operating in an internal-to-external mode
- FIG 7 is a simplified logic diagram of an address translator operating in an external-to-internal mode.
- system bus 5 couples the multiprocessor boards 1 , 2, 3, 4 to one another and to various other system components (including a service processor "SP") represented by the block 6
- system bus 5 couples the multiprocessor boards 1 , 2, 3, 4 to a memory controller 10 which, in turn, interfaces via a memory bus 9 with a main memory 8 representative of one or more main memory devices.
- each multiprocessor board 1 , 2, 3, 4 includes four CPUs 1 1 , 12, 13, 14.
- the four CPUs 1 1 , 12, 13, 14 are provided with respective primary caches 1 1 C, 12C, 13C, 14C.
- the primary caches on each multiprocessor board are each disposed between its directly associated CPU and a common secondary cache 7 and utilize a the classical "store-into-cache" configuration.
- the secondary cache 7 interfaces with the system bus 5.
- address translators 1 1 A, 12A, 13 A, 14A Interposed intermediate each of the primary caches 1 1 C, 12C, 13C, 14C and the common (to the cluster) secondary cache 7 are address translators 1 1 A, 12A, 13 A, 14A which are also constituents of their respective processors 1 1 , 12, 13, 14.
- each of the multiprocessor boards 1 , 2, 3, 4 constitutes a cluster, and each cluster runs under its own operating system to improve system efficiency.
- FIG. 2 illustrates the environment of the subject invention in more detail.
- CPU 1 1 on multiprocessor board 1 (board “0") communicates with the system bus 5 via an address register 15, address translator 18 and secondary cache 7.
- Register 15 is merely a convenient representation of address interface circuitry in the primary cache of the CPU 1 1 by which an address generated by the CPU 1 1 may be transmitted, transformed in the address translator 18, as a request to the secondary cache 7. This condition occurs when information required by the CPU 1 1 is not resident in at least one of the primary caches of the CPUs 1 1 , 12, 13, 14 on the multiprocessor board 1 . (Those skilled in the art will understand that, in many such multiprocessor configurations, it is possible for one CPU to "siphon" information from another CPU's primary cache.)
- CPUs 2 1 , 22, 23, 24 are found on multiprocessor board 2 (board “1 ").
- corresponding CPUs 31 , 32, 33, 34 and 41 , 42, 43, 44 are found on multiprocessor boards 3 (board “2"), 4 (board “3"), respectively.
- registers 25, 35, 45, corresponding to register 15, are respectively found on multiprocessor boards 2, 3, 4.
- address translators 28, 38, 48, corresponding to address translator 18, are respectively found CPUO on each of multiprocessor boards 2, 3, 4.
- first and second two-bit identification registers are shown incorporated in the primary cache of CPU 1 1 on the multiprocessor board 1 .
- the registers 16, 17 are representative of any convenient means for establishing a two-bit cluster identification for the multiprocessor board 1 and a two-bit cluster member identification for the CPU 1 1.
- a cluster/cluster member identification could be hard-wired in or exist as four switches which can be set to a complete cluster member number
- the four stages of the registers 16, 17 are each set to the logic "0" position, thereby providing a cluster identification of "00" (board “0") and a cluster member identification of "00" (CPU "0").
- the registers 16, 17 may be concatenated and may be set upon system initialization under control of the service processor SP as represented by the dashed line 20.
- Corresponding register pairs, 26, 27; 36, 37; and 46, 47 are provided on multiprocessor boards 2, 3, 4, for respective CPU0s 21 , 31 , 41 and are respectively set to provide cluster identifications of "01 “, "10” and “ 1 1 " and, m each case, cluster member identification of "00"
- multiprocessor board 1 (board “0")
- multiprocessor boards 2, 3, 4 operate identically, taking into account their differing cluster number identifications as stored in the registers 26, 36, 46. i .e., the cluster member number for CPU2 33 on multiprocessor board 3 is "1010" (board “2'7CPU "2").
- the 30-bit register 15 in the primary cache of the CPU 1 1 can specify one gigabyte of address locations which is the family limit of the exemplary CPUs. There is value in reserving a portion of the addressable space in main memory 8 to the private use of the CPUs on each multiprocessor board for, among other reasons, permitting each multiprocessor board to operate under an independent operating system. (These independent operating systems may be the same or different operating systems.) On the other hand, there is a need for establishing direct communication among the clusters and CPUs operating under the different operating systems in order that they can function with the full power of a cluster system architecture. One way in which this feature can be achieved is by providing shared memory space in main memory 8.
- the present invention provides for the enjoyment of all these features while also permitting the collective direct and indirect address of more memory spaces in main memory than the CPUs in the system are individually inherently capable.
- internal space means the memory addressable by the CPUs on each multiprocessor board while the term “external space” means the total memory addressable, I e , the memory space available in main memory 8
- each CPU has a 30-bit address field and can therefore directly address one gigabyte
- the available external space in the exemplary main memory is two gigabytes and that the external address field is 32-b ⁇ ts long, i.e., capable of addressing four gigabytes .
- a key aspect of the present invention is the manner m which addressable memory for each multiprocessor board is allocated For the external memory space to be accessible, as a result of address transformation, by each multiprocessor board 1 , 2, 3, 4, three-eighths of the inherently addressable internal space is private and one-half is shared Comment on the apparently remaining one-eighth is reserved for discussion below. Under these conditions, the memory allocation may be appreciated from an examination of FIG. 3.
- Multiprocessor board 1 enjoys 3/8th gigabyte private memory space identified as 1/8th gigabyte segments P1 1 , P12, P13.
- Multiprocessor board 1 has access to 1/2 gigabyte shared memory space in 1 /8th gigabyte segments SA, SB, SC, SD.
- Multiprocessor board 2 enjoys 3/8th gigabyte private memory space identified as 1 /8th gigabyte segments P21 , P22, P23.
- Multiprocessor board 2 has access to 1/2 gigabyte shared memory space in 1/8th gigabyte segments SA, SB, SC, SD.
- the internal space for multiprocessor boards 3 and 4 are correspondingly assigned as shown in FIG. 3.
- This internal space address information is provided to the address translation block which, as previously described, is present in the primary cache of each CPU, but is shown separately as a single block in FIG. 3 for clarity.
- this address information is transformable, according to the invention, to obtain external space address segments distributed as shown schematically in FIG. 3.
- FIG .4 shows the higher order address bit distribution for the four multiprocessor boards for both the internal and external space addresses as they are transformed by the address translation block (e.g., the address translator 18 in FIG. 2).
- the address translation block e.g., the address translator 18 in FIG. 2.
- the most significant bit of the 32-bit transformed address is always a "0" in the example.
- the cluster number is preset to "00", the private space three most significant bits are “000”, “001 “ and “010” and the shared space three most significant bits are " 100", “ 101 “, “ 1 10” and “1 1 1 ". It will be noted that, in this example, the combination "01 1 " for the three most significant bits is reserved.
- the three highest order internal address bits may be deemed the higher order segment of the processor address field and the remaining bits 3-29 may be deemed the lower order segment thereof.
- the corresponding addresses transformed into the five most significant bits of the private external space addresses to be transformed (i.e., bits 1 , 2, 3, 4), are, respectively, “00000", “00001 “, “00010” (or P1 1 , P12, P13) and those for the shared external space addresses are, respectively, “0001 1 ", "00011” , “0101 1 " and "01 1 1 1 " (or SA, SB, SC, SD).
- the five highest order internal address bits may be deemed the higher order segment of the memory address field and the remaining bits 5-31 may be deemed the lower order segment thereof.
- the cluster number is preset to "01"
- the private space three most significant bits are, again, “000”, “001” and “010”
- the shared space three most significant bits are, again, “100”, “101 “, “1 10” and “ 1 1 1 ".
- the internal addresses of multiprocessor board 3 and 4 are respectively transformed to external addresses "01000” (P31), "01001” (P32), “01010” (P33) "00011” (SA), “0001 1” (SB), “01011” (SC), "01111” (SD) and ''01100"(P41), "01101” (P42), “01110” (P43) "00011” (SA), “00011” (SB), “0101 1 " (SC), "01111” (SD).
- bit 1 of the internal address known to be a "1"
- Bits 1 and 2 of the internal address are used as bits 1 and 2 of the external address.
- bits 3 and 4 of the external address are set to "1 1”.
- FIGs. 6 and 7 Exemplary transfomiation apparatus for the address translator 18 of CPUO 1 1 is shown in FIGs. 6 and 7.
- FIG 6 illustrates this apparatus operating in the internal-to-external transformation mode in which an internal address, including a cluster number, is sent to the address translator 18 as a request from the primaiy cache directed to the secondary cache 7 (which, of course, will forward the request to main memory if the requested information is not resident in the secondary cache at the time of the request).
- the internal address is thus present in register 15 to serve as an input to die address translator in conjunction with the cluster number m register 16.
- bit 0 of the internal address is key. If it is a "0", the address is identified as private to the requesting multiprocessor board which itself is identified by CN0, CN 1 in register 16.
- Bit 0 is inverted to a "1 " by inverter 55, and the output of inverter 55 therefore enables one input each of AND-gates 61 , 63, 65, 67
- the other input to AND-gate 61 is CN0 which is therefore copied through OR-gate 56 into bit 1 of the external address in exemplary address translator output register 54.
- the other input to AND-gate 63 is CN1 which is therefore copied through OR-gate 67 into bit 2 of the external address.
- the other input to AND-gate 65 is bit 1 of the internal address which is therefore copied, via OR-gate 58, to bit 3 of the external address in register 54.
- bit 2 of the internal address which is therefore copied, via OR-gate 59, to bit 4 of the external address in register 54.
- the lower order address bits 3 - 29 of the internal address in register 18 are directly copied to bits 5 - 31 of the external address in register 54.
- Bit 0 of the external address in register 54 is forced to logic "0" because external space is limited, in the example, to two gigabytes. As previously mentioned, this bit is available to accommodate two separate systems having access to the main memory.
- the address being transformed has been supplied by the primary cache of CPU0 1 1 , i e., CN0, CN 1 are set to "00" and that bits 0,1 ,2 of the internal address are "010"
- the external space addressed after the transformation by the higher order address bits "00010" will be the 1 /8 gigabyte private block identified m FIG 3 as P13
- bit 0 of an internal address sent to the address translator 18 is a logic "1 " indicating a call to shared space. Since bit 0, m this instance, will be inverted to a logic "0" by the inverter 55, the AND-gates 61 , 63, 65, 67 will be disabled Instead, AND-gates 60, 62, 64, 66 will each have one input enabled as a result of the logic "1 " present in bit 0 of register 53
- the other input to AND-gate 60 comes from bit 1 of register 53 such that the logic level of bit 1 in the internal address is copied, via OR-gate 56, into bit 1 of the external address m register 54
- the other input to AND-gate 62 comes from bit 2 of register 53 such that the logic level of bit 2 in the internal address is copied, via OR-gate 57, into bit 2 of the external address in register 54.
- each of the AND-gates 64, 66 are directly tied to logic "1 " such that bits 3 and 4 of the external address in register 54 are set to "1 " via OR-gates 58, 59, respectively Again, bit 0 of the external address in register 54 is forced to "0" because of the two gigabyte limitation on external space m the example.
- Lower order address bits 3 - 29 of the internal address are directly copied into bits 5 - 31 of the external address as before.
- bits 0, 1 ,2 of the internal address supplied by the multiprocessor board 1 are " 1 1 1 "
- the external space addressed after the transformation by the higher order address bits "011 1 1" will be the 1/8 gigabyte shared block identified in FIG. 3 as SD.
- the CPU on a given multiprocessor board making a request to the secondary cache 7 is conventionally tracked by the secondary cache.
- the contents of the register 17 containing the cluster member number is sent to the secondary cache for that purpose.
- FIG. 7 illustrates the address translator 18 operating in the external-to-internal address transformation mode
- An external address from the secondary cache is placed in register 68, representative of any appropriate logic for the purpose.
- Bit 0 of the external address is not used because of the two gigabyte capacity of the main memory.
- Bits 1 and 2 are applied to corresponding inputs to multiplexer pair 84, 85 which selectively drive inputs to register 86 which is representative of any appropriate logic for interfacing the primary cache with the address translator.
- bits 1 and 2 in the register 68 are applied as respective inputs to comparators 81 , 82 which have CN0 and CN1 in register 16 as their respective second inputs.
- First respective inputs to the comparators 87, 88 are CMO, CM1 from register 17 while the second respective inputs thereto are the cluster member number received from the secondary cache which has conventionally previously recorded that CPU0 in the local cluster made the original request for access to the memory block identified by the external address.
- AND-gate 83 is fully enabled to enable the multiplexer 84 to transfer the transformed external-to-internal address to register 86. Since private space is indicated in the example, one or the other of bits 3 and 4 in register 68 are "0", and AND-gate 70 is disabled such that its output is "0" and the output of inverter 71 is "1 ".
- bits 5-31 in register 68 are transferred through multiplexer 84 to bits 3-29 m register 86 to complete the external-to-internal transformation of the address information and the selection of the correct CPU in the correct cluster to receive requested information in the private storage area of the mass memory.
- a "1 " is copied into bit 0 of register 86, via OR-gate 78 and multiplexer 85, to provide the internal address indicator for shared space.
- the other inputs to AND-gates 75, 76 are, respectively, from bits 1 , 2 in register 68.
- the contents of bits 1 , 2 in register 68 are copied into bits 1 , 2 of register 86 via OR-gates 79, 80, respectively, and multiplexer 85.
- Bits 5-31 of the external address in register 68 are copied through multiplexer 85 into bits 3-29 of the internal address in register 86 as the lower order address bits common to the internal and external addresses.
- each multiprocessor board loses the capacity to address 1/8 gigabyte of the one gigabyte inherently addressable by a 30 bit address field.
- the ability to directly communicate among all the multiprocessor boards via the shared space is achieved.
- any multiprocessor board to indirectly address the private space of another multiprocessor board by sending a suitable request via shared space which results in the desired information being moved from private space into shared space
- the previously discussed advantage of permitting each multiprocessor board to operate under its own operating system is achieved. Still further, the capability to enjoy the benefits of running separate operating systems in each cluster is facilitated and enhanced.
- FIGs 3 - 7, inclusive is only one of many address transformations which may be established according to the present invention.
- each multiprocessor board can, as before, inherently directly address one gigabyte while the main memory can store four gigabytes. Then, bit 0 of the external address would come into play, and the logic of FIGs . 6 and 7 would be accordingly adjusted and expanded
- the cluster number for each multiprocessor board may be extended to three bits with the most significant cluster number bit copied to and from bit 0 of the external address. This arrangement will expand the number of four-multiprocessor clusters which can be accommodated as well as expand the directly and indirectly addressable external memory. Alternatively, the clusters can be reduced to two multiprocessors per cluster (i.
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Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
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CA002211083A CA2211083C (en) | 1995-10-06 | 1996-10-04 | Address transformation in a cluster computer system |
EP96934045A EP0855057B1 (en) | 1995-10-06 | 1996-10-04 | Address transformation in a cluster computer system |
DE69635865T DE69635865T2 (en) | 1995-10-06 | 1996-10-04 | ADDRESS TRANSFORMATION IN A CLUSTER COMPUTER SYSTEM |
JP9514461A JPH11512857A (en) | 1995-10-06 | 1996-10-04 | Address translation in a cluster computer system |
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US08/540,106 US5590301A (en) | 1995-10-06 | 1995-10-06 | Address transformation in a cluster computer system |
US08/540,106 | 1995-10-06 |
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PCT/US1996/015937 WO1997013191A1 (en) | 1995-10-06 | 1996-10-04 | Address transformation in a cluster computer system |
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US (1) | US5590301A (en) |
EP (1) | EP0855057B1 (en) |
JP (1) | JPH11512857A (en) |
CA (1) | CA2211083C (en) |
DE (1) | DE69635865T2 (en) |
WO (1) | WO1997013191A1 (en) |
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JPH04246745A (en) * | 1991-02-01 | 1992-09-02 | Canon Inc | Memory access system |
WO1995025306A2 (en) * | 1994-03-14 | 1995-09-21 | Stanford University | Distributed shared-cache for multi-processors |
-
1995
- 1995-10-06 US US08/540,106 patent/US5590301A/en not_active Expired - Lifetime
-
1996
- 1996-10-04 DE DE69635865T patent/DE69635865T2/en not_active Expired - Lifetime
- 1996-10-04 CA CA002211083A patent/CA2211083C/en not_active Expired - Fee Related
- 1996-10-04 JP JP9514461A patent/JPH11512857A/en active Pending
- 1996-10-04 EP EP96934045A patent/EP0855057B1/en not_active Expired - Lifetime
- 1996-10-04 WO PCT/US1996/015937 patent/WO1997013191A1/en active IP Right Grant
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5197130A (en) * | 1989-12-29 | 1993-03-23 | Supercomputer Systems Limited Partnership | Cluster architecture for a highly parallel scalar/vector multiprocessor system |
US5265235A (en) * | 1990-11-30 | 1993-11-23 | Xerox Corporation | Consistency protocols for shared memory multiprocessors |
US5394555A (en) * | 1992-12-23 | 1995-02-28 | Bull Hn Information Systems Inc. | Multi-node cluster computer system incorporating an external coherency unit at each node to insure integrity of information stored in a shared, distributed memory |
Non-Patent Citations (1)
Title |
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See also references of EP0855057A4 * |
Also Published As
Publication number | Publication date |
---|---|
EP0855057A1 (en) | 1998-07-29 |
EP0855057A4 (en) | 1999-12-08 |
DE69635865T2 (en) | 2006-09-14 |
DE69635865D1 (en) | 2006-04-27 |
CA2211083A1 (en) | 1997-04-10 |
EP0855057B1 (en) | 2006-03-01 |
JPH11512857A (en) | 1999-11-02 |
US5590301A (en) | 1996-12-31 |
CA2211083C (en) | 2003-05-20 |
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