WO1997006558A1 - Process for rounding corners in trench isolation - Google Patents

Process for rounding corners in trench isolation Download PDF

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Publication number
WO1997006558A1
WO1997006558A1 PCT/US1996/012852 US9612852W WO9706558A1 WO 1997006558 A1 WO1997006558 A1 WO 1997006558A1 US 9612852 W US9612852 W US 9612852W WO 9706558 A1 WO9706558 A1 WO 9706558A1
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WO
WIPO (PCT)
Prior art keywords
forming
substrate
spacer structure
trench
etching
Prior art date
Application number
PCT/US1996/012852
Other languages
French (fr)
Inventor
Larry Yu Wang
Farrokh Omid-Zohoor
Original Assignee
Advanced Micro Devices, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices, Inc. filed Critical Advanced Micro Devices, Inc.
Publication of WO1997006558A1 publication Critical patent/WO1997006558A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3085—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment

Definitions

  • This invention is related to semiconductor fabrication processes and, particularly to trench isolation semiconductor fabrication processes.
  • FIG. 1 shows a cross-sectional view of a stage in a process to form a trench 100.
  • Trench 100 is used in a typical trench isolation technology to isolate field effect transistors (FETs) .
  • Trench 100 is formed in a Si substrate 102 with a substantially planar surface.
  • Nitride layers 104 define the active region of a FET being formed using this trench isolation technology.
  • Trench 100 and the substantially planar surface of substrate 102 form Si corners 106.
  • each corner 106 concentrates the electric field in an active transistor, thereby reducing the threshold voltage of the region proximate tc corners 106.
  • the reduced threshold voltage may cause undesirable leakage current along the field.
  • the enhanced field around corners 106 can cause the gate oxide
  • trench isolation technologies typically round off corners 106 to reduce the electric field concentration.
  • Conventional corner rounding processes typically are done after the trench is formed, thereby adding a process step which decreases throughput in the manufacturing process.
  • corners 106 get oxidized faster than the planar surface of substrate 102 and sidewalls 108 of trench 100,
  • the oxide may grow under nitride layer 104 (i.e., the so-called bird's beak), thereby reducing the active area under nitride layer 104.
  • the high temperature needed in this process to round off corners may warp the wafer. Large wafer sizes are especially susceptible to this warping problem.
  • a method for rounding corners in a trench is provided.
  • the method is applied to round corners of a trench formed in a substrate, where the trench is used to isolate integrated circuit devices built into and on the substrate.
  • an oxide layer is formed on the substrate, upon which a hard mask layer is formed.
  • the hard mask layer and the oxide layer is patterned by photolithography and then etched to form hard masks defining active regions.
  • a conformal layer is formed above the etched hard masks and the oxide layer.
  • the conformal layer is then etched to the substrate, thereby forming a rounded spacer structure around each hard mask.
  • the trench is etched in the substrate between hard masks using an etch method that etches the substrate selective to the hard masks and relatively non-selective to spacer structures.
  • the rounded shape of the spacer structure is transferred to the substrate, thereby forming rounded corners in the trench without using high temperatures that can warp the wafer containing the substrate.
  • this process offers a great degree of freedom in modifying the shape of the trench corners by varying etch chemistry and etch endpoint.
  • FIG. 1 shows a trench formed u ⁇ ing a conventional trench isolation technology.
  • FIGs. 2-8 show cross-sectional diagrams illustrating a process for forming rounded corners in a trench according to one embodiment of the present invention.
  • FIG. 2 shows a cross-sectional side view of structures formed in an early stage in forming a trench with rounded corners in accordance with one embodiment of the present invention.
  • An oxide layer 200 is formed over a Si substrate 202 in a conventional manner.
  • oxide layer 200 is grown by thermal oxidation to approximately l5 ⁇ A.
  • a hard mask layer is then formed over oxide layer
  • the hard mask layer is a silicon nitride layer formed in a conventional manner by low pressure (“LP”) chemical vapor deposition ( "CVD") to a thickness of approximately 2000A.
  • LP low pressure
  • CVD chemical vapor deposition
  • the thickness of the nitride layer must be thick enough to survive subsequent etching and polishing steps.
  • the nitride layers in the range 1500-2500A can be used.
  • the nitride layer is patterned by conventional photolithography processes and then etched down to oxide layer 200.
  • the nitride layer is etched in a conventional manner using a conventional dry etch. Consequently, this etching step forms photoresist segments 204 and nitride hard masks 206, resulting in photoresist/nitride/oxide stacks 208 being 5 formed on Si substrate 202.
  • FIG. 3 shows a cross-sectional side view of structures formed in a next stage in forming a rounded corner trench according to this embodiment of the present invention.
  • the photoresist segments are
  • stacks 208 are now nitride/oxide stacks.
  • the . photoresist is stripped using a conventional plasma strip followed by wet clean in sulfuric/-f ⁇ 0 2 solution. Then a conformal layer 300 is formed over stacks 208.
  • conformal layer is an oxide layer formed in a conventional manner by CVD to a thickness of approximately lOOOA, although any thickness in the range of 900-1200A can be used.
  • conformal layer 300 can be made of any material that the trench
  • etch step (described below in conjunction with FIG. 5) is less selective relative to hard masks 206.
  • conformal layer 300 can be poly or amorphous silicon.
  • FIG. 4 shows a cross-sectional side view
  • Conformal layer 300 is anisotropically etched down to substrate 202 and hard masks 206 to form spacer structures 400 surrounding
  • conformal layer 300 is etched using a conventional CHF 3 -based plasma etch process. This process results in spacer structures 400 having rounded portions 402.
  • FIG. 5 shows a cross-sectional side view
  • a trench 500 is etched into substrate 202 to approximately 2000A, leaving hard masks 206 and spacer structures 400 substantially intact.
  • trench 500 is etched using a reactive ion etching process.
  • FIG. 6 shows a cross-sectional side view of structures formed in a next stage in forming a rounded corner trench according to this embodiment of the present invention.
  • the rounded shape of spacer structures 400 is transferred to substrate 202 using an anisotropic etch that is relatively non-selective for both the substrate and the spacer structure material, but still relatively selective to the hard mask material.
  • a conventional anisotropic oxide/Si etch transfers the rounded shape of spacer structures 400 to the substrate 202.
  • This corner etch is stopped when most of spacer structures 400 are etched away, thereby forming a nitride/oxide stack 602.
  • this corner etch step forms rounded corners 604.
  • this corner etch step also increases the depth of trench 500.
  • a trench formed according to this embodiment of the present invention has rounded corners 604 without using high temperature oxidation as in some conventional processes.
  • rounded corners 604 are formed below spacer structures 400 and not below hard masks 206, the lithographic requirements for forming hard masks 206 can be relaxed.
  • photoresist segments 204 when forming a 0.25 micron wide trench using conventional processes, photoresist segments 204 must be formed 0.25 microns apart. A deep UV stepper must be used to pattern the photoresist at 0.25 micron spacing.
  • forming a 0.25 micron trench according to this embodiment of the present invention allows hard masks 206 to be separated by 0.25 microns plus twice the width "x" of spacer structures 400 (FIG. 5) .
  • photoresist segments 204 can be separated by as much as 0.3-0.4 microns, thereby allowing the use of a much less costly I-line stepper.
  • the spacer structure/substrate etch selectivity is one-to-one, which causes the rounded shape of the spacer structure to be substantially identically transferred to the corner. If the etch is more selective to the spacer structure than the substrate, then the spacer structure will be etched away more slowly than the substrate. Thus, as shown in FIG. 7, the corner will have a "flatter" cross-sectional curve than the cross section curve of rounded portions 402 (FIG. 4) , as shown respectively by curves 700 and 702.
  • FIG. 8 shows a cross-sectional side view of structures formed in a next stage in forming a rounded corner trench according to this embodiment of the present invention.
  • a liner oxide 800 is formed in trench 500.
  • liner oxide 800 is in a conventional thermal oxidation process to a thickness of approximately 50 ⁇ A. The remaining steps in forming the trench isolation structure can be performed using any conventional trench isolation process.
  • conformal layer 300 is formed by depositing polysilicon by CVD to a thickness of approximately lOOOA.
  • forming spacer structures 400 (FIG. 4) , trench 500 (FIG. 5) and rounded corners 604 (FIG. 6) can be accomplished using a single etching operation without changing the etch chemistry.
  • fabrication throughput is greatly improved compared to the conventional processes that use separate etching operations to form the trench and to round the trench corners.
  • substrate 202 is Si
  • the spacer structure/substrate etch selectivity will be approximately 1:1, thereby resulting in rounded portions 402 (FIG. 4) being substantially identically transferred to corners 604 (FIG. 6) .
  • trench 500 (FIG. 6) will be approximately equal to the maximum thickness of spacer structures 400 (FIG. 4) .
  • conformal layer 300 (FIG. 3) from amorphous Si instead of polysilicon will result in a trench having similar characteristics.

Abstract

A method for rounding corners in a trench is provided. In one embodiment, the method is applied to round the corners of a trench formed in a substrate. A hard mask layer is formed on the substrate. The hard mask layer is patterned by photolithography and then etched to form hard masks. Then a conformal layer is formed above the hard masks and substrate. The conformal layer is then etched to the substrate, thereby forming a rounded spacer structure around each hard mask. Then the trench is etched in the substrate between hard masks using an etch method that etches the substrate selective to the hard masks and relatively non-selective to spacer structures. As a result, the rounded shaped of the spacer structure is transferred to the substrate.

Description

PROCESS FOR ROUNDING CORNERS IN TRENCH ISOLATION
FIELD OF THE INVENTION This invention is related to semiconductor fabrication processes and, particularly to trench isolation semiconductor fabrication processes.
BACKGROUND OF THE INVENTION FIG. 1 shows a cross-sectional view of a stage in a process to form a trench 100. Trench 100 is used in a typical trench isolation technology to isolate field effect transistors (FETs) . Trench 100 is formed in a Si substrate 102 with a substantially planar surface. Nitride layers 104 define the active region of a FET being formed using this trench isolation technology. Trench 100 and the substantially planar surface of substrate 102 form Si corners 106.
One problem in trench isolation technologies is that each corner 106 concentrates the electric field in an active transistor, thereby reducing the threshold voltage of the region proximate tc corners 106. The reduced threshold voltage may cause undesirable leakage current along the field. In addition, the enhanced field around corners 106 can cause the gate oxide
(formed in later steps) to breakdown, thereby creating reliability problems.
As a result, trench isolation technologies typically round off corners 106 to reduce the electric field concentration. Conventional corner rounding processes typically are done after the trench is formed, thereby adding a process step which decreases throughput in the manufacturing process.
Further, in one conventional technique to round off corners 106, high temperature oxidation is used to round corners 106. This technique is disclosed in "Nonplanar Oxidation and Reduction of Oxide Leakage Currents at Silicon Corners by Rounding-Off Oxidation" by Yamabe and I ai, IEEE Transactions on Electron Devices, Vol. ED-34, No. 8, August 1987, pp. 1681-1687, which is herein incorporated by reference in its entirety. In high temperature oxidation, corners 106 get oxidized faster than the planar surface of substrate 102 and sidewalls 108 of trench 100, However, in this technique, the oxide may grow under nitride layer 104 (i.e., the so-called bird's beak), thereby reducing the active area under nitride layer 104. Further, the high temperature needed in this process to round off corners may warp the wafer. Large wafer sizes are especially susceptible to this warping problem.
SUMMARY
In accordance with the present invention, a method for rounding corners in a trench is provided. In one embodiment, the method is applied to round corners of a trench formed in a substrate, where the trench is used to isolate integrated circuit devices built into and on the substrate. In this embodiment, an oxide layer is formed on the substrate, upon which a hard mask layer is formed. The hard mask layer and the oxide layer is patterned by photolithography and then etched to form hard masks defining active regions. Then a conformal layer is formed above the etched hard masks and the oxide layer. The conformal layer is then etched to the substrate, thereby forming a rounded spacer structure around each hard mask. Then the trench is etched in the substrate between hard masks using an etch method that etches the substrate selective to the hard masks and relatively non-selective to spacer structures. As a result, the rounded shape of the spacer structure is transferred to the substrate, thereby forming rounded corners in the trench without using high temperatures that can warp the wafer containing the substrate. Further, this process offers a great degree of freedom in modifying the shape of the trench corners by varying etch chemistry and etch endpoint.
BRIEF DFSrPIPTION OF THE DRAWTTSTπ.q
FIG. 1 shows a trench formed uεing a conventional trench isolation technology.
FIGs. 2-8 show cross-sectional diagrams illustrating a process for forming rounded corners in a trench according to one embodiment of the present invention.
DETAILED DESCRIPTION
FIG. 2 shows a cross-sectional side view of structures formed in an early stage in forming a trench with rounded corners in accordance with one embodiment of the present invention. An oxide layer 200 is formed over a Si substrate 202 in a conventional manner. In this embodiment, oxide layer 200 is grown by thermal oxidation to approximately l5θA.
A hard mask layer is then formed over oxide layer
200. in this embodiment, the hard mask layer is a silicon nitride layer formed in a conventional manner by low pressure ("LP") chemical vapor deposition ("CVD") to a thickness of approximately 2000A. The thickness of the nitride layer must be thick enough to survive subsequent etching and polishing steps. Thus, the nitride layers in the range 1500-2500A can be used.
Of course, if other material is used to form the hard mask layer, then different thicknesses are appropriate for the alternative material.
The nitride layer is patterned by conventional photolithography processes and then etched down to oxide layer 200. In this embodiment, the nitride layer is etched in a conventional manner using a conventional dry etch. Consequently, this etching step forms photoresist segments 204 and nitride hard masks 206, resulting in photoresist/nitride/oxide stacks 208 being 5 formed on Si substrate 202.
FIG. 3 shows a cross-sectional side view of structures formed in a next stage in forming a rounded corner trench according to this embodiment of the present invention. The photoresist segments are
10. removed from stacks 208. Consequently, stacks 208 are now nitride/oxide stacks. In this embodiment, the . photoresist is stripped using a conventional plasma strip followed by wet clean in sulfuric/-f^02 solution. Then a conformal layer 300 is formed over stacks 208.
15 In this embodiment, conformal layer is an oxide layer formed in a conventional manner by CVD to a thickness of approximately lOOOA, although any thickness in the range of 900-1200A can be used. Of course, conformal layer 300 can be made of any material that the trench
20 etch step (described below in conjunction with FIG. 5) is less selective relative to hard masks 206. For example, conformal layer 300 can be poly or amorphous silicon.
FIG. 4 shows a cross-sectional side view of
25 structures formed in a next stage in forming a rounded corner trench according to this embodiment of the present invention. Conformal layer 300 is anisotropically etched down to substrate 202 and hard masks 206 to form spacer structures 400 surrounding
30 hard masks 206. In this embodiment, conformal layer 300 is etched using a conventional CHF3-based plasma etch process. This process results in spacer structures 400 having rounded portions 402.
FIG. 5 shows a cross-sectional side view of
35 structures formed in a next stage in forming a rounded corner trench according to this embodiment of the present invention. A trench 500 is etched into substrate 202 to approximately 2000A, leaving hard masks 206 and spacer structures 400 substantially intact. In this embodiment, trench 500 is etched using a reactive ion etching process.
FIG. 6 shows a cross-sectional side view of structures formed in a next stage in forming a rounded corner trench according to this embodiment of the present invention. The rounded shape of spacer structures 400 is transferred to substrate 202 using an anisotropic etch that is relatively non-selective for both the substrate and the spacer structure material, but still relatively selective to the hard mask material. In this embodiment, a conventional anisotropic oxide/Si etch transfers the rounded shape of spacer structures 400 to the substrate 202. This corner etch is stopped when most of spacer structures 400 are etched away, thereby forming a nitride/oxide stack 602. Thus, this corner etch step forms rounded corners 604. In addition, this corner etch step also increases the depth of trench 500.
It is important not to overetch. As shown in FIG. 6b, overetching creates sharp corners 610 where stack 602 contacts substrate 202. Thus, a trench formed according to this embodiment of the present invention has rounded corners 604 without using high temperature oxidation as in some conventional processes.
Further, because rounded corners 604 are formed below spacer structures 400 and not below hard masks 206, the lithographic requirements for forming hard masks 206 can be relaxed. For example, when forming a 0.25 micron wide trench using conventional processes, photoresist segments 204 must be formed 0.25 microns apart. A deep UV stepper must be used to pattern the photoresist at 0.25 micron spacing. In contrast, forming a 0.25 micron trench according to this embodiment of the present invention allows hard masks 206 to be separated by 0.25 microns plus twice the width "x" of spacer structures 400 (FIG. 5) . Thus, photoresist segments 204 can be separated by as much as 0.3-0.4 microns, thereby allowing the use of a much less costly I-line stepper.
In one embodiment, the spacer structure/substrate etch selectivity is one-to-one, which causes the rounded shape of the spacer structure to be substantially identically transferred to the corner. If the etch is more selective to the spacer structure than the substrate, then the spacer structure will be etched away more slowly than the substrate. Thus, as shown in FIG. 7, the corner will have a "flatter" cross-sectional curve than the cross section curve of rounded portions 402 (FIG. 4) , as shown respectively by curves 700 and 702.
In contrast, if the etch is less selective to the spacer structure than the substrate, then the spacer structure will be etched away more quickly than the substrate, thereby causing the corner to have a "steeper" cross-sectional curve than rounded portions 402, as indicated by curve 704. FIG. 8 shows a cross-sectional side view of structures formed in a next stage in forming a rounded corner trench according to this embodiment of the present invention. A liner oxide 800 is formed in trench 500. In this embodiment, liner oxide 800 is in a conventional thermal oxidation process to a thickness of approximately 50θA. The remaining steps in forming the trench isolation structure can be performed using any conventional trench isolation process.
In another embodiment of the present invention, conformal layer 300 (FIG. 3) is formed by depositing polysilicon by CVD to a thickness of approximately lOOOA. In this embodiment, forming spacer structures 400 (FIG. 4) , trench 500 (FIG. 5) and rounded corners 604 (FIG. 6) can be accomplished using a single etching operation without changing the etch chemistry. As a result, fabrication throughput is greatly improved compared to the conventional processes that use separate etching operations to form the trench and to round the trench corners. Further, when substrate 202 is Si, the spacer structure/substrate etch selectivity will be approximately 1:1, thereby resulting in rounded portions 402 (FIG. 4) being substantially identically transferred to corners 604 (FIG. 6) . However, the depth of trench 500 (FIG. 6) will be approximately equal to the maximum thickness of spacer structures 400 (FIG. 4) . Of course, forming conformal layer 300 (FIG. 3) from amorphous Si instead of polysilicon will result in a trench having similar characteristics.
The foregoing has described the principles and preferred embodiments of the present invention. However, the invention should not be construed as being limited to the particular embodiments described. For example, different material may be used to form the hard masks, the spacer structures and substrate. Further, different methods may be used to form and etch the various layers. Thus, the above-described embodiments should be regarded as illustrative rather than restrictive. Variations can be made to those embodiments by workers skilled in the art without departing from the scope of the present invention as defined by the following claims.

Claims

CLAIMS We claim:
1. A method comprising: forming a hard mask on a substrate; forming a spacer structure on said substrate and surrounding said hard mask, said spacer structure having a portion with a rounded shape,- forming a trench in said substrate proximate to said spacer structure; and etching said spacer structure and said substrate to form a trench corner with a rounded shape, said rounded shape of said trench corner being dependent on said rounded shape of said portion of said spacer structure.
2. The method of claim 1 wherein forming said hard mask comprises: forming a layer of nitride on said substrate; and etching said layer of nitride.
3. The method of claim 2 wherein forming said nitride layer comprises forming said nitride layer by chemical vapor deposition.
4. The method of claim 1 wherein forming said spacer structure comprises: forming a conformal layer over said hard mask; and anisotropically etching said conformal layer.
5. The method of claim 4 wherein forming said conformal layer comprises forming a conformal layer of oxide by chemical vapor deposition.
6. The method of claim 4 wherein forming said conformal layer comprises forming a conformal layer of polysilicon.
7. The method of claim 1 wherein forming said trench in said substrate comprises forming said trench while leaving said spacer structure and said hard mask substantially intact.
8. The method of claim 7 wherein forming said trench further comprises anisotropically etching said trench.
9. The method of claim 1 wherein etching said spacer structure and said substrate comprises etching said spacer structure and said substrate while leaving said hard mask substantially intact.
10. The method of claim 9 wherein etching said spacer structure and said substrate comprises etching said spacer structure and said substrate with a spacer structure-to-substrate etch selectivity of approximately one-to-one.
11. The method of claim 1 further comprising forming an oxide layer between said hard mask and said substrate.
12. The method of claim 11 wherein forming said oxide layer comprises forming said oxide layer by thermal oxidation of said substrate before forming said hard mask.
13. The method of claim 1 wherein a single etching operation is used in forming said spacer structure and forming said trench.
14. The method of claim 13 wherein said single etching operation is further used in etching said spacer structure.
15. A structure formed according to the method of claim 1.
16. A method for rounding corners in a trench used in isolating devices in an integrated circuit, said method comprising: forming an oxide layer above a substrate, forming a hard mask above said oxide layer; forming a spacer structure on said substrate and surrounding said hard mask, said spacer structure having a portion with a rounded shape; forming a trench in said substrate proximate to said spacer structure; and etching said spacer structure and said substrate to form a trench corner with a rounded shape, said rounded shape of said trench corner being dependent on said rounded shape of said portion of said spacer structure.
17. The method of claim 16 wherein forming said hard mask comprises: forming a layer of nitride on said substrate; and etching said layer of nitride.
18. The method of claim 16 wherein forming said spacer structure comprises: forming a conformal layer over said hard mask; and etching said conformal layer.
19. The method of claim 16 wherein forming said trench in said substrate comprises forming said trench while leaving said spacer structure and said hard mask substantially intact.
20. The method of claim 16 wherein etching said spacer structure and said substrate comprises etching said spacer structure and said substrate while leaving said hard mask substantially intact.
21. The method of claim 16 wherein forming said oxide layer comprises forming said oxide layer by thermal oxidation of said substrate.
22. A trench with rounded corners formed according to the method of claim 16.
23. The method of claim 16 wherein a single etching operation is used in forming said spacer structure and forming said trench.
24. The method of claim 23 wherein said single etching operation is further used in etching said spacer structure.
PCT/US1996/012852 1995-08-09 1996-08-07 Process for rounding corners in trench isolation WO1997006558A1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6452246B1 (en) 1999-07-16 2002-09-17 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having an improved isolation structure, and method of manufacturing the semiconductor device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4857477A (en) * 1986-09-18 1989-08-15 Oki Electric Industry Co., Ltd. Process for fabricating a semiconductor device
EP0375632A2 (en) * 1988-12-15 1990-06-27 STMicroelectronics S.r.l. A process for excavating trenches with a rounded bottom in a silicon substrate for making trench isolation structures
JPH02271620A (en) * 1989-04-13 1990-11-06 Seiko Epson Corp Manufacture of semiconductor device
JPH02271619A (en) * 1989-04-13 1990-11-06 Seiko Epson Corp Manufacture of semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4857477A (en) * 1986-09-18 1989-08-15 Oki Electric Industry Co., Ltd. Process for fabricating a semiconductor device
EP0375632A2 (en) * 1988-12-15 1990-06-27 STMicroelectronics S.r.l. A process for excavating trenches with a rounded bottom in a silicon substrate for making trench isolation structures
JPH02271620A (en) * 1989-04-13 1990-11-06 Seiko Epson Corp Manufacture of semiconductor device
JPH02271619A (en) * 1989-04-13 1990-11-06 Seiko Epson Corp Manufacture of semiconductor device

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
MAA J ET AL: "Effects on sidewall profile of Si etched in BCl/sub 3//Cl/sub 3/ chemistry", JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B (MICROELECTRONICS PROCESSING AND PHENOMENA), JULY-AUG. 1990, USA, VOL. 8, NR. 4, PAGE(S) 581 - 585, ISSN 0734-211X, XP002017691 *
PATENT ABSTRACTS OF JAPAN vol. 15, no. 26 (E - 1025) 22 January 1991 (1991-01-22) *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6452246B1 (en) 1999-07-16 2002-09-17 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having an improved isolation structure, and method of manufacturing the semiconductor device
US6855615B2 (en) 1999-07-16 2005-02-15 Renesas Technology Corp. Method of manufacturing semiconductor device having an improved isolation structure

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