WO1997004542A3 - Multipoint-to-point arbitration in a network switch - Google Patents

Multipoint-to-point arbitration in a network switch Download PDF

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Publication number
WO1997004542A3
WO1997004542A3 PCT/US1996/011922 US9611922W WO9704542A3 WO 1997004542 A3 WO1997004542 A3 WO 1997004542A3 US 9611922 W US9611922 W US 9611922W WO 9704542 A3 WO9704542 A3 WO 9704542A3
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WO
WIPO (PCT)
Prior art keywords
input
fin
network switch
input port
multipoint
Prior art date
Application number
PCT/US1996/011922
Other languages
French (fr)
Other versions
WO1997004542A2 (en
Inventor
Thomas A Manning
Stephen A Caldara
Stephen A Hauser
Matthias L Colsman
Original Assignee
Thomas A Manning
Stephen A Caldara
Stephen A Hauser
Matthias L Colsman
Ascom Nexion Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomas A Manning, Stephen A Caldara, Stephen A Hauser, Matthias L Colsman, Ascom Nexion Inc filed Critical Thomas A Manning
Priority to PCT/US1996/011922 priority Critical patent/WO1997004542A2/en
Priority to JP9506867A priority patent/JP2000501902A/en
Priority to AU67620/96A priority patent/AU6762096A/en
Publication of WO1997004542A2 publication Critical patent/WO1997004542A2/en
Publication of WO1997004542A3 publication Critical patent/WO1997004542A3/en

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    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5681—Buffer or queue management
    • H04L2012/5683—Buffer or queue management for avoiding head of line blocking
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5685—Addressing issues
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/046—Speed or phase control by synchronisation signals using special codes as synchronising signal using a dotting sequence

Abstract

An apparatus and a method are disclosed for arbitrating between streams of ATM cells, or sources for a connection, on multiple input port processors vying for an opportunity to be transmitted as a fixed bandwidth, or allocated, connection on a single output port through a network switch. The network switch maintains a plurality of input port processors, at least one output port, and input and output buffers associated with the respective input and output ports. Streams of ATM cells enter the network switch as sources for a connection through the multiple input port processors and are buffered in the input buffers. The ATM cells are then routed from the input buffers to an output buffer in the output port. The network switch also provides a multipoint topology controller (MTC) and a bandwidth arbiter (BA) for performing the arbitration. The MTC looks up a Fan-In-Number (FIN) identifier for every cell time slot in a switch allocation table (SAT) for which a scheduling list has an entry, assuming that the input buffers, which are arranged into queues, that are listed on the scheduling list have ATM cells to send and the scheduling list has not exceeded its bandwidth allocation. The BA compares all the valid FIN identifies and, if there is a match, performs multipoint-to-point arbitration among the input port processors that have scheduling lists which reference that FIN. The BA reads the FIN state information and gives the bandwidth to the input port processor having the highest priority. The BA then updates the FIN state information with data that indicates which input port processor will have the highest priority on the next arbitration for this multipoint-to-point connection.
PCT/US1996/011922 1995-07-19 1996-07-18 Multipoint-to-point arbitration in a network switch WO1997004542A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/US1996/011922 WO1997004542A2 (en) 1995-07-19 1996-07-18 Multipoint-to-point arbitration in a network switch
JP9506867A JP2000501902A (en) 1995-07-19 1996-07-18 Multipoint-to-point arbitration in a network switch
AU67620/96A AU6762096A (en) 1995-07-19 1996-07-18 Multipoint-to-point arbitration in a network switch

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US149895P 1995-07-19 1995-07-19
US60/001,498 1995-07-19
PCT/US1996/011922 WO1997004542A2 (en) 1995-07-19 1996-07-18 Multipoint-to-point arbitration in a network switch

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WO1997004542A2 WO1997004542A2 (en) 1997-02-06
WO1997004542A3 true WO1997004542A3 (en) 1997-04-24

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EP1176767B1 (en) * 2000-07-27 2007-09-05 Roke Manor Research Limited Improvements in or relating to switching devices
CN115190024B (en) * 2022-05-30 2023-03-28 中科驭数（北京）科技有限公司 Basic unit of multi-topology structure bus and topology structure

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AU6762096A (en) 1997-02-18
JP2000501902A (en) 2000-02-15
WO1997004542A2 (en) 1997-02-06

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