WO1996041277A1

WO1996041277A1 - Neutral network processor for communication systems and method for its use

Info

Publication number: WO1996041277A1
Application number: PCT/US1996/009621
Authority: WO
Inventors: Alex D. Rast; Mark A. Astengo
Original assignee: Inficom, Inc.
Priority date: 1995-06-07
Filing date: 1996-06-07
Publication date: 1996-12-19
Also published as: AU6105296A

Abstract

A self-contained device to transmit and receive data communications over long ranges at high speeds. The unit uses a Neural Net Processor (NNP 18) to control a lock-in/synchronous detector operating at radio frequencies. The synchronous detection device (44) employs variable feedback to enhance the signal and contains alternating active integrators (46) for higher signal resolution. The transmitter (88) employs synchronous power modulation to transmit a data stream. The NNP 18 controls synchronization of all the units. Its internal structure employs a division into a neural control unit and neural execution units. The control unit is itself divided in the same way. Unique internal structures in the NNP 18 enhance its functionality.

Description

NEURAL NETWORK PROCESSOR FOR COMMUNICATION SYSTEMS AND METHOD

FOR ITS USE

Technical Field

The present invention relates to methods and apparatus for application of a neural network processor, and more particularly, to methods and apparatus for applying a neural network processor to a communication system.

Background of the Invention

Modulated radio signals heavily buried in noise are difficult to detect. Filtering may not remove enough of the noise to allow the signal to be detected accurately. One of the principal difficulties with filtering is that standard detectors known in the prior art have tuning parameters that depend on the characteristics of the signal. There are two primary ways to get around the detection problem described above. One way is to provide a technique in which the tuning is not critical. However, such a technique trades off ultimate detection sensitivity for detector stability. The other way is to sample the noise-buried radio signal and process then the sample in order to tune the receiver. Until the present invention, this sampling method, has relied upon sampling the signal before detection. The reason is that the output signal from the detector is the actual transmitted information and carries no information about the modulated signal.

A neural net processor overcomes many of these limitations. Neural nets readily extract signals from noise. Therefore, if for no other reason, a receiver can employ a neural net for post-detection processing, to improve SNR. Neural net technology also works well for adaptive control. Such a situation exists in the radio detection problem, where the received signal changes in response to environmental changes, interference from landforms, and various forms of electromagnetic interference. In addition, a neural net can control parameters of the detector with input only from the output of the detector. In other words, it can successfully tune the detector without having to know anything about the specifics of the modulated signal.

The body of literature on neural network applications is extensive. After about 1982 there are many works examining the application of neural networks to signal processing. Hoyt and Wechsler, in their 1990 paper "An Examination of Multi- Layer Neural Networks to Audio Signal Processing" discuss using a neural net to locate a speech signal buried in noise. They use a neural net processor as the basis for an adaptive filter. The neural net itself is a multilayer perceptron with backpropagation learning algorithm. The paper gives no indication as to whether the neural net is a simulation or a hardware implementation, or whether it is an on-line or off¬ line technique. From the general comments of the paper it appears that their work used an offline simulation but that they plan eventually to implement the system in hardware. One of the major issues in systems control is that frequently the available information about the controlled process is insufficient to describe completely to the controller the steps it needs to execute to control the process. Barto, Sutton, and Anderson, in their 1983 paper, discuss a method to solve control problems where the nature of the problem prohibits a priori knowledge of the best solution. In their paper, they apply the method to the problem of balancing a broom on a cart. In this case, the only available information is that of complete failure; i.e., when the broomstick falls the processor can conclude it has made an error. Their solution involves two neural units, an

Associative Search Element (ASE) that actually controls the broom and looks at the current input, and an Adaptive Critic Element (ACE) that looks at the processing of the neural and at past behaviors. The ACE reinforces the ASE if its current processing matches a past successful behavior and suppresses the ASE if its processing matches a past unsuccessful successful behavior. The processor in this case was a software simulation only.

In real-time control environments, such software neural nets are insufficiently fast. U.S. Patent #5,259,064 (Furuta et al.) describes a hardware embodiment of Barto et al. 's concept. The embodiment is an all digital neural net requiring off-line supervised training. That is, the neural net can only learn when it is not processing, and requires input from a user. The topology of the neural net is feedforward and the learning algorithm follows the method of backpropagation. The implementation of the ACE is also very simple and not a true neural net. Therefore, it is best suited for control environments where the nature of the input is fairly statistically consistent with time.

For environments where the input statistic itself changes with time, the neural net must be able to create new category recognition codes while on-line. A neural net of this type is an unsupervised neural net. U.S. Patent No. 5,133,021 (Carpenter et al.) describes ART-2, a neural net capable of self-organization. This design is analog and the topology is feedback. ART-2 can recognize analog patterns quickly (i.e., in real time) . The patent does not mention using ART-2 in a control application. A neural net of this type, however, used in a method similar to that of Barto et al. , should be able to solve complex control problems while adaptively learning, in real rime.

One way to detect radio signals among noise is to look for particular frequency distributions. A neural net can be to pattern recognize in such a system. U.S. Patent #5,233,354 (Wroth et al.) describes using a neural net to recognize frequency patterns. In their case the neural recognizes radar patterns by performing a spectral analysis on the signal. It discriminates targets as possessing a narrow and unshifting frequency band. The device is used for recognition only and not for control. The patent neglects to mention whether such a device operates in real time.

It is desirable, therefore, to control a radio receiver with a neural net capable of processing and learning, all in real time. Such a detection system has a receiver tuned by a neural net. The neural net processor itself should be self- organizing, i.e., unsupervised-learning. It needs to process analog input data, in real time. It must also control other devices based on inputs to the neural net, whose inputs themselves may not be sufficient to characterize the correct control responses. In this application, the neural net should output control signals to the detector itself, to optimize the detector's response to the particular input signal. The neural net can also provide back-end postprocessing of the detected signal, to further improve the SNR. Such a detection system can improve radio reception markedly over conventional techniques. Summary of the Invention

According to one aspect, the invention is an apparatus for detection of a particular electromagnetic signal included among other electromagnetic signals. The apparatus comprises a detector and a neural net processor. The detector receives all of the electromagnetic signals and a detector control signal and produces a detected signal in response thereto. The detected signal has first and second states respectively indicating that the apparatus has and has not detected the particular electromagnetic signal. The a neural net processor receives the detected signal and produces the detector control signal in response thereto. The detector control signal is fed back to the detector.

According to a further aspect, the invention is a method for detecting a particular electromagnetic signal included among other electromagnetic signals. The method comprises the steps of a) receiving all of the electromagnetic signals and a detector control signal and producing a detected signal in response thereto, the detected signal having first and second states respectively indicating that the apparatus has and has not detected the particular electromagnetic signal, b) and transmitting the detected signal. The method further comprises the steps of c) receiving the detected signal and producing the detector control signal in response thereto, d) transmitting the control signal, and e) causing the detector control signal to be received.

Brief Description of the Drawings

Figure 1 is an overall schematic diagram of the apparatus of the inventive device.

Figure 2 is a diagrammatic representation of some of the types of signals with which the inventive apparatus is useful. Figure 3 5 shows a first phase detector for use with the preferred embodiment of the invention.

Figure 4 shows a first improved circuit for use with the preferred embodiment of the invention. Figure 5 shows a neural predictor of the sort known in the prior art.

Figure 6 shows a novel will generator, which is a part of the present invention.

Detailed Description of the Preferred Embodiment of the Invention

Figure 1 is an overall schematic diagram of the apparatus of the inventive device. The apparatus 10 of the inventive device includes three distinct modules: a digital interface module 12 to allow communication with a host computer (not shown), a transmitter module 14, and a receiver module 16. A neural net processor 18 controls all of the modules 12, 14, and 16. In this context the can be considered as a CPU for the apparatus 10 of the inventive device. The digital interface module 12 comprises a controller 20 for an interface to a conventional SCSI bus (not shown) , respective first and second FIFOs 22 and 24 to buffer I/O respectively from and to the SCSI bus controller 20, and respective first and second conversion sections 26 and 28. The first and second conversion sections 26 and 28 are respectively a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC) . The first and second conversion sections 26 and 28 are respectively optically isolated from the first and second FIFOs 22 and 24 by first and second optoisolators 30 and 32. To be specific, the digital signals produced by the first FIFO 22 are transmitted through the first optoisolator 30 to the DAC 26 and the digital signals produced by the ADC 28 are transmitted through the second optoisolator 32 to the FIFO 24. By this optical isolation the I/O stream signals from and to the SCSI bus controller 20 (and thence from and to the SCSI bus) are translated to and from the rest of the circuitry of the apparatus 10.

A SCSI interface is chosen to stream data to and from the host computer in several advantageous ways. First, the SCSI standard is well-defined and there are no engineering complications that have to be worked out. Second, many different computer platforms support the SCSI interface, allowing the^"device to have a measure of platform- independence. Third, hardware components for implementation of a SCSI interface exist and are readily available commercially as standard parts, allowing much simplified design of the digital interface. Fourth, advantageous software interfaces for SCSI (such as ASPI) much reduce the task of programming a software front end for the device, allowing rapid deployment. Fifth, the SCSI standard specifies data rates that are sufficiently high to permit data to be transferred at the anticipated internal data rates. Sixth, the eight-bit-wide specification of the data path described above matches readily available conventional high-speed ADC and DAC chips. Therefore, the chosen interface needs no additional processors to match bit widths. Seventh, the SCSI architecture scales well.

There are various version of the SCSI interface available. The SCSI-1 and narrow SCSI-II interfaces both support a total of eight devices on the SCSI bus. This allows connection of several devices such as the inventive apparatus 10 described here, as well as conventional 1/0 devices. In addition, wide SCSI-II and the upcoming SCSI-II in both provide a clear upgrade wide SCSI-II and the upcoming 16- and 32-bit SCSI-II interfaces all provide a clear upgrade path for future devices when ADCs and DACs of greater bit widths become commercially available.

The analog portions of the first and second optoisolators 30 and 32 detect extremely weak signals. Therefore, it is imperative to reduce noise from other components near the device as much as possible. An optoisolator handles this task effectively. At present a conventional optoisolator capable of supporting the data rates required is the Hewlett-Packard HCPL 7101. This device specifies a data rate of up to 50 Mbps.

The neural net processor 18 controls the DAC 26 through the control line 30 and the ADC 28 through the control line 32. In order for transmission and reception of the control signals through the control lines 30 and 32 to work properly, the neural net processor 18 must synchronize the transmission frequency of the control signals through the control lines 30 and 32. The control signals on the control line 30 are transmitted from the NNP 18 through the control line 31. It must also synchronize the sampling rate of the ADC 28 to the SCSI bus through the SCSI bus controller 20. Therefore, the clock frequency input to both the DAC 26 and the ADC 28 comes is produced by the neural net processor 18 (hereinafter referred to as NNP 18) . NNP 18 monitors the output of the DAC 26 through the line 34, and the input to the ADC 28 to make sure that the clock frequencies of the DAC 26 and the ADC 28 are properly matched. A subsequent section of this patent application describes the operation of the NNP 18 in considerably more detail.

There are many digital-to-analog converters supporting a sufficiently high sampling rate to serve as the DAC 26. For the purposes of the apparatus 10, a minimum 8-bit sampling rate of 100 megasamples per second (Msps) was specified. Such a high sampling rate mandates the use of flash analog-to- digital converters for the ADC 28. The AD9002 ADC used specifies a conversion rate of 125 Msps. In addition, using a flash analog-to-digital converter for the ADC 28 eliminates the need for sample-and-hold circuitry between the NNP 18 and the ADC 28. This allows continuous, real-time data transmission between the apparatus 10 and the host computer to which the apparatus 10 is connected. Applications such as computer data networks require capabilities of such high rates.

To match the input signal to the ADC to the expected input range of the AD9002 ADC, it is necessary to provide an amplified input driver. Signals coming from the output of the receiver will in general have a varying output range depending on the RMS received signal power at the receiver. It is desirable, therefore, to provide a variable gain in the ADC input drivers so that the output of the ADC maintains a consistent digital representation of the received signal. In the case of the current embodiment, the received signal falls into a range of 255 discrete levels. The formula for these signal levels is: S_r=P_RMS/255*S_A, where S_r is the received signal level, and S_A is a number from 0 to 255 describing the absolute signal level (the desired output of the ADC) . Therefore, the driver must provide gain G such that G = [S_A(A_max-A_n._in)+A_πιin]/S_r where A-.- is the analog input value to the ADC that produces a digital output value of 255 (11111111 binary) and H_niΛ is the input value to the ADC that produces a digital output value of 0 (00000000 binary) . To implement this variable-gain driver, the apparatus 10 employs the same circuit as the synchronous multiplier 82 in a different configuration. In this case, the input to the driver is the input to the op-amp and the input to the MOS transistor is a tuning signal that determines- the gain of the overall driver. The NNP 18 controls the signal to the MOS transistor. To determine the control signal, the transmitting apparatus 10 sends a pre-determined signal that the NNP 18 of the receiving apparatus 10 compares against an internal reference. The pre-determined signal consists of a 255 clock cycle pulse of reference level 255, a constant ramp from reference level 255 to reference level 0 again occupying 255 clock cycles, a 255 clock cycle pulse of reference level 0, a constant ramp from reference level 0 to reference level 255 occupying 255 clock cycles, and a second 255 clock cycle pulse of reference level 255. The NNP sets the tuning value to the driver that provides the best fit between the output of the ADC and the internal reference signal.

The receiver module 16 includes a receiver 40, a prefilter 42 and a phase detector 44. The receiver module 16 also includes an integrator 46 and a postfilter 48. In addition, the receiver module 16 includes a phase shifter 50 and a frequency divider 52. Signals from the receiver 40 are passed to the prefilter 42 through a signal line 54 and then to the phase detector 44 through a signal line 56. Signals from the integrator 46 are passed to the postfilter 48 through a signal line 58 and then to the NNP 18 through the signal line 60. The phase shifter 50 receives signals from the NNP 18 through the control line 31 and the signal line 70. The phase shifter 50 produces lock frequency signals in response to the signals on the respective control and signal lines 31 and 70 and transmits those signals to the phase detector 44 and frequency divider 52 through the signal lines 72 and 74, respectively. The frequency divider 52 receives a signal from the phase shifter 50 through the signal line 74 and a signal from the NNP 18 through the signal line 76 and produces a frequency-divided signal on the signal line 7-8 for transmission to the integrator 46. Also, the- NNP 18 produces a control signal on the signal line 80 for transmission to the phase detector 44. This configuration is a highly sensitive, neurally-controlled synchronous detector that detects power- modulated (or synchronous AM) transmissions.

The synchronous multiplier 82 receives the signal O_mlt over the signal line 84 and is synchronized by the signal ω from the NNP 18 over the line 86. The output of the synchronous multiplier 82, S^_t = (0 (0^) , is transmitted to the transmitter 88 over the signal line 90. The transmitter 88 then transmits the signal in a conventional manner.

Use of the term "power modulation" (PM) deserves a few additional remarks. Figure 2 is a diagrammatic representation of some of the types of signals with which the inventive apparatus 18 is useful. Figure 2 illustrates the differences between AM and PM and in addition shows the type of distortion that non-synchronized signals produce.

With reference to Figure 2, standard amplitude modulation (AM) is the simple asynchronous mixing of an analog signal 100 onto a high frequency carrier 102 to produce an AM signal 104. The analog signal 100 is usually assumed to contain much lower frequencies than does the high frequency carrier signal 102.

Standard AM modulation creates a spectral distribution 106 from respective analog and high frequency carrier signals 100 and 102, which have respective spectral distributions 108 and 110. The spectral distribution 106 has symmetrical sidebands 112 and 114 around the spectral peak 116 at the carrier frequency. The spectral distribution 106 accurately represents the spectral distribution of the frequencies of the high frequency carrier signal 102. This type of modulation is unacceptable in the case of synchronous detection if high levels of noise rejection are desired.

In order to improve noise rejection and provide a more easily detected signal, the inventive apparatus 10 uses power modulation. In power modulation, an analog-valued digital signal 120 multiplies a high frequency carrier signal 122 by an amount corresponding to the analog value representation of a specific waveform to produce the power modulated signal 124.

The analog ^"value represented is part of an analog representation of a data stream whose information in general may be quite arbitrary. In the context of the present device, the analog values are produced by the DAC 26 (see Figure 1) . Transitions between different values of the analog representation occur only synchronously; that is, the transition frequency corresponds to an even harmonic of the carrier frequency. In addition, the transitions between different values of the analog representation occur only at the zero-crossing points of the high frequency carrier signal 122. The spectral distribution of the power modulated signal 124 then contains only the high frequency carrier signal 122 and its harmonics, as may be seen by comparing the spectral distributions 126 and 128. (The spectral distribution of the analog-valued digital signal 120 is shown in the spectral distribution 130.)

It is important to note that modulation of this type is only possible when the modulating analog-valued digital signal 120 is a data stream. The modulating analog-valued digital signal 120 cannot be an analog waveform in the standard sense, since then there is no way to ensure that the modulating analog-valued digital signal 120 will modulate the high frequency carrier signal 122 synchronously. In addition, it should be clear that synchronization is a critical issue. If the phase or frequency of the modulating analog-valued digital signal 120 deviates too much from that of the high frequency carrier signal 122, the power modulated signal 124 will be distorted. As a practical matter, this means that the NNP 18 must continually monitor the modulation process to maintain precise synchronization.

The well-known synchronous (or lock-in) detector detects signals of this type. With the use of power modulation (PM, described above) , it is possible to employ some additional techniques in the detector section of a receiver to improve signal resolution still further.

Figure 3 shows a diagram of a typical lock-in detector. The theory of a lock-in detector is as follows. An input signal initially passes through a bandpass prefilter to remove noise far away from the signal of interest. The signal then passes through a phase detector, essentially a synchronous rectifier whose rectification period corresponds to the carrier frequency of the incoming signal. The detector rectifies signals that match its frequency and phase to continuously positive values, while signals whose frequency and phase do not match do not get rectified in this manner.

Figure 4 illustrates this process. An oscillator connected to a phase shifter controls the detector frequency. The rectified signal then passes through an integrator. Input signals in phase with, and of the same frequency as, the detector frequency integrate to some finite value, while noise, which has a random frequency and phase, integrates to zero since integration is an averaging function. Finally, the output passes through a postfilter, usually a low-pass filter, to eliminate any remaining interference from nearby signals.

In such a device, proper synchronization of the detector is critical. Even a small mismatch leads to hum and distortion. Moreover, the synchronizing signal tends to drift on both short and long time scales. As a result, a fixed- frequency clock proves unacceptable in such a detector. The conventional method of providing a synchronized signal is to use a phase-locked-loop (PLL) . As is well-known, a PLL samples the input frequency of a signal and provides an output frequency that settles to a value precisely matching the frequency and phase of the input. This device eliminates the drift and synchronization problems described above.

A PLL, however, has significant disadvantages. Since it must sample the input signal, it will not settle to a good locking frequency if the signal of interest lies buried in noise, i.e., if the received SNR is too low to allow any detection of the signal before passing through the phase detector. Such a disadvantage is acceptable if the signal has sufficient SNR or if the modulating carrier of the signal may be passed to the PLL without noise. Such a condition arises, for instance, if a carrier signal modulates some nearby signal source, where a direct wire can connect the carrier generator to the PLL. Obviously in a radio transmission application, this condition does not exist.

A second method occurs if a detector placed in front of the lock-in detector can retrieve sufficient signal to allow the PLL to lock. In an AM application, for instance, one can place a superheterodyne receiver in front of the synchronous detector that is part of the system. If the superheterodyne receiver retrieves enough signal, the PLL locks and the synchronous detector can operate properly. This tactic, however, will not work with power modulation, since the heterodyning process destroys the strict synchronization of the signal. In addition, the tactic will not work if the signal is so weak that the superheterodyne receiver cannot improve the SNR sufficiently to allow the PLL- to lock. A third method involves choosing a carrier signal frequency that is a standard reference signal available as a broadcast from any location. Signals such as GPSS and the National Time Standard are examples of such frequencies. This method, however, places severe restrictions on the frequencies available for transmission and makes the device not strictly self-contained. Also, there are time-delay and other synchronization issues involved arising from different conditions at the transmission (or source modulation) site and the reception (or target modulation) site.

For many reasons, then, a PLL is undesirable if the signal of interest-is extremely weak. The present inventive device solves the synchronization problem by inserting a neural net processor (such as the NNP 18, shown in Figure 1) into the lock-in detector. The NNP 18 provides a reference signal to the lock-in detector based on retrieved signal from the detector itself and not from the stage before the detector. In other words, the receiver is an active detector rather than a passive detector. Such a solution allows for the retrieval of signals buried far below the level required for other methods to allow detection.

Operation of the lock-in detector in this fashion is somewhat different than the operation of a conventional detector. Since there is no way of knowing the initial value of a signal, the lock-in detector must provide a procedure for searching for a signal and locking into the signal once the lock-in detector finds the signal. The lock-in detector of the inventive device has three operating modes.

In an out-of-lock condition (that is, there is no signal at all) , the NNP 18 provides a signal to the phase detector 44, where the frequency of the signal slowly sweeps through the entire band of frequencies allowed for transmission. Sweep times are typically approximately 1 second in length. The NNP 18 also sweeps through the phase at a rate that is large compared to the frequency sweep but small compared to the frequencies of interest. The phase detector 44 remains in this state until the NNP 18 detects a signal.

When the NNP 18 detects a signal, it stops the frequency sweep and rapidly sweeps the phase until it finds the best possible match to the signal. At that point the detected signal is locked. In the locked state, the NNP 18 continually adapts the frequency and phase, looking for the best possible signal match. The phase detector 44 shows small adjustments in frequency and phase, but shows no consistent pattern unless the frequency deviations themselves have some regular cause. The lock-in phase detector 44 itself contains two enhancements that improve the SNR performance and allow additional detection speed. The first enhancement is in the phase detector 44.

Figure 3 5 shows a first A phase detector 150 for use with the preferred embodiment of the invention. The first phase detector 150 is an amplifier whose gain is periodically reversed, so that the first phase detector 150 alternates between an inverting configuration and a noninverting configuration. The frequency of the configuration reversal is the phase detector frequency. The first phase detector 150 has enhanced performance when it operates close to the lock frequency if the feedback loop of the amplifier contains a variable impedance which is at a maximum at the detector frequency. In such a case, the amplification of the first phase detector 150 will be large when it operates at frequencies close to the detector frequency, and the amplification of the first phase detector 150 will be small when it operates at frequencies far from the detector frequency. If the filter of the integrator 152 is sufficiently sharp, the integrator 152 will give large positive output values for signals matching the detector frequency and output values tending to zero for signals that do not match the detector frequency. Such a detector therefore effects a large improvement in the dynamic range.

Figure 6 is a diagram of the implementation of tThe phase detector. It consists of a detector of the type just described, whose feedback is a bridged differentiator filter with notch frequency determined by a voltage-compensated and normalized MOS gate. A MOS gate in the subthreshold regions acts like a variable resistor and is ideal for this application. The NNP 18 controls the value of the resistance of the MOS gate, keeping it at a value that makes the center frequency of the filter match the frequency of the phase detector.

The second enhancement of the lock-in phase detector 44 is at the integrator. Frequently, the integrator is a simple lowpass filter. This is adequate for low-frequency signals where the resolution is good, but undesirable for high frequency signals or when the resolution remains poor after phase detection. The inventive apparatus then uses a different type of integrator. The integrator of the second enhancement consists of two active integrators alternately switched between periods of integration and reset.

Such a system offers specific advantages. For one, the integrator can successfully integrate signals that are monotonically positive. By way of contrast, an unswitched integrator will ultimately saturate on such a signal and provide no further useful integration. As a result, the device is also insensitive to drift effects and other properties tending to distort the integration. An external clock signal can control the integration period, making the inventive apparatus ideal for the recovery of synchronized signals. Finally, the design of the apparatus allows for smaller capacitor values, permitting higher precision at high frequencies. Figure 7 is a diagram of the integrator. Because of the properties of the integrator just described, the NNP 18 can control the integration frequency and phase to further enhance the received signal. At very short integration periods, there will be an incomplete cancellation of nearby noise signals and, as a result, the SNR declines. At long integration periods, SNR increases, but the allowed data rate declines (it can be no faster than one period) . The NNP 18 adjusts the frequency and phase of integration to permit the maximum data rate possible under the circumstances.

The other parts of the lock-in detector are standard. The prefilter is a 4-pole Chebyshev bandpass filter with l dB ripple and a bandpass of 200-600 MHz. The postfilter is an 8- pole Bessel low pass filter with a 3 dB point of 150 MHz. The phase shifter and frequency divider both have operating frequencies matching those of the prefilter.

The assembly consisting of the synchronous multiplier and transmitter constitutes the transmission module of the device. The transmitter is standard. The synchronous multiplier, however, constitutes an original component.

Referring to the earlier discussion of power modulation, it should be clear that any transmitter designed for power modulation must have an extremely stable modulator. The synchronous multiplier (such as the synchronous multiplier shown in the transmitter module 14 of the apparatus 10) is this device. At this point it should also be clear why the NNP 18 controls the output of the DAC 26 (see. Figure 1) : the DAC 26 must be synchronous with the carrier in order to effect power modulation.

The synchronous multiplier consists of a gyrated MOS transistor, actively compensated to offset nonlinearities in the subthreshold resistance and provide appropriate input biasing. In this case the compensation circuitry maps signal input voltages O^ to values that keep the MOS transistor in the subthreshold region while keeping a linear relationship between different input values. The MOS transistor is gyrated to make its effective resistance increase rather than decrease with increasing gate voltage and inserted into the feedback loop of an ordinary op-amp, a Comlinear CLC449. Such a circuit has the effect of multiplying the input signal to it by a value that is proportional to 0_BUt. The input to this amplifier is the carrier frequency ω while the O^_t input is the signal. The NNP 18 controls both the carrier frequency and the signal, making sure that their respective frequencies and phases match. In the diagram, The carrier is denoted by co, the signal is denoted by 0-^, the output is denoted by S^_t, and V_R denotes a voltage chosen to place appropriate biasing for the transistor.

The 0-,-_t values are in the range 0-255 corresponding to input 8-bit digital data from 00000000 to 11111111. The synchronous multiplier thus multiplies a carrier by a scaled quantity proportional to these values such that S^_t/S^_t. = Oout/O_ouc • For example, if _mt = 16 and 0^, •= 8, then S^_t could be 32 and S-^_t. could be 16, or any representation such that S-_ut/S_out- = 2. Different values of V, only occur at even multiples of the carrier, that is, 5θ_out /3θ_ouc, ■ kω_c. Again, refer to Figure 2 for more information. The NNP 18 is, as Figure 1 implies, the central unit of the device. This processor is a VLSI analog neural net chip with multiple on-board modules. Traditional NNP chips and software simulations focus on one neural net topology and learning strategy. The current device uses multiple different neural net topologies and strategies to optimize its processing for different tasks. Figure 9 details the internal architecture of the NNP 18.

One of the most important facts about the nature of the processing task that the NNP 18 faces is that it must adapt to a system with more variables than it has complete information about. The NNP 18 has only one measure of its adaptive success: the received signal resolution. By contrast, there are no less than four parameters that directly affect the achieved resolution. They are the detector frequency, the detector phase, the integration frequency, and the impedance of the phase detector feedback loop. Such a system falls into the category that Barto, Sutton and Anderson examine in their paper. Their solution is to split the neural net into a part that performs the actual tasks required and a part that examines the performance of the system, providing positive or negative reinforcement as necessary. Positive reinforcement occurs upon the execution of a successful behavior while negative reinforcement occurs upon the execution of an unsuccessful one. The neural net processor used in this device employs such a scheme. The unit within the processor that examines the performance is the Vital Functions Unit 200 (hereafter VFU) - see Figure 4, which 4 shows a first improved circuit for use with the preferred embodiment of the invention..

In the case of the NNP 18 used in the device, the internal structure is very complex. Therefore, the VFU 200 itself faces the same issue that the processor as a whole faces. It must perform a task with insufficient initial information to determine the process to follow. Therefore, the VFU 200 is in turn divided in the same way into the same two components. The part that examines the system is the Operations Monitor 202 while the part that performs instructions is the Command Generator 204. The Operations Monitor 202 is connected to the Command Generator 204 through the control .line 206.

The nature of the inventive apparatus 10 means that for long periods of time there is no significant input data. Therefore, the actual detector units that are part of the inventive apparatus 10 will be inactive most of the time. Only during transmissions will the detector units actually operate. To insure that the NNP 18 does not spontaneously adapt to the meaningless input state of no input, no unit in the inventive apparatus 10 performs any computation without instruction from the VFU 200. That is, the units in the inventive apparatus 10 must receive positive reinforcement from the VFU 200 before they start processing. Each of the neural net structures in the processor of the inventive apparatus 10 has, as some input, neurons directly connected to the output of the VFU 200. The control line in Figure 9 connects these neurons. As the diagram of Figure 4 shows, the output layer of the VFU 200 that provides this input to the control line is in the command generator. It is the command generator that oversees and directs the operation of the rest of the NNP 18. The command generator must be able to produce an output even in the complete absence of input to the NNP 18. The command generator also must be able to direct the other units to perform tasks. To this end, the command generator contains two special neural nets: a predictor and a will generator. A separate section discusses the operation of these two special neural nets. Functionally, the predictor, as shown in Figure 5, gives the probability that the (n+x)^th input will give output A, based on the output A' given by the n^th input. The will generator takes a random input distribution and produces an output W to process P whose statistical likelihood is proportional to the desirability D of that output. D is the measure of the distance between the output vector of a unit and the nearest matching stored memory. The will generator actually maps the statistical distribution of the random input to the various possible inputs it can provide to the process.

The output, W, activates those neural pathways that cause process P to create the output state that D measures. The will generator supplies output values to the other units of the processor and in return receives feedback from a predictor. The commands it issues to the other units will therefore have an output state whose distance from a stored memory matches their individual occurrence at the predicted time T_n+X. The properties of these described neural nets satisfy the requirements outlined above. Namely, such a neural net unit produces an output even in the absence of input (the random input vector to the will generator assures an output vector) and the neural net unit supplies a command to the other units of the processor. The command generator satisfies the second condition as long as the other neural net units have activation function in all neurons such that a neuron will never exceed threshold if none of the inputs J from the command generator is active.

Mathematically, this means the following: take a neuron v_A with inputs i,j corresponding to inputs from other neurons and inputs from the command generator, and coupling coefficients T_i and T_! between other neurons and neurons in the command generator. Let σ_i:j = ∑_4j

. Let f(σ_i:j) be the output of v_i# where f is the activation function. Then f(σ_i;j) « 0 for j-0. The neurons used in the NNP 18 will have this property. In addition, these neurons have the property required to create a random input vector at the input layer of the command generator, namely, they generate spontaneous signals. Careful choice of the transfer function allows the same basic neuron design to fulfill both of these requirements.

The operations monitor performs much the same process on the command generator as the command generator does to the rest of the processor. The command generator, however, does not require input from the operations monitor in order to proceed. This follows from the will generator: a neuron that produces spontaneous signals has this property:

If f(σi_j)_t = 0, f (σ_ii) _t. -≠ 0, But for any unit that only processes upon input from a specific unit, f(σ_i:i) « 0, j = 0, thus in this case, assuming the approximation f (o_i ) _t = 0 = £ (σ_±i ) _t. = 0.

Therefore it is impossible to have a neuron that simultaneously spontaneously produces a signal and processes only upon input from another unit.

The operations monitor does, however, alter the values of the synaptic weightings of the command generator. The operations monitor takes an input vector that consists of the output vectors of the four major functional units of the NNP 18. Following the work of Grossberg, the operations monitor uses an adaptive resonance topology neural network to match the input vector to the nearest stored pattern, or to add a new pattern if there is no good match. The neural network is analog in implementation; however, it does not use input contrast enhancement as in ART-2.

The resulting pattern next becomes the input vector for a predictor. The output of the predictor in turn feeds into an analog Hopfield neural net. If the distance between the output and a stored memory is large, i.e., if the time to settling of the network is long, the operations monitor outputs a negative reinforcement to the neurons that were active in the command generator at the arrival of the initial input vector. A separate buffer stores which neurons were active. If the distance between the output and a stored memory is small, i.e., the settling time is short, the operations monitor outputs a positive reinforcement to the neurons in the command generator. The reinforcement values are analog values that can be normalized into the range t-1,1] where -1 represents absolute suppression and one absolute enhancement. The analog value is a scaled measure of the time the Hopfield neural net takes to settle to a final state.

The inference processing unit (IPU) 210 is the unit that does most of the core processing task: identifying the input signal of the lock-in detector. It has several subunits to maximize its ability to find a pattern match. The primary unit is an associator, a neural network again following the ART topology and including on-center off-surround lateral feedback for contrast improvement and noise rejection in all layers. A secondary unit, the similarizer, uses an analog Hopfield model to compare the input pattern against previously established patterns stored as memory states. The unit also includes a guesser, a unit that has a simple will generator connected to a simple network that computes the difference between the guess vector and the input vector. If there is a match, the guesser outputs the value thus generated. The process that the will generator uses to develop its structure is the associator. As soon as any one of these units finds a pattern match, it outputs that value to a central control unit. The control unit contains the input neurons for the entire IPU 210, and the output neurons as well. These neurons connect to the respective input and output layers of the other units in the IPU 210. The control unit also contains a timer that measures the number of passes through each of the structures the input vector makes before one of them identifies the vector. Good signal resolution corresponds to short matching times. The control unit sends information about the matching times, matching units, and identified pattern to the VFU 200.

Several of the units on board benefit from a unit able to do pure math and logic calculations, and to that effect, the NNP 18 includes an arithmetic logic unit (ALU) 220. It is, in fact, fairly simple to implement versions of standard functions using neurons. A neuron with unit input synapse weights performs the add and subtract operations. A neuron with only one input performs multiply and divide operations. In this case, the multiply operation actually occurs at the synapse. In this context, it is inappropriate to consider the synapse as a stored memory. The synapse is the multiply operator. Various combinations of neurons and connections also enable AND and OR functions. In fact, AND and OR represent different threshold functions. The on-board ALU 220 incorporates these elements and in addition a few logical operators, notably a vector sum and integral, that are very difficult to implement using digital circuits.

The final component in the NNP 18, the input/output translator (hereafter I/OT) 240 is the processor's external interface. The I/OT 240 also handles the task of routing input data to the appropriate processor's external module. The I/OT 240 also contains the controllers for each of the four variable parameters that the NNP 18 can control to improve signal resolution: the frequency co, the phase φ, the integration period A, and the feedback network impedance R. The command generator sends instructions to each of these units to alter their values in order to improve the achieved resolution.

These interfaces have a design matching their function. Thus ω is a PLL, and φ, A, and R are simple op-amp outputs developing a control voltage. The input channel is an ART network with contrast enhancement to improve the input signal as much as possible before sending it to the rest of the NNP 18. The output channel is a neural summing junction that takes the multineural output pattern of the NNP 18 and converts it to a single output value suitable for conversion by the ADC 28.

The translation interface of the I/OT 240 has two primary processing units. One is a spectrum analyzer. This neural net breaks down the signal into its spectral components.

Primarily the neural net is looking for signal energies in a narrow band of frequencies. The neural net also looks for any tendency of the peak of narrow energy distributions to drift. Such a drift manifests as a slow exchange in the activations of adjacent output neurons.

The second unit performs a more complex process: it finds the chaotic stability of the system. Chaotic stability is the tendency of similar input vectors to map to similar output vectors. Mathematically, this function is

Note that chaotic stability exists only over a specified range. It is possible to define chaotic stability over an entire function, but such a function is of limited practical value. In any case, any neural net can easily find a good approximation to the chaotic stability of a given input vector set by simply feeding back the output vectors to the input. A chaotically stable system rapidly settles to a single state while an unstable one requires many iterations before it settles. The simplest form of neural net implementing this function is the bi-directional associative memory (hereafter BAM) . Therefore, the I/OT 240 contains an adaptive BAM (not shown) to measure the chaotic stability. The measure of the chaotic stability is the time it takes the synapses to stop changing with each pass. The VFU 200 determines how the I/OT 240 routes input data. The I/OT 240 uses chaotic stability to determine where a given input vector should go. In general, it is probable that the I/OT 240 will route data of low stability to the IPU 210 and data of very high stability to the ALU 220. The I/OT 240 discards extremely unstable input as probable noise. The NNP 18 has various operating modes. Hardwired weights in the VFU 200 determine some of these modes. The first operation the NNP 18 always performs at power-up is to load its synapse values to the local synapses from an on-chip EEPROM. This is an operation hardwired into the command generator. As soon as the processor loads its synapses, it passes out to this mode and normal operation begins. With no signal detected, the command generator suppresses operation of all units except the spectrum analyzer in the I/OT 240. The I/OT 240 continues to analyze the input while the VFU 200 slowly sweeps the frequency and phase. It adjusts R to match the output frequency co. Once the I/OT 240 finds a signal in a narrow frequency band, the VFU 200 turns on all the other units.

During a detection phase, the NNP 18 focuses on rapid identification of the signal. The signals pass to the various processing units where they attempt to identify a signal. Meanwhile, the VFU 200 sweeps the phase somewhat faster to find a better matching phase. If the NNP 18 detects a signal, it looks for a certain signature.

A power-modulated signal has amplitude-valued data. Therefore, it is of prime importance to determine the received amplitudes of any given transmission. The first part of a valid transmission is, therefore, a fixed number sequence that the neural net uses to establish relative magnitudes. This sequence alternates in continuous fashion with the address of the device the unit is trying to communicate with. In the first string, therefore, the NNP 18 looks to match the pattern category of the fixed string. From the values it finds for this string it assigns the numeric value of any one received amplitude. It then immediately examines the address information. If it finds its own address, it sends an acknowledgment and prepares for reception. Otherwise, it ends the lock-in process and resumes its normal sweep.

At some point after it finds a signal, the NNP 18 relaxes to an optimal value for all the parameters governing the lock- in detector. At this point the system is locked. The NNP 18 continues to examine the received signal for evidence of drifts and degradation, and continues to adjust the parameters. In this phase, it adjusts them in an asynchronous, opportunistic way. In other words, it does not sweep parameters or change them in some sequential fashion. Rather, it alters each using methods it learns during operation.

To transmit, the NNP 18 receives a Ready- to Send signal from the host. At this point, there are two possible actions.

If the device is in an existing communications session, the NNP 18 waits for the end of the current received data packet, then sends the outgoing data packet. If the device is to initiate a session, the NNP 18 immediately halts its searching for signals. It then sends as output to the synchronous multiplier the fixed number string (hardwired in ROM) and the address of the unit it is trying to reach. It repeats this signal until it receives an acknowledgment from the target unit or until a user-specified time-out period elapses. If it receives an acknowledgment, it begins normal transmission. Otherwise it aborts and resumes its normal sweep.

There is a possibility that the NNP 18 receives a packet it cannot reconstruct. If this happens, the NNP 18 sends a request to the sending unit to retransmit. The user can specify a drop rate to end transmission, and the NNP 18 also internally defines a drop rate indicating a high probability of a lost connection. Eventually, the transmission ends. The NNP 18 receives an End of Transmission signal from the target unit, and stops transmitting. It resumes its search for signals and the state cycle starts again from the no signal state.

Two neural structures in the NNP 18 are new. These are the predictor and the will generator. A predictor is not a new neural process. The specific implementation of this predictor is new, however. A predictor is a process that computes the probability of input vector X_t+n, corresponding to stored memory A based on the stored memory B that input vector _t corresponds to. Figure 10 is a diagram of the predictor. Neurons i-d,., are the delay loop. These neurons establish how far forward in time the predictor predicts. Input X_A is the real input vector for time t+n. Input X_A is the real input vector for time t+n. Input X_B is the real input vector for time t. Neuron R∞ forms the term f(S^) where f is the transfer function, Sj_, = ∑_i:j T X_A + T_Bj X_B. Connections Ts each are sensitive to a particular value of S_M. If a T_s connection is active, neuron X^ fires. The signal down synapse T_M increments that synapse's weight. In time, the weights of synapses T^ match the probability that input X_t+n will have value A if input X_t has value B. Neuron P_x has a transfer function with threshold above one input, to prevent spurious output during sampling. A neuron with this transfer function permits continuous unsupervised training. Input I is the command neuron. When I is active, the predictor makes its prediction. The value of I determines which output value the predictor returns a probability on. Note that such a unit is therefore not confined to predicting the most probable outcome but instead can assess the likelihood of any given output. The will generator is an entirely new element with an input vector X_Ϊ to process proportional to the difference between X, which arises from internally produced spontaneous random signals. This aspect of the present invention is shown in Figure 6. The output from a neuron _τ arises from output forward to synapses I_n, of which, at one moment, only one of the neurons X_τ is active. The X_τ neurons form the input layer to a process P. For simplicity Figure 6 shows only one output neuron from P but there may be more than one. Output neuron p_τ computes the difference between the output of P and p_j. The p_ memory does not come from P itself. It is, however, related to favorable outcomes from P. The P_dummy is a delay loop to synchronize the X_r with the p_τ . The synapses T_pI each respond to a particular value of pj. The neurons have a transfer function biased to remove the T_pI contribution to the output. If neuron X_τ, fires, it stores its value in inhibitory synapse T_j.. The neurons X_τ now have an inhibition proportional to the difference between the output of P and the p_ memory. Consequently, they have an activation probability inversely proportional to that difference. The will generator causes more favorable outputs to occur with higher probability.

Both of these devices require a synapse that will respond only to certain signals. The synapse the NNP 18 uses is an integrator with reset acting as a frequency-to-voltage converter. As long as the amplitude of an incoming signal is approximately constant, the output voltage of such a device is proportional to the frequency. The axon into the synapse encodes analog data as a frequency. To make the synapse respond only to certain signals, a filter is placed in front of the integrator. The precision and cutoff of the filter need not usually be great, especially in an analog neural net where ultimate precisions are relatively low. As a result, a simple RC passive filter suffices for most applications. It is possible to use an active gyrator filter in situations requiring higher filter precisions. The gyrator filter is the filter of choice because of its low sensitivity to component variations. On a VLSI chip, component tolerances are often large and it is best to avoid the associated problems. A capacitor stores the weight for the synapse while the processor has power. To maintain synaptic weights when the chip is powered down, the chip has an EEPROM floating-gate array on board to store synaptic values. In addition to the following claims, the foregoing specification also describes other inventions in sufficient detail for understanding by those skilled in the relevant arts. For example, the foregoing description describes a method of using a neural net processor to search, detect and extract the data from the radio signal with noise reduction. It also describes control of lock-in synchronous detection by a neural net processor (at any frequency) , using a neural net processor to provide the synchronous signals that lock-in detection requires. The neural net enhances the received signal internally. The foregoing further describes a system that is compatible with long distance low-power high-speed wireless communications, by describing a neural net for the transmission and reception of a radio signal in a self- contained module. The radio signal shall be low power (less than 250 mW) , high-speed (greater than 10 Mb/s) and long range (greater than 100 mile range) . Also, the foregoing describes in sufficient detail the use of a neural net processor for simultaneous pattern recognition and control through the simultaneous recognition of patterns, followed by control of a pattern recognition and control system based on those patterns.

Also, the foregoing detailed description can support an application of neural nets to incompletely defined systems, wherein the neural net involves multiple variable problems that are too complex to find a definite answer for using traditional computational methods, by means of specialized neural agents having a dedicated neural control agent assigning tasks. The concept of lock-in detection described in the foregoing specification scan be used in applications to data networking over wireless data network transmissions. The system described in the foregoing can also be used for wireless transmission and reception via the ATM (Asynchronous Transfer Mode) standard for computer data network communication, and the use of power radio frequency (RF) modulation to produce synchronous AM systems wherein the transmitter emits a single frequency, phase polarized radio signal, having an output power which varies on a cycle-by cycle basis to send digital information.

Further, the neural net described can be realized by means of vector transistors (i.e., a neuron circuit with a quantum series of transfer functions dependent on input magnitude and direction of signal) . The neural circuit can include synapse circuits with weightings biased by dendrite line feedback, where the synapse circuit acts as a preprocessor to the neurons and can respond to all signals or to specific signals. The synapse circuit converts frequency encoded data to voltage encoded data. Its weightings compensate for different line lengths. Separation of the neural net into distinct functional modules can allow a single neural net processor to use multiple neural topologies, permitting greater specialization of processing and improvement in performance.

The VFU descried above can be used to internally determine operation of the entire neural net, since the VFU can be regarded as a separate neural net control unit. Further, the VFU can be separated into two distinct parts - a command generator and a operations monitor. The command generator executes instructions and the operation monitor controls execution, as will be understood by those skilled in the art of neural net design. Using multiple variable in the VFU to determine reinforcement or suppression can serve to aid the performance of the rest of the neural net by strengthening or diminishing signals, as is appropriate. The capability of the VFU to issue commands in the absence of input data is based on the VFU use of random noise to continue the processing where no other input data are available. A processor based on a neural net can consist of several units to carry out different processes, such as multiple inference topologies. This factor increases parallelism and improves performance of the neural net.

Another approach to use of the neural net processor described in the foregoing concerns having an I/O unit configured as a neural net with a buffer and internal routing by chaotic stability analysis, in which an off-chip input is directed to the I/O power of the neural net and is then analyzed for chaotic stability, which allows the data to be directed to the most effective specialized neural unit within the neural net. The neural net processor in the foregoing can also be used with feedback over multiple layers (i.e., greater than first-order feedback) , to any arbitrary layer in the network.

According to a second embodiment of the apparatus 10, the NNP is a Nestor NI1000 neural net processor. This processor is adequate in cases where the signal input statistic does not change too rapidly with time. It is also usable under similar conditions as the first neural net described above in cases where the received SNR is somewhat better or where the data rate is lower. With reference to the range, speed, and power targets described earlier, the radio signal shall be low power (less than 1 W) , high-speed (greater than 1 Mb/s) and long range (greater than 5 mile range) . Also, the foregoing describes a system that is capable of data transmission and reception over a variety of distances, data rates, and power outputs.

The NI1000 is a CMOS processor with an I/O bus width of 64 bits. In a single burst clock cycle the NI1000 can output 8 class identifications or accept as input 8 feature vectors.

In the present embodiment, each 64-bit word is a long feature vector or long class ID where each 8-bit feature vector or class ID within the word corresponds to a specific control line or I/O data element.

Figures 7a-d are diagrams showing each of the of the vector alignments for the four possible I/O states of the neural net processor. Figure 7a is a diagram of the vector alignment for the I^ state. Figure 7b is a diagram of the vector alignment for the I_ia state. Figure 7c is a diagram of the vector alignment for the O_o,.,- state. Figure 7d is a diagram of the vector alignment for the O_in state. Bytes 0 and 1 are the data, bytes 2 and 3 are the frequency value ω, byte 4 is the phase φ, byte 5 is the requency multiple A, byte 6 is the feedback resistance in the phase detector R, and byte 7 is the buffer gain G for the data ADC.

The training process for the NNP 118 proceeds in 2 distinct phases. In the fist phase, 2 humans operate the entire apparatus 10 without the NNP 118. They input the control values and data identifications from a series of standard data sets into a data logger, forming a training data set. This data set is then used as a first training set for the NNP 118. Once the NNP achieves an acceptably high rate of classification performance, training moves to the second phase.

In the second phase, the NNP 118 is inserted into apparatus 10 and the entire apparatus is operated using a different series of standard data sets from those used in the first phase. The only training information the NNP 118 receives is the correct identification of the data element in any one training pass. Phase 2 ends when the NNP 118 achieves a rate of classification suf iciently high to permit the entire apparatus 10 to achieve the specified data rate required and thus be suitable for field use.

The 2-phase training process has several advantages. It permits the NNP 118 to achieve a reasonably good level of classification performance quickly, avoiding the necessity of a great many training passes. It minimizes the probability of overgeneralization due to early incorrect classifications arising from spurious data. It permits fine-tuning to occur in a real environment and therefore catch any discrepancies between real operational conditions and the (necessarily artificial) first training set that may lead to error. It gives a higher weight to ultimate correct identification of the data rather than absolute best tuning of control parameters, thus preventing excessive commitment of internal prototypes to control parameters. Finally, it allows site-to- site training flexibility in the final unit. The NNP 118 can fine-tune itself to adapt to different environmental conditions between sites. The fact of the NI1000 having CMOS output levels necessitates some changes to the I/O structure of the apparatus 10. Fig. 8 is a diagram showing a second preferred embodiment of the invention, which is a revision of the apparatus 10. When components are unchanged from the way they are shown in Figure 1, they are given the same reference number as Figure 1. Essentially, the NNP 118 is now in the digital portion of the apparatus 10' and all I/O to the rest of the device is through the ADC 28 and the DAC 26. In addition, the data I/O lines pass through a multiplexer 120 that allows both input and output to pass over the same lines (such as a bus 64) from the multiplexer 120 to the NNP 118. Euch control line uses an AD9002 ADC 28 (augmented with an ECL driver 124 and the optoisolator 32) connected to the multiplexer 120 through a line 125 as an interface and the data lines 31', 36, 70, 76, 80, 84 and 122 use an AD9768 DAC 26 (augmented with the optoisolator 30 and an ECL driver 126) , connected to the multiplexer 120 through the line 128, for output. The optoisolators 30 and 32 and the ECL drivers 124 and 126 are used because both the ADC 28 and the DAC 26 use ECL logic levels, and the optoisolators and ECL drivers constitute a logic level converter that changes the CMOS logic levels to ECL logic levels.

While the foregoing is a detailed description of the preferred embodiment of the invention, there are many alternative ^"embodiments of the invention that would occur to those skilled in the art and which are within the scope of the present invention. Accordingly, the present invention is to be determined by the following claims.

Claims

1. An apparatus for detection of a particular electromagnetic signal included among other electromagnetic signals, comprising: a detector to receive all of the electromagnetic signals and a detector control signal and to produce a detected signal in response thereto, the detected signal having first and second states respectively indicating that the apparatus has and has not detected the particular electromagnetic signal; and a neural net processor to receive the detected signal and to produce the detector control signal in response thereto, the detector control signal being fed back to the detector.

2. The apparatus of claim 1, wherein the neural net processor includes a neural execution circuit and a neural control circuit, the neural execution circuit receiving the detector signal and an execution control signal and producing a neural control signal and a processed signal in response thereto, and the neural control circuit receiving the processed signal and producing the execution control signal in response thereto.

3. The apparatus of claim 2, wherein the neural control circuit includes a control execution circuit and a control control circuit, the control execution means being adapted to receive a control execution control signal and to produce the neural control signal in response thereto, and the control control circuit being adapted to receive a processed signal and to produce a control execution control signal in response thereto.

4. The apparatus of claim 2, wherein the neural execution circuit includes a plurality of individual neural execution unit circuits, each individual neural execution unit producing

5 a processed signal to be received by the neural control circuit.

5. The apparatus of claim 1, wherein the neural net processor includes a synchronization circuit to receive the

10 electromagnetic signals and to produce a synchronization signal in response thereto, the synchronization signal being transmitted to the detector to synchronize the detector and the neural net processor.

15 6. The apparatus of claim 1, wherein the detector includes a plurality of active integrating circuits to receive the control signal and to process the particular electromagnetic signal and to process the other electromagnetic signals.

20 7. A method for detecting a particular electromagnetic signal included among other electromagnetic signals, comprising the steps of: a) receiving all of the electromagnetic signals and a detector control signal and producing a detected signal in

25 response thereto, the detected signal having first and second states respectively indicating that the apparatus has and has not detected the particular electromagnetic signal; and b) transmitting the detected signal; c) receiving the detected signal and producing the '30 detector control signal in response thereto; d) transmitting the control signal; and e) causing the detector control signal to be received.

8. The method of claim 7, further comprising the steps of: f) receiving the detected signal and an execution control signal and producing a neural control signal and a processed signal in response thereto; and g) receiving the processed signal and producing the execution control signal in response thereto.

9. The method of claim 8, further comprising the steps of: f) producing a plurality of individual processed signals; and g) transmitting the plurality of individual processed i/

10. The method of claim 7, further comprising the steps of: f) receiving the control signal and all of the electromagnetic signals and to produce a synchronization signal in response thereto; and g) transmitting the synchronization signal.

11. The method of claim 7, further comprising the steps of: f) receiving the control signal and processing the particular electromagnetic signal in response thereto; and g) receiving the control signal and processing the other electromagnetic signals in response thereto.

12. An apparatus for detection of a particular electromagnetic signal included among other electromagnetic signals, comprising: detector means for receiving all of the electromagnetic signals and a detector control signal and to producing a detected signal in response thereto, the detected signal having first and second states respectively indicating that the apparatus has and has not detected the particular electromagnetic signal; and neural net processor means for receiving the detected signal and producing the detector control signal in response thereto, the detector control signal being fed back to the detector.

13. The apparatus of claim 12, wherein the neural net processor means includes a neural execution circuit means and a neural control circuit means, the neural execution circuit means receiving the detector signal and an execution control signal and producing a neural control signal and a processed signal in response thereto, and the neural control circuit means receiving the processed signal and producing the execution control signal in response thereto.

14. The apparatus of claim 13, wherein the neural execution circuit means includes a plurality of individual neural execution unit circuits, each individual neural execution unit for producing a processed signal to be received by the neural control circuit.

15. The apparatus of claim 13, wherein the neural control circuit means includes a control execution circuit means and a control control circuit means, the control execution means receiving a control execution control signal and producing the neural control signal in response thereto, and the control control circuit means receiving a processed signal and producing a control execution control signal in response thereto.

16. The apparatus of claim 12, wherein the neural net processor means includes a synchronization circuit for receiving the electromagnetic signals and to produce a synchronization signal in response thereto, the synchronization signal being transmitted to the detector to synchronize the detector and the neural net processor.

17. The apparatus of claim 12, wherein the detector includes a plurality of active integrating circuits for receiving the control signal and processing the particular electromagnetic signal and for processing the other electromagnetic signals.

18. An apparatus to transmit the particular electromagnetic signal of claim 1, comprising:

A transmitter to receive a particular electromagnetic signal and an information-carrying signal and to produce a transmitted signal in response thereto; and a neural net processor to receive the information-carrying signal and to synchronize the signal with a particular electromagnetic signal, both signals being fed into the transmitter.

19. The apparatus of claim 18, wherein the transmitter includes a multiplication circuit to receive the particular electromagnetic signal and the information-carrying signal and to multiply the one by the other.

20. A method for transmitting a particular electromagnetic signal comprising the steps of: a) receiving a particular information-carrying signal and producing a particular electromagnetic signal synchronized with the information-carrying signal in response thereto; b) multiplying the information-carrying signal by the particular electromagnetic signal, producing a signal to be transmitted; and c) transmitting the signal to be transmitted.

21. An apparatus for the transmission of a particular electromagnetic signal, comprising: transmitter means for receiving a particular electromagnetic signal and an information-carrying signal and producing a transmitted signal in response thereto; and neural net processor means for receiving the information- carrying signal and synchronizing the signal with a particular electromagnetic signal, both signals being fed into the transmitter.

22. The apparatus of claim 21, wherein the transmitter means includes a multiplication circuit means for receiving the particular electromagnetic signal and the information- carrying signal and multiplying the one by the other.

23. An apparatus to produce an electromagnetic signal falling into a particular power range, comprising:

A transmitter to receive a particular electromagnetic signal and a control signal and to produce a transmitted signal in response thereto; and a neural net processor to receive the particular electromagnetic signal and to synchronize the signal with a control signal, both signals being fed into the transmitter.

24. The apparatus of claim 23, wherein the transmitter includes a multiplication circuit to receive the particular electromagnetic signal and the control signal and to multiply the one by the other.

25. A method for transmitting an electromagnetic signal falling into a particular power range comprising the steps of: a) receiving a particular electromagnetic signal and producing a control signal synchronized with the particular electromagnetic signal in response thereto; b) multiplying the control signal by the particular electromagnetic signal, producing a signal to be transmitted; and c) transmitting the signal to be transmitted.

26. An apparatus to produce an electromagnetic signal falling into a particular power range, comprising: transmitter means for receiving a particular electromagnetic signal and a control signal and producing a transmitted signal in response thereto; and neural net processor means for receiving the particular electromagnetic signal and synchronizing the signal with a control signal, both signals being fed into the transmitter.

27. The apparatus of claim 26, wherein the transmitter means includes a multiplication circuit means for receiving the particular electromagnetic signal and the control signal and multipling the one by the other.