WO1996041271A1

WO1996041271A1 - Programmable bus arbiter including real time priority indicator fields for arbitration priority selection

Info

Publication number: WO1996041271A1
Application number: PCT/US1996/009756
Authority: WO
Inventors: Dale Gulick; Andy Lambrecht; Mike Webb; Larry Hewitt; Brian Barnes
Original assignee: Advanced Micro Devices, Inc.
Priority date: 1995-06-07
Filing date: 1996-06-07
Publication date: 1996-12-19

Abstract

A programmable bus arbiter is provided that includes a plurality of arbitration priority registers each having a real time field for arbitration priority selection. Each real time bus master is associated with a designated real time field within the bus arbiter. Each real time field includes a real time access bit indicative of whether a real time access is to be initiated by the associated master and a priority code which sets the arbitration priority for the master with respect to other masters which may contend for the bus. Prior to initiating a real time data transfer, the real time field for a particular master may be programmed to indicate the real time transfer as well as to set the priority level for the request. A bus arbitration state machine detects the real time fields and grants bus mastership to real time bus agents in favor of other contending bus requests by non-real time agents.

Description

TITLE: PROGRAMMABLE BUS ARBITER INCLUDING REAL

TIME PRIORITY INDICATOR FIELDS FOR ARBITRATION PRIORITY SELECTION

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to bus arbitration within computer systems and, more particularly, to a computer system having an improved bus arbiter for arbitrating bus accesses of a CPU, real time DSP hardware, and other system resources.

Description of the Relevant Art

Computer architectures generally include a plurality of devices interconnected by one or more buses. For example, conventional computer systems typically include a CPU coupled through bridge logic to a main memory. The bridge logic also typically couples to a high bandwidth local expansion bus, such as the Peripheral Component Interconnect (PCI) bus or the VESA (Video Electronics Standards Association) VL bus. Modern local bus standards such as the PCI bus and the VL bus are not constrained by a requirement to be backwards compatible with prior expansion bus adapters and thus provide much higher throughput than older expansion buses. Examples of devices which can be coupled to local expansion buses include SCSI adapters, network interface cards, video accelerators, audio cards, telephony cards, etc. An older-style expansion bus may also be coupled to the local expansion bus to provide compatibility with earlier-version expansion bus adapters. Examples of such expansion buses include the industry standard architecture (ISA) bus, also referred to as the AT bus, the extended industry standard architecture (EISA) bus, and the microchannel architecture (MCA) bus. Various devices may be coupled to this second expansion bus, including a fax/modem, sound card, etc.

A CPU local bus arbiter as well as a PCI bus arbiter are typically included as part of the bridge logic in many computer systems. The CPU local bus arbiter determines and prioritizes ownership of the CPU local bus, while the PCI bus arbiter determines and prioritizes ownership of the PCI bus. Mastership of either bus is typically based on a fixed arbitration fairness scheme, such as a round-robin algorithm. In some situations, a master must acquire ownership of both the PCI bus and the CPU local bus before it can proceed with a particular transfer cycle.

Computer systems were originally developed for business applications including word processing and spreadsheets, among others. Recently, computer systems have evolved toward more real time applications, including multimedia applications such as video and audio, video capture and playback, telephony, and speech recognition. Computer systems originally designed for business applications, however, are not well suited for the real time requirements of modern multimedia applications for a variety of reasons. For example, current operating systems for personal computers are not real time operating systems. In addition, the bus architecture of modern personal computer systems still presumes that the majority of applications executing on the computer system are non-real time, business applications such as word processing and/or spreadsheets which are executed solely by the main CPU.

A significant problem associated with modern computer systems is that the bus arbiter which arbitrates between real time resources, non-real time resources and the CPU is typically designed to provide the CPU with maximum availability to the system memory, or is otherwise not cognizant of the real time accesses of other bus mastering devices. Real time devices can accordingly be "starved" for memory access, particularly when a relatively large number of real time devices are included within the system. This can correspondingly result in degraded performance, unsynchronized audio and video, and the dropping of frames during video or animation sequences. Therefore, a new bus arbiter system and method are desirable which provide greater access to the bus subsystems and main memory for real time devices to thus better facilitate real time applications.

SUMMARY OF THE INVENTION

The problems outlined above are in large part solved by a programmable bus arbiter in accordance with the present invention. In one embodiment, a programmable bus arbiter is provided that includes a plurality of arbitration priority registers each having a real time field for arbitration priority selection. Each real time bus master is associated with a designated real time field within the bus arbiter. Each real time field includes a real time access bit indicative of whether a real time access is to be initiated by the associated master and a priority code which sets the arbitration priority for the master with respect to other masters which may contend for the bus. Prior to initiating a real time data transfer, the real time field for a particular master may be programmed to indicate the real time transfer as well as to set the priority level for the request. A bus arbitration state machine detects the real time fields and grants bus mastership to real time bus agents in favor of other contending bus requests by non-real time agents. In one implementation, the bus arbiter is incorporated within a bus bridge coupled between a CPU local bus and a PCI bus. The bus arbiter prioritizes and controls ownership of the PCI bus. The bus bridge may further include memory controller logic for controlling data transfers between a main memory and masters residing on either the CPU local bus or the PCI bus. A variety of peripheral devices are coupled to the PCI bus, including both real time resources and non-real time resources. For example, in one configuration a SCSI controller, a network interface card, a video adapter, a video capture card, an audio adapter, and a telephony adapter are coupled to the PCI bus. The system is capable of supporting numerous real time processing resources while maintaining proper overall operation.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which:

Figure 1 is a block diagram of a computer system including a variety of real time resources and a bus arbiter in accordance with the present invention. Figure 2 is a block diagram which depicts internal portions of the bus arbiter of Figure 1.

Figure 3 is a diagram which illustrates the real time priority indicator fields associated with the bus arbiter of Figure 2.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.

DETAILED DESCRIPTION OF THE INVENTION

Referring now to Figure 1, a block diagram of a computer system incorporating a plurality of real time bus devices and bus arbitration logic in accordance with the present invention is shown. As illustrated in the figure, the computer system includes a central processing unit (CPU) 102 which is coupled through a CPU local bus 104 to a host/PCI/cache bridge 106. The bridge 106 includes memory control logic and is coupled through a memory bus 108 to a main memory 110. A cache memory subsystem (not shown) may further be coupled to bus bridge 106.

Bus bridge 106 also interfaces to a peripheral component interconnect (PCI) bus 120. Further details regarding PCI bus 120 may be found within the publication "PCI Local Bus Specification"; Revision 2.0; April 30, 1993; PCI Special Interest Group; Hillsboro, Oregon. This publication is incorporated herein by reference in its entirety. It is noted that other local buses could be alternatively employed, such as the VESA (Video Electronics Standards Association) VL bus.

CPU 102 is illustrative of, for example, an x86 microprocessor such as an 80486 microprocessor or a Pentium-compatible microprocessor. It is understood, however, that a system according to the present invention may employ other types of microprocessors. It is further understood that the present invention may be employed within a multiprocessing environment.

Various types of devices may be connected to the PCI bus 120. For the embodiment illustrated in Figure 1, a video adapter 170 for controlling video functions is coupled to PCI bus 120. Other real time DSP devices are also preferably coupled to the PCI bus, including an audio adapter 172, a telephony adapter 174, and a video capture board 176, among others. A SCSI (small computer systems interface) disk controller 122 and a network interface card 140 are additionally shown coupled to the PCI bus 120. SCSI controller 122 is configured to provide an interface to SCSI devices such as a CD-ROM device, a tape drive device, and/or a composite disk array. The network interface card 140 interfaces to a local area network (LAN) 142. An expansion bus bridge 150 is also preferably coupled to the PCI bus 120. The expansion bus bridge 150 interfaces to an expansion bus 152. The expansion bus 152 may be any of a variety of types, including the industry standard architecture (ISA) bus, also referred to as the AT bus, the extended industry standard architecture (EISA) bus, or the microchannel architecture (MCA) bus. Various devices may be coupled to the expansion bus 152, including expansion bus memory 154 and a modem 156.

A bus arbiter 180 configured to control ownership of PCI bus 120 is illustrated as a portion of bus bridge 106 . As will be explained in further detail below, the arbitration scheme employed by the computer system of Figure 1 provides a unique request signal REQ# and grant signal GNT# for each PCI master. When a particular master requires ownership of PCI bus 120, it asserts its associated request signal REQ#. In accordance with the invention, bus arbiter 180 is configured to allow selected bus request channels to be programmed as real time bus requests. Real time bus requests are given a higher priority for bus access in comparison to non-real time bus requests. The bus arbiter 180 may further be programmed to provide differing priority levels for different real time masters. In accordance with the arbitration mechanism provided by bus arbiter 180, non-real time masters will lose an arbitration for PCI bus 120 to real time masters. Further details regarding bus arbiter 180 will be provided further below in conjunction with Figures 2 and 3.

As stated above, each bus master of Figure 1 asserts a unique request signal REQ# when bus access is desired. These request signals (shown collectively as REQ[7:0]) are routed to bus arbiter 180. For example, request signal REQ2 is generated by video adapter 170, and request signal REQ5 is generated by telephony adapter 174. Corresponding grant signals GNT[7:0] are similarly routed back to the masters from bus arbiter 180 to indicate the current owner of PCI bus 120. It is noted that request signal REQ4 may be asserted by expansion bus bridge 150 if access of PCI bus 120 is required by an agent of expansion bus 152, such as modem 156. It is further noted that each request signal/grant signal pair is referred to as a bus request channel.

Figure 2 is a diagram that depicts internal portions of bus arbiter 180. As shown, bus arbiter 180 includes an arbitration state machine 202 coupled to a request detection unit 204, a grant generator 208 and programmable arbitration priority registers 210. A decoder 212 is additionally shown coupled to programmable arbitration priority registers 210.

Programmable arbitration priority registers 210 are provided to allow a particular bus request channel to be designated as a real time channel. Programmable arbitration priority registers 210 are further provided to set the arbitration priority associated with the processing of real time bus requests by arbitration state machine 202. Figure 3 is a diagram that illustrates a plurality of real time fields 300 included within the programmable arbitration priority registers 210. Each real time field 300 includes a real time access bit and a priority code. Decoder 212 is provided to allow software programming of each real time field 300. It is noted that in this implementation, a separate real time field 300 is provided for (i.e., is associated with) each request signal REQ[7:0]. The real time access bit associated with a particular request signal REQ# may be cleared if the master corresponding to the request signal REQ# is going to initiate a non-real time data transfer, and may be set if the master is going to perform a real time data transfer. The priority code may further be set to select the arbitration priority level to be associated with a particular master.

Arbitration state machine 202 is configured to transition between several bus arbitration states depending upon assertions of the bus request signals REQ[7:0] detected by request detection unit 204 . Transitions between the various arbitration states of arbitration state machine 202 are further dependent upon values stored within the real time fields 300. In one implementation, arbitration state machine 202 is configured to provide the lowest level of arbitration priority to any request signals REQ# which do not have an associated real time access bit set. Thus, any contending request signal REQ# having an associated real time access bit set will gain access to the bus in favor of any non-real time requests. In one embodiment, contending non-real time requests are handled by state machine 202 in a round-robin fashion.

The priority code associated with a particular real time priority indicator field sets the priority for contending real time requests. Priority code "00" is given the lowest priority, while priority code "11" is given the highest priority. For example, for the particular programmed configuration illustrated in Figure 3, a contending request by the master asserting the request signal REQ6 will win over a contending request of any of the other masters. Similarly, a bus request by the master asserting request signal REQ1 will win over a bus request of the master asserting request signal REQ4, but will lose to a contending request by the master asserting request signal REQ5. If the same priority code is given to more than one contending request signal REQ#, such contending bus requests are treated in a round-robin manner after any higher priority real time requests have been serviced.

The operation of the bus arbiter 180 as described above ensures that real time requests are serviced expeditiously. Accordingly, a relatively large number of real time devices may be employed within the computer system while maintaining proper overall operation. The system further allows differentiation in bus arbitration priorities for differing bus masters, as desired.

It is noted that the above-described system further allows bus requests of a particular bus agent to be designated at one time during the operation as a non-real time master and at other times of operation as a real time master. For example, consider a situation where request signal REQ7 is associated with requests invoked by bridge 106 in response to cycles initiated by CPU 102. Prior to initiating a transfer of data to a disk drive managed by SCSI controller 122, the system programmer may cause the real time access bit associated with request signal REQ7 to be cleared, thus indicating a non-real time data transfer. If at a later time during the operation of the computer system the CPU 102 is to initiate a sequence of real time data transfers to, for example, audio adapter 172, the system programmer can cause the real time access bit associated with request signal REQ7 to be set, and additionally cause a predetermined priority code to be associated with request signal REQ7. In accordance with this operation, arbitration state machine 202 provides a higher priority to the subsequent real time transfers in comparison to that provided for the earlier non-real time transfer. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.

Claims

WHAT IS CLAIMED IS:

1. A bus arbiter for controlling and prioritizing ownership of a bus comprising:

a request detection unit for detecting a plurality of bus request signals corresponding to designated bus masters;

a grant generator for generating a plurality of bus grant signals;

an arbitration state machine coupled said request detection unit and to said grant generator, wherein said arbitration state machine processes contending bus requests received by said request detection unit; and

a programmable storage unit coupled to said arbitration state machine, wherein said programmable storage unit is configured to store a plurality of real time access bits, wherein each real time access bit is associated with a different request signal received by said request detection unit and indicates whether a particular request corresponds to a real time data transfer, and wherein said arbitration state machine is configured to provide a higher priority for bus ownership to bus request signals associated with a real time data transfer.

2. The bus arbiter as recited in claim 1 wherein said programmable storage unit includes a plurality of registers.

3. The bus arbiter as recited in claim 1 further comprising a decoder coupled to said programmable storage unit, wherein said decoder is configured to decode an address signal to thereby allow a setting of a predetermined real time access bit within said programmable storage unit.

4. A computer system comprising:

a microprocessor;

a bus bridge coupled to said microprocessor through a CPU local bus;

an expansion bus coupled to said bus bridge, wherein said bus bridge is configured to accommodate data transfers between said CPU local bus and said expansion bus;

a real time master coupled to said expansion bus, wherein said real time master is configured to perform real time processing functions;

a non-real time master coupled to said expansion bus, wherein said non-real time master is configured to perform non-real time processing functions; and a bus arbiter coupled to said expansion bus, wherein said bus arbiter includes a programmable storage unit including a plurality of real time priority indicator fields, wherein a first real time priority indicator field is associated with said real time master and is configured to store a real time access bit, and wherein said bus arbiter is configured to grant mastership of said expansion bus to said real time master in favor of a contending request by said non-real time master if said real time access bit is set.

5. The computer system as recited in claim 4, wherein said non-real time master is configured to assert a first request signal to request ownership of said expansion bus and wherein said real time master is configured to assert a second request signal to request ownership of said expansion bus.

6. The computer system as recited in claim 4 wherein said expansion bus is a PCI bus.

7. The computer system as recited in claim 4 wherein said real time master is an audio adapter.