WO1996037950A1 - Channel coupled feedback circuits - Google Patents

Abstract

Channel coupled feedback technology for implementing many analog and digital signal processing functions in a single-polysilicon digital IC fabrication process is described. Field effect transistors are constructed having a common channel and the substrate regions of the field effect transistors in the channel are electronically connected. Thus, a fixed amount of charge can freely move within the channel in response to the application of the signal to be processed. By sensing the charge transferred within the channel when the input signal is applied, many signal processing functions are possible. Fixed-gain amplifiers, offset compensated amplifiers, integrators, differentiators, analog-to-digital converters, digital-to-analog converters, switchable gain amplifiers, automatic gain control systems, and linear transform computation circuits are constructed entirely with field effect transistors, eliminating the need for passive components for most signal processing functions.

Description

DESCRIPTION

CHA NEL COUPLED FEEDBACK CIRCUITS

Field of the Invention

The present invention relates to electronic circuits. Specifically, the present invention relates to amplifiers that have channel coupled feedback circuits to perform signal processing functions.

Background

Feedback is an important aspect of many signal pro¬ cessing circuits. In control systems, feedback consists of comparing the actual output of the system with the desired output and making corrections accordingly. In fixed gain amplifier circuits, the output voltage of the amplifier should be a multiple of the input voltage. Therefore, in a feedback amplifier, the input voltage is compared with an attenuated version of the output voltage. Negative feedback is the process of coupling the output voltage of an amplifier back in such a way as to cancel some of the input voltage. While negative feedback lowers the gain of the amplifier, it serves to improve other characteristics of the amplifier, such as freedom from distortion and non-linearity, flatness of response and predictability. In fact, as more negative feedback is used, the resultant amplifier characteristics become less dependent upon the characteristics of the open-loop (no- feedback) amplifier and finally depend only upon the properties of the feedback network itself. See generally, Horowitz and Hill, The Art of Electronics. Cambridge University Press (2nd Ed. 1989), pp. 175-250.

Traditionally, feedback and analog signal processing functions have been designed using passive components, such as resistors or capacitors. For example, Figure 2 shows a conventional inverting, fixed-gain amplifier circuit having a resistor (9) in the feedback loop. Based upon the facts that (a) the amplifier (10) adjusts its output so as to make the voltage difference between its inputs equals zero and (b) the inputs of the amplifier draw virtually no current, the following relationship is evident:

By rearranging this equation, the voltage gain of the amplifier (V_out/V_in) is equal to the ratio of the two resistors (-R-_j/R . Therefore, one can change the gain of an inverting, fixed-gain amplifier by altering the resis¬ tivity of the feedback resistors. See Horowitz and Hill, pp. 177-178.

The inverting amplifier shown in Figure 2 is a useful device for analog signal processing. An analog system carries signals in the form of voltages, currents, charg¬ es, etc., that are continuous functions of a continuous time variable. Some typical examples of analog signal processors are audio amplifiers and telecommunications systems. By contrast, in a digital system each signal is represented by a sequence of numbers or discrete values. A typical example of a digital system is a microprocessor in which the computations are done in terms of "Is" and "0s" .

Prior to the mid-1970s, analog signal processing systems were not widely implemented using monolithic integrated circuit (IC) technology, particularly metal- oxide semiconductor (MOS) technology, primarily because most analog signal processing circuits require precise passive components, such as resistors and capacitors. Monolithically fabricating an absolute precision resistor or capacitor is still difficult given the capability of current IC fabrication technology.

However, in the late 1970s and thereafter, a design technique known as switched capacitor circuits emerged. Using this design technique, the combination of a capaci¬ tor and a few transistor switches can functionally replace a resistor. Figure 3 shows a switched capacitor circuit that is equivalent in function to the inverting, fixed- gain amplifier of Figure 2. By properly choosing the size of the capacitors (14) and (16) and the transistor switch clocking scheme (12) , (13) and (15) , the need for mono- lithic resistors in IC design can be eliminated. See generally, Gregorian and Temes, Analog MOS Integrated Circuits, John Wiley & Sons (1986) ; Allen and Holberg, CMOS Analog Circuit Design. Holt, Rinehart & Winston (1987) . Several advantages are inherent to the use of switched capacitor circuit designs. First, monolithic resistors require an inordinately large area of the IC. The capacitor and switches that replace the resistor may require less than 1% of the area that the equivalent resistor would require. Thus, the use of switched capaci¬ tors in place of resistors generally serves to reduce the size of the IC necessary for a given signal processing function.

Second, the accuracy of switched capacitor circuits relies primarily upon the ratios of monolithic capacitors, rather than the precision of each capacitor individually. The matching of two identical capacitors within the same die area of most MOS ICs can be highly accurate and can be in the range of 0.1 - 1%. Therefore, the accuracy of analog processing circuits using switched capacitors can be improved over circuits using monolithic resistors.

While the use of monolithic capacitors has permitted the design of many monolithic analog signal processing systems, the use of monolithic capacitors is not without disadvantages. Monolithic capacitors generally can be classified into either of two types depending upon the host material for the thermally grown silicon dioxide dielectric layer: (1) capacitors formed on heavily doped crystalline silicon (Figure 4) or (2) capacitors formed on poly-crystalline silicon (polysilicon) (Figure 5) . Conventional switched capacitor circuits are currently fabricated in special complementary metal-oxide semicon- ductor (CMOS) fabrication processes that have special fabrication steps required to implement accurate capaci¬ tors. For further instruction on designing monolithic analog processing circuits using monolithic passive components, see Allstot and Black, Technological Design Considerations for Monolithic MOS Switched-Capacitor Filtering Systems. Proceedings of the IEEE, Vol. 71, No. 8, pp. 967-986 (1983) .

The capacitor shown in Figure 4 is manufactured by growing a thin oxide over the top of the silicon crystal and diffusing either n+ or p+ ions through the thin oxide into the silicon crystal (20) . After this heavy (ion) diffusion step, a conducting layer of either metal or polysilicon (19) is placed on top of the thin oxide. For common silicon gate CMOS processes, the diffused capacitor plate requires an extra lithography step. This extra lithography step can adversely impact yield and hence result in a higher fabrication cost.

Also, the bottom (diffusion) electrode (20) has a large non-linear capacitance (voltage coefficient) due to coupling to the substrate (21) (also known as the bulk) . Gregorian and Temes, p.89. This heavy diffusion-to- substrate back plate also has a junction leakage current associated with it. Id.; Gray and Meyer, Analysis and Design of Analog Integrated Circuits. John Wiley & Sons (1984), p. 148. Therefore, in order to achieve accurate analog processing, the voltage on the diffusion electrode (20) cannot be permitted to float, or parasitic capaci¬ tance problems and leakage induced drift will be signifi- cant.

As for the second type of capacitor that uses a poly¬ silicon layer for the bottom electrode (Figure 5) , a thin oxide must be grown on top of the polysilicon layer (24) . Growing a thin oxide on top of polysilicon leads to accuracy and yield problems, because the granularity of the polysilicon surface presents a poor oxidation host surface. Gregorian and Temes, pp. 88-89. Since the growth of the thin oxide (insulator) layer is not well controlled, MOS capacitor matching becomes more difficult. Typically, a thicker oxide layer is grown on top of the polysilicon layer to help overcome the granularity prob- lem. But the capacitance per unit area of the capacitor is reduced when the insulating layer is thickened, thereby effectively increasing the size of the capacitors required to implement a desired function.

Using either of these types of capacitors, additional problems are incurred depending upon whether the top electrode (23) is metal or polysilicon. If metal is used, metal ions can diffuse into the thin oxide layer, thereby reducing the insulating properties of the oxide layer. Also, using metal as an electrode leads to accuracy problems because the conductance of the metal electrode is effectively increased by the amount of metal interconnect (22) that is bonded to the capacitor.

If a double polysilicon capacitor is desired (i.e., both the top and bottom electrodes (23, 24) are poly- silicon) , the cost of manufacturing the IC will be in¬ creased. Since an extra mask step is necessary to add the second polysilicon layer, a lower IC yield can be expect¬ ed.

Most digital IC fabrication processes typically only require the fabrication of transistors and low accuracy capacitors. Current digital IC fabrication processes have many well-controlled parameters including a uniform transistor threshold voltage and uniform thin oxide thickness (local relative accuracy of about 0.05%) . Since most conventional digital IC processes provide only a single polysilicon layer, these fabrication processes are currently the least expensive IC manufacturing processes available. But since these digital processes lack a second polysilicon layer or a diffused capacitor plate, thermally grown oxide capacitors cannot be fabricated and therefore switched capacitor circuits are not normally fabricated in these digital processes. Only parasitic capacitors, such as polysilicon to metal capacitors, are available, but these capacitors lack good fabrication control and have an undesirably low value of capacitance per unit area.

Objects of the Invention

In view of these limitations in the prior art, one object of the present invention is to provide for mono¬ lithic electronic amplification circuits that have feed¬ back and analog signal processing functions that do not require the construction of monolithic resistors or thermally-grown capacitors.

A second object of the present invention is to provide accurate analog signal processing circuits that can be fabricated in conventional digital processes, thereby eliminating the need for specialty fabrication processes for many signal processing functions and conse¬ quently decreasing the cost of manufacturing these cir¬ cuits.

A third object of the present invention is to in- crease the accuracy of many analog processing circuits by eliminating the need for monolithic passive components, such as capacitors and resistors.

A fourth object of the present invention is to in¬ crease the integration density of many analog signal processing circuits by eliminating the need for resistor and capacitor components. Increasing circuit density will serve to reduce silicon requirements to implement many circuit functions and thereby reduce manufacturing costs for these circuits. A fifth object of the present invention is to provide analog signal processing circuits that can replace conven¬ tional switched capacitor circuits and can be monolithi¬ cally integrated on the same substrate as high density digital CMOS circuitry. Other objects of the present invention will become apparent as the description proceeds. SUMMARY OF THE INVENTION

The present invention relates to the novel technology of channel coupled feedback circuits for making accurate and reliable signal processing circuitry. By using channel coupled feedback circuits, circuit functions previously performed by switched capacitor or resistor components can be implemented in conventional digital IC fabrication processes that do not require or provide for a special capacitor or resistor layer. In fact, many analog and digital signal processing functions that are currently capable of monolithic integration can now be implemented solely with semiconductor devices using the present invention, thereby completely eliminating the need for passive components, such as capacitors and resistors for these circuit functions. In applicant's preferred embodiment, an inverting, fixed-gain amplifier is con¬ structed solely with field effect transistors (FETs) .

As illustrated in Figure 1, channel coupled feedback technology used in the present invention is characterized by (a) one or more channel reset device(s) (1) that serve to fix the amount of charge in the channel during the computation phase, and (b) two or more channel coupled semiconductors (CCSCs) (3) that perform the signal pro¬ cessing function in conjunction with (c) a means (5) for sensing charge transfer within the channel, which means may also maintain the surface voltage of the channel constant. The CCSCs (3) are preferentially FETs and are electronically connected or coupled to each other and to the channel reset device(s) (1). The channel reset device(s) (1) preferably are FETs, but can be any means for controlling the flow of charge into the channel. The means (5) for sensing the charge transferred within the channel and for maintaining the surface voltage of the channel constant is preferentially an operational ampli- fier.

Preferably, signal processing operations are per¬ formed in the present invention by setting the channel to a fixed reset voltage having a fixed amount of charge. An input signal (6) is applied to one or more of the CCSCs (3) which will cause charge to be transferred under the CCSCs within the channel if the input signal differs from the reset voltage. By sensing the amount of charge that has been transferred within the channel, channel coupled semiconductor devices can perform many feedback and signal processing functions, including but not limited to, fixed- gain, sample and hold, addition, subtraction, offset compensation, integration, differentiation, analog-to- digital conversion, digital-to-analog conversion, switch- able gain, ladder filtering and linear transform computa¬ tion.

In one aspect of the present invention, channel coupled feedback operation can be summarized as follows. In the reset phase of the signal processing operation, a reset signal is applied to the channel reset device(s) , so as to allow charge to fill the channel from a charge source. The surface potential of the channel is fixed at a desired level during this phase. Upon the removal of the reset signal, the channel is disconnected from the charge source.

Preferably, the channel reset device is one FET. In the reset phase, a reset voltage is applied to the gate of the channel reset FET permitting the substrate under the FET gate to become conductive. In the post-reset phase, a post-reset voltage is applied to the gate, causing the channel reset FET to become non-conductive and to act as a barrier preventing charge from moving either into or out of the channel.

In the computation phase of the feedback or signal processing operation, the input signal (e.g., a voltage) to be processed is applied to the gate of at least one of the channel coupled semiconductors within the channel. Preferably, the channel coupled semiconductors are FETs. Applying the input signal to the gate of one of the FETs causes the amount of charge under the gate of that FET to change, which change is proportional to the input signal voltage applied to the gate and the area of the gate. The charge is transferred to or from the substrate underneath the gates of the other FET(s) within the channel. By adding a device to sense the charge movement within the channel, preferably an operational amplifier, a variety of analog and digital signal processing functions are possi¬ ble. These channel coupled semiconductors are preferen¬ tially employed to perform the signal processing functions normally associated with conventional feedback functions that previously have been constructed with passive compo¬ nents, such as capacitors or resistors.

Applicant has therefore invented a channel coupled feedback technology that can be used to implement a variety of feedback and signal processing functions in commodity digital IC fabrication processes. The need for precision passive components is avoided and the cost of implementing circuit functionality is reduced. Circuits constructed according to the present invention will also serve to increase the integration density of most analog signal processing circuits, thereby reducing the silicon area necessary to implement these circuit functions. Further, since many commodity digital processes have well controlled transistor fabrication steps, the accuracy of many analog signal processing circuits can be improved.

BRIEF DESCRIPTION OF THE FIGURES

Figure 1 is a block diagram of channel coupled feed¬ back circuits constructed according to the present inven¬ tion. Figure 2 is a schematic of a conventional inverting, fixed-gain amplifier implemented with resistors.

Figure 3 is a schematic of a conventional inverting, fixed-gain amplifier implemented with switched capacitors.

Figure 4 is a cross-section of a conventional mono- lithic capacitor having a diffusion bottom electrode (20) and either a metal or polysilicon top electrode (19) . Figure 5 is a cross-section of a conventional mono¬ lithic capacitor having a polysilicon bottom electrode (24) and either a metal or polysilicon top electrode (23) .

Figure 6 is a schematic of an inverting, fixed-gain amplifier implemented with the channel coupled feedback technology of the present invention.

Figure 7 is a clock diagram appropriate to implement the circuit of Figure 6.

Figure 8 is a top view of a layout of the circuit of Figure 6.

Figure 9 is a top view of a second layout of an inverting fixed gain amplifier constructed according to the present invention.

Figure 10 is a schematic of the circuit of Figure 6 with a conceptual physical cross section of the channel coupled semiconductors.

Figure 11 is an electron well diagram of the circuit of Figure 10 in the reset phase of the circuit operation.

Figure 12 is an electron well diagram of the circuit of Figure 10 in the post-reset phase of the circuit operation.

Figure 13 is an electron well diagram of the circuit of Figure 10 in the signal processing or computation phase of the circuit operation. Figure 14 is a simplified functional equivalent circuit of the circuit shown in Figure 6.

Figure 15 is a schematic of the circuit of Figure 6 that has been constructed with "unit gates."

Figure 16 is a schematic of an inverting, fixed-gain amplifier constructed according to the present invention having two FETs (122, 124) to decouple the gates of FETs

(121, 123) and FETs (123, 125) in order to eliminate perimeter coupling (sidewall capacitance) . Figure 17 is a schematic of a non-inverting, fixed- gain amplifier constructed according to the present invention.

Figure 18 is a schematic of an offset compensated, 5 inverting, fixed-gain amplifier constructed according to the present invention.

Figure 19 is a schematic of an offset compensated, sample and hold circuit constructed according to the present invention. 10 Figure 20 is a schematic of an addition circuit constructed according to the present invention.

Figure 21 is a schematic of a subtraction circuit constructed according to the present invention.

Figure 22 is a schematic of an inverting, offset 15. compensated integrating amplifier constructed according to the present invention.

Figure 23 is a clocking scheme appropriate to imple¬ ment the circuits of Figures 22 and 24.

Figure 24 is a schematic of an inverting, offset 20 compensated differentiating amplifier constructed accord¬ ing to the present invention.

Figure 25 is a schematic of a fully differential amplifier constructed according to the present invention.

Figure 26 is a digital-to-analog converter construct- 25 ed according to the present invention.

Figure 27 is a logic diagram that is appropriate to generate the clocking scheme to implement the circuit of Figure 26.

Figure 28 is a block diagram of a successive approxi- 30 mation analog-to-digital converter constructed according to the present invention.

Figure 29 is a schematic of a digital to analog converter combined with a comparator that can implement an analog-to digital converter constructed according to 35 Figure 28. Figure 30 is a switchable gain, inverting amplifier constructed according to the present invention that can be used in an automatic gain control system.

Figure 31 is an analog pixel matrix that is imple- mented with channel coupled semiconductors.

Figure 32 is a flow chart for the manufacture of an inverting, fixed-gain operational amplifier according to the present invention.

DESCRIPTION OF THE EMBODIMENTS As the illustrations and description herein show, applicant has invented channel coupled feedback circuits that can be used to implement a variety of analog and digital signal processing functions. The operation and effect of channel coupled feedback circuits (Figure 1) can be understood by an analysis of the preferred embodiment, e.g., an inverting, fixed-gain amplifier constructed according to the present invention, as shown in Figure 6. The circuit of Figure 6 can perform the same signal processing function as the conventional circuits shown in Figures 2 and 3, A monolithic inverting, fixed-gain amplifier constructed with channel coupled semiconductors does not require monolithic resistive elements (8, 9) as in Figure 2 or well-matched monolithic capacitors (14, 16) fabricated with a special process having two capacitor electrode layers as in Figure 3. Instead, the functional¬ ly equivalent circuit shown in Figure 6 can be constructed entirely in a conventional digital IC fabrication process designed to implement FETs only.

An inverting, fixed-gain amplifier can be construct- ed, for example, with as few as three channel coupled semiconductors ("CCSCs"). In applicant's preferred embodiment, the channel coupled semiconductors are, in fact, channel coupled FETs, in which all three FETs share a common channel. Referring to Figure 6, applicant preferably employs one channel reset device, FET (30) , to permit charge to move into and out of the channel during the reset phase of operation. This device (30) essential¬ ly performs a switching function at one end of the chan¬ nel. When the switch (channel reset device) is closed, charge^* is conducted either into or out of the channel, depending upon the surface voltage of the channel, in order to achieve potential equilibrium within the channel. Once potential equilibrium is achieved, the switch may be opened, thereby fixing the amount of charge within the channel. Those skilled in the art will recognize that only one device is necessary to permit the movement of charge into or out of the channel, but that increasing the number of switches between the channel and a charge source may permit the channel to reach potential equilibrium faster. Those skilled in the art also will recognize that the channel reset device may be connected to the channel at any point along the channel.

Also, the type of charge reset device (30) utilized is not essential to practice the invention. Any device that permits switching control to a source of charge is appropriate for use with the present invention. For example, a bipolar transistor, a charge coupled device

(CCD) or a more elaborate switching means, such as a T- gate, also may be employed to provide the channel reset function, depending upon the performance characteristics desired by the IC designer.

In Figure 6, one terminal of FET (30) is electroni¬ cally connected to V_cs (29) , which connection provides a supply of charge for the channel. V_cs represents a channel set voltage. The channel reset device(s) is (are) con- nected to V_cs, which preferably is a small positive voltage, but those skilled in the art will recognize that a variety of voltage sources can be used to supply charge to the channel, including electrical ground.

Therefore, the reader will note that the IC designer has great latitude in deciding how many channel reset devices to provide for the channel, the type of device to be used to perform the switching function, the position along the channel to connect the channet reset device and the voltage source that is connected to the channel by the channel reset device(s). Preferably, applicant uses one FET (30) to perform the switching means and FET (30) is connected to a small positive voltage, V_cs (29) , to supply charge to the channel.

Referring again to Figure 6, the gate of the channel reset FET (30) is controlled by the phi clock signal. An appropriate clocking scheme for the circuit of Figure 6 is shown in Figure 7. In the preferred embodiment the clocking scheme is comprised of two non-overlapping clocks (phi and ph2) . When phi is high, a reset voltage is applied to the gate of the channel reset FET (30) , which reset voltage in turn permits electrons to flow into or out of the channel through FET (30) . When phi is low, a post-reset voltage is applied to the gate of the channel reset FET (30) , thereby preventing the flow of electrons into or out of the channel. A zero voltage signal is appropriate for the second phase of phi. Referring back to Figure 6, FET (30) serves to conduct electrons into or out of the channel during the reset phase and then acts as an electron barrier during the signal processing or computation phase, thereby maintaining a constant or fixed amount of charge in the channel during the signal process- ing or computation phase.

In the embodiment shown in Figure 6, three channel coupled semiconductors, FETs (31) , (32) and (33) , share the common channel and the substrate regions of the channel FETs are electronically connected or coupled so that charge can move freely between the substrate regions beneath the FETs. The substrate underneath the gate of a FET is a lightly doped silicon crystal. Acting as a true semiconductor, when a zero voltage is applied to a gate on the surface of a lightly doped p-type silicon crystal, electrons are not conducted within the substrate. There¬ fore outside of the channel, no voltage is applied to the lightly doped substrate and thus, no electrons are con- ducted. Thus, lightly-doped p-type silicon with no voltage applied to it acts as an insulator.

When a voltage is applied to the gate of a FET, charge within the substrate is attracted to the substrate surface. Those skilled in the art also will recognize that if a negative voltage is applied to the gate, posi¬ tive charge will be attracted to the substrate surface and vice versa. Those skilled in the art also will recognize that when the gate voltage of the FET reaches its thresh- old voltage, the substrate underneath the gate becomes inverted. This attracted charge is mobile and can be moved within the inverted substrate underneath the gate. By providing a means (38, 39) for electronically connect¬ ing the inverted substrate regions underneath the gates of the FETs (31-33) within the channel, charge can move freely throughout the common channel, when the gates of FETs (31-33) are held at a voltage permitting conduction underneath the gates. The means (37-39) for electronical¬ ly connecting the substrates can be, for example, either a heavily doped ion diffusion implant, polysilicon, metal interconnect, a charge-coupled device (CCD) or an addi¬ tional FET between the two FETs to be connected, wherein the additional FET is biased to be conductive.

Therefore, as used herein, the channel is comprised of (a) the semiconductor substrate regions underneath the gates of the channel coupled semiconductors that are inverted when the threshold voltage of the device is applied to the gate and (b) the means for electronically connecting the inverted substrate regions. The channel is connected to the channel reset device (s), which channel reset device(s) also can connect the channel to a voltage (charge) source during the reset phase. The layout of the semiconductor substrate regions and the connection means are not essential to practice the invention, nor is the order in which the semiconductor substrates are connected within the channel. Preferably, the applicant uses FETs to perform the feedback or signal processing functions. For this pur¬ pose, a FET is defined as a device having a metal or polysilicon gate and heavy (ion) diffusion implants for the drain and source terminals. In the preferred embodi¬ ment, the means (38, 39) for electronically connecting any two FETs within the channel, and for that matter the means (37) for connecting a FET within the channel to the channel reset device(s), is the heavy (ion) diffusion implant. The two FETs to be electronically connected may share a heavy diffusion implant, wherein this implant serves, for example, as the drain of one FET and the source of the second FET. Therefore, the implant acts as means for conducting charge from the inverted substrate region of one FET to the inverted substrate region of the second FET.

One skilled in the art should recognize that the essential function of the channel coupled FET in the preferred embodiment of the present invention is the use of the gate of the FET and the lightly-doped substrate underneath the gate in a manner that is functionally equivalent to a capacitor. The source and drain implants of the FETs are merely used as means for electronically connecting or coupling the substrates underneath the FETs. Thus, to practice the present invention a channel coupled semiconductor device is comprised of a gate separated from the lightly doped silicon crystal (substrate) by a silicon dioxide layer (insulator) . The lightly doped silicon crystal substrate conducts only when a voltage is applied to the surface of the substrate.

Therefore, as used herein, a channel coupled semicon¬ ductor is a device having at least (a) a gate constructed of a conducting material, preferably polysilicon, (b) a lightly doped silicon crystal substrate and (c) an oxide (insulating) layer separating the gate and the substrate. The oxide (insulating) layer is preferably silicon diox¬ ide, although those skilled in the art will recognize that other materials may be used for the insulating layer, such as Si₃N₄. As noted above, the substrates of the channel coupled semiconductors can be connected by, for example, diffusion (ion) implants, polysilicon, metal, a CCD, or some combination of these elements. As will be shown in Figure 16 that is discussed below, two substrates also can be connected by an additional gate above the lightly doped substrate, where the gate is biased such that the sub¬ strate underneath the gate is conductive. Those skilled in the art will recognize in view of the present disclosure that the particular arrangement of the semiconductors within the channel is not important to the invention. Since charge can move freely within the common channel, the location of any specific channel coupled semiconductor or channel reset device is not essential to practice the invention. For example, Figure 8 shows a top view of a layout for Figure 6. The reader will note that the solid line blocks represent the gates of the channel coupled semiconductors (41-43) and the channel reset device (40) . For example, block (41) represents the gate of FET (31) in Figure 6. The dashed line structure (44) represents the channel, which is a combination of (a) lightly doped substrate and thin oxide underneath the gates and (b) heavy (ion) diffusion. The solid lines represent standard electrical connections (wires) which may be metal, polysilicon or a heavy (ion) diffusion, for example.

Consistent with the previous discussions, Figure 9 shows a different layout for a fixed-gain amplifier that is equivalent in function to the circuit of Figure 6. In this figure, the reader will note that a channel reset device (52) has been connected to the substrate region of the channel coupled semiconductor whose gate (50) is connected to the output of the amplifier (56) . Also, note that gates (50, 51) have been switched in order from the location in Figure 8. Thus, the arrangement and the location of the channel coupled semiconductors, the channel reset device(s) and the amplifier is within the discretion of the IC designer. Also, those skilled in the art will recognize that additional semiconductors, FETs or even passive components can be used to modify the func- tionality of the circuit without departing from the spirit of the invention.

Therefore, the reader will note that the IC designer has great flexibility, for example, in deciding the number of channel coupled semiconductors to use in the channel, the material to be used to electronically connect the substrate regions, the arrangement of channel coupled semiconductors within the channel, and the order in which the semiconductor substrates are connected.

Referring back to Figure 6, in the preferred embodi- ment the gate of FET (31) can be connected to V_ref in one phase and to V_in (the input signal to be processed) in the second phase. The gate of FET (32) is connected to the inverting (-) input of the operational amplifier (35) . The gate of FET (33) is connected to the output terminal of the amplifier (35) . The gates of FETs (32) and (33) are connected through switch (34) during the reset phase when phi is high.

Those skilled in the art will recognize in light of the present disclosure that the design of the operational amplifier (35) is not essential to practice the present invention. Many conventional operational amplifier designs are appropriate for use with the present inven¬ tion. The designs for a variety of operational amplifiers appropriate for use with the present invention can be found both in Gregorian and Temes and in Allen and Holberg. The IC designer has great flexibility in choos¬ ing the design of the operational amplifier to maximize desired performance characteristics, such as power, slew rate, accuracy, settling rate, etc. For example, in one aspect of the preset invention, the amplifier is an inverting, fixed-gain high voltage amplifier capable of amplifying a video image input signal into a high voltage output signal, which output signal can be driven onto a liquid crystal display. Further details concerning the operation and effect of this amplifier can be found in United States Patent Application, Serial No. 08/185,540. Also, the non-inverting (+) input of the amplifier (35) is connected to a reference voltage (V_ref) in the present example. But those skilled in the art will recog¬ nize that, depending upon the specific application of the present invention, the non-inverting input can also be connected to some other voltage that is between the power supply rails for the amplifier.

Referring to Figures 10-13, the operation of the channel coupled semiconductors in an inverting, fixed-gain amplifier system is best understood by examining electron well diagrams of the channel during each phase of the signal processing operation. For illustrative purposes, the circuit of Figure 6 has been redrawn in Figure 10 to show the substrate regions of the channel coupled feedback circuits. Figures 11, 12 and 13 show electron well diagrams for the reset, post-reset and computation phases, respectively. While not wishing to be bound by theory, applicant believes the operation and effect of channel coupled semiconductors can be best understood by analyzing how charge moves within the channel during the reset, post-reset and signal processing operation phases of the device. All four figures (10-13) should be viewed togeth¬ er.

As shown in Figure 11, during the reset phase, the channel reset FET (70) is pulsed by the phi signal (shown in Figure 7) , so as to allow charge to flow into or out of the channel. Ph2 is low during this phase. A reference voltage (V_ref) is applied to FET gate (71) . With the switch

(74) closed between FET gates (72) and (73) , the amplifier

(78) is in a unity gain follower configuration. There- fore, V_ref is also applied to FET gates (72) and (73) . Thus, during the reset phase, the gate voltages of the channel coupled FETs are set to V_ref by operation of the amplifier (78) and FET gates (71), (72) and (73), and charge is permitted to move into the channel via the channel reset FET (70) , so that potential equilibrium is achieved within the channel. In Figures 11, 12 and 13 mobile charge within the inverted substrate is designated by a diagonal cross hatch.

As is shown in Figure 12, during the post-reset phase, the channel reset FET (70) is pulsed so as to provide a barrier to the movement of electrons into or out of the channel, preferably by applying a zero volt signal to FET gate (70), as is shown in Figure 7. In this phase, both phi and ph2 are low. Therefore, the channel becomes electronically isolated from the charge source, V_cs, with a fixed amount of charge within the channel and has a common channel gate voltage of V_ref.

As shown in Figure 13, during the signal processing or computation operation, the input signal (V_in) is applied to the gate of FET (71) . This operation is performed when phi is low and ph2 is high. In the example shown in Figure 13, V_in is a lower voltage than V_ref, thereby causing electrons to be forced out of the substrate region immedi¬ ately underneath FET gate (71) . The dashed section (91) under FET gate (71) indicates the amount of electrons forced from the substrate region by the application of V_in. Since the channel is electronically isolated by FET (70) and FET substrate regions (63, 65 and 67) are electroni¬ cally coupled by heavy (ion) diffusion implants (64, 66), the charge forced out from underneath FET gate (71) , due to the application of V_in to FET gate (71) , must move to the channel underneath FET gates (72) and (73) . As charge moves under FET gate (72) , the charge temporarily will cause the voltage on that gate (72) to change. But since the amplifier (78) will adjust its output (77) so that its input terminals (75, 76) are at the same voltage, and since the output (77) of the amplifier (78) is coupled to the input of the amplifier through the channel (65-67) connecting FET gates (72) and (73) , FET gate (72) will be maintained at V_ref. Therefore, essentially all of the charge forced from underneath FET gate (71) will be transferred to underneath FET gate (73) . The double cross hatch (95) in Figure 13 indicates the additional charge that has moved under gate (73) .

The gain of the amplifier system of Figure 6 can be calculated by conceptually treating FETs (31) and (33) as capacitors. In these applications, the channel coupled semiconductors are acting electronically in a manner similar to MOS capacitors, in which the light (ion) diffusion underneath each gate acts as one electrode and the polysilicon gate acts as the second electrode. A functionally simplified equivalent of the circuit of Figure 6 is shown in Figure 14. The variable capacitor C4 (102) indicates the non-linear parasitic capacitance of the channel charge regions to the bulk used in the present invention. But since C4 is kept at a constant voltage during the signal processing or computation phase by the operation of the amplifier (105) , the parasitic capaci- tance of C4 (102) is not noticeable and thus non-linearity is not a concern.

The charge held on a MOS capacitor is equal to the capacitance of the MOS capacitor multiplied by the voltage across the thin oxide, insulator layer: Q = C V (1) .

In the example shown in Figures 10-13, the amount of charge (91) forced out from the substrate region (63) underneath FET gate (71) is equal to C-*_. (V_in-V_ref) , wherein Ci is the gate oxide capacitance of FET (71) . Since the amount of charge forced from underneath FET gate (71) iε equal to the amount of new charge transferred to the substrate (67) underneath FET gate (73), the following relationship results:

C-_x (V^-V^) = C₂ (V-^-V^) (2) , wherein C₂ is the gate oxide capacitance of FET ( 73 ) . By rearranging equation (2 ) , the following relation is found : (V_out - V_ref) / (V_in - V_ref ) = -C_x/C₂ (3 ) . Thus, by adjusting the gate oxide capacitance of FETs (71) and (73) , the gain of a channel coupled semiconductor, inverting, fixed-gain amplifier can be chosen.

The intrinsic gate oxide capacitance of a FET is: C - e_ox A/1 (4) , where e_ox is the permittivity of silicon dioxide (approxi¬ mately 0.35 pF/cm) ; A is the area of the top electrode (the gate) and 1 is the thickness of the silicon dioxide layer. Gregorian and Temes, p. 69. This relationship can be employed to adjust the gate oxide capacitance of the FETs used in the present invention. In the case of the channel coupled semiconductors of the present invention, the FETs are physically located close to each other; thus, manufacturing variability between transistors should be low. Therefore, e_ox and 1 can be expected to be approxi¬ mately equal for each FET in the channel. With this fact in mind and substituting equation (4) into equation (3) , the gain of the present amplifier system will be propor¬ tional to the area of the gates of FETs (71) and (73) : (V_out - V_ref ) / (V_in - V_ref ) = -A1/A2 ( 5 ) .

Since the ratio of the areas of FET gates can be a well controlled parameter in most digital fabrication process¬ es, highly accurate fixed-gain amplifiers are possible using the present invention. The reader will note that the area of the gate (72) connected to the inverting (-) input terminal (75) of the operational amplifier (78) is not included in the gain calculation. Since the charge underneath this gate is kept constant during the reset, post-reset and computation phases, this gate does not play a role in adjusting the gain of the system. Thus, the designer may want to make the area of gate (72) as small as possible to minimize the silicon wafer area necessary to implement each signal processing function. But for design purposes, the size of the gate connected to the amplifier input should be correlated to the amplitude of the input signal. Simply stated, for large amplitude input signals gate (72) should be large and conversely, for small amplitude input signals gate (72) can be made small.

The necessity for adjusting the size of gate (72) is based^" upon the amount of time the amplifier takes to settle after the input signal has been applied to gate (71) . When a negative input signal is initially applied to the channel coupled semiconductor(s) , the surface voltage of the channel will fall until the proper amount of charge has been transferred from the substrate region (63) underneath (input) gate (71) to the substrate region

(67) underneath (output) gate (73) . If the surface voltage of the channel were to fall sufficiently to cause the channel reset device (70) to conduct, some charge would spill out of the channel, thereby affecting the accuracy of the circuit. By enlarging the area of (sense) gate (72) (and thereby the channel) , the fall in channel surface voltage is reduced by the increased surface area and charge capacity of the channel. Thus, by increasing the size of (sense) gate (72) , the negative input range is increased. Therefore, choosing the area of gate (72) is entirely within the discretion of the IC designer and can be tailored to each signal processing situation.

Although the FETs of this example are similar to substrate-to-polysilicon MOS capacitors, the performance of the present channel coupled semiconductors does not suffer from the non-linear voltage coefficient of such capacitors. Since the operational amplifier holds the surface voltage of the channel at a constant level, the channel-to-substrate parasitic capacitance is not problem- atic. Thus, the "capacitance" of the channel coupled semiconductors used according to the present invention is first order linear.

Although not necessary to practice the present inven¬ tion, the accuracy of the circuit shown in Figure 6 can be improved using various design refinements. First, the gate perimeter ratio of FETs (31) and (33) is an important consideration because the FETs are communicating between the edges of the gates. As a result of current IC manu¬ facturing processes, the edges of the gates (top elec¬ trode) are subject to random variation. In order to minimize the absolute error of each of the channel coupled semiconductors, the shape of the gates should be square. The relative error of channel coupled feedback circuits can also be minimized by ratioing the gates of the CCSCs. A common technique for increasing the accuracy of tradi¬ tional monolithic capacitor ratios is to connect identi- cally sized smaller capacitors ("unit capacitors") in parallel to construct a larger capacitor. Similarly, in order to increase the accuracy of channel coupled feedback circuits, identically sized smaller gates (and the sub¬ strates underneath the gates) can be connected in parallel to construct larger "capacitors." For further instruction on the use of perimeter ratioing and unit capacitors to improve the accuracy of analog processing circuits employ¬ ing capacitors, see Gregorian and Temes, pp. 90-93; McCreary, Matching Properties, and Voltage and Temperature Dependence of MOS Capacitors, IEEE J. Solid-State Cir¬ cuits. SC-16, 608-618 (1981) .

Channel coupled feedback circuits can be constructed with "unit gates" to minimize the effects of manufactur¬ ing variation. That is, identically sized gates can be connected to form the channel coupled semiconductors.

Referring to Figure 15, the circuit of Figure 6 has been constructed with "unit gates" in a configuration having a 4x voltage gain. Each of gates (110-113, 115) is an identically sized square gate. Gates (110-113) are connected to the input signal and the substrate regions underneath those gates are connected to form the channel. Those skilled in the art will recognize that a wide variety of circuit designs and layouts can be implemented using "unit gates" without departing from the spirit of the present invention.

Second, to decouple the parasitic capacitance between the gates of the channel coupled semiconductors (sidewall capacitance) , two or more additional FETs can be added to the circuit of Figure 6. Preferably, applicant employs the use of transistors, although a device having just an overlapping gate and a semiconductor substrate (no addi- tional source or drain implants) is sufficient for this decoupling function. Referring to Figure 16, FETs (122) and (124) have been added between channel FETs (121)/ (123) and (123)/(125). The gates (127, 128) of FETs (122, 124) are held at a constant voltage throughout the reset, post- reset and computation phases. In this case, the constant voltage is the high rail of the power supply, V_dd. Since FETs (122) and (124) are n-FETs, a high voltage on the gate makes the n-FET conductive. Therefore, FETs (122) and (124) allow charge to pass underneath the gates, but remove the parasitic (sidewall) capacitance between FETs (121) , (123) and (125) .

One additional design consideration when using channel coupled semiconducting according to the present invention is that the input and output voltage ranges of channel coupled feedback devices are limited by the need to keep channel charge under all FETs in the channel. If the input signal is driven below the charge source voltage plus the characteristic transistor threshold, V_cs+V_τ, then the channel underneath the input FET has no charge beneath it, thus changing the influence the input voltage has on the rest of the circuit drastically.

Similarly, for the output voltage range, the output can never drop below V_cs+V_τ. Since V_cs is a low voltage (possibly electrical ground) and V_τ is typically less than a volt, the restrictions on input and output ranges are noticeable but not a substantial hindrance in most circuit designs.

Those skilled in the art will recognize that the inverting, fixed-gain amplifier described herein can be used to amplify any input signal regardless of whether the signal is characterized as an "analog" or a "digital" signal. The reader will also note that the teachings provided with regard to the present preferred embodiment are applicable to the additional examples and are incorpo¬ rated into all of the additional examples.

The following examples serve as additional illustra- tions of the use of the present invention and should not be construed as limitations of the claimed invention. Those skilled in the art will recognize that numerous modifications can be made to the circuits described herein to tailor the performance of the circuit to a specific application without departing from the spirit of the invention. Furthermore, applicant has described herein various signal processing circuits that may serve as building blocks of larger, more complicated applications, such as ladder filters, for example. These larger cir- - cuits are encompassed within the scope of the present invention.

Additional Examples

Example 1. Non-Inverting, Fixed-Gain Amplifier Referring to Figure 17, a non-inverting, fixed-gain amplifier can be constructed according to the present invention. As can be seen by comparison to Figure 16, the only difference between the two circuits is that the clocking of switches (131) and (132) has been swapped. The clocking scheme shown in Figure 7 also is appropriate to operate this non-inverting amplifier. As was discussed above, the use of FETs (135, 137) is optional and at the discretion of the designer. Also note that a second (optional) channel reset device (139) has been included.

Example 2. Offset Compensated Inverting, Fixed-Gain Amplifier

One nonideal effect that can degrade the performance of practical amplifiers is offset voltage. To reduce the effects of operational amplifier offset voltage in a channel coupled feedback, inverting, fixed-gain amplifier system, a few additional components may be added to the circuit in Figure 6. Referring to Figure 18, switch (149) is added and is controlled by the ph2 clock of Figure 7. Switch (150) is also added and is controlled by the phi clock^'of Figure 7. The drain of switch (150) is connected to the gate of FET (147) and the source of switch (150) is connected to V_ref.

When the phi clock is high and the ph2 clock is low (reset phase) , the output of the operational amplifier is shorted to its inverting input and the amplifier performs as a unity-gain follower, having an output voltage of V_ref + V_of£set. Also in this clock phase, ^• switch (142) is open and switch (143) is closed; therefore FET gate (145) is set to V_ref. Likewise, FET gate (147) is also set to V_ref by the operation of switch (150) . Therefore, gate (146) is set to V_ref + V_of£set. When phi is low and ph2 is high (computation phase) , V_in is connected to gate (145) and gate (147) is connected to the output of the amplifier (151) . Since V_offget was added to gate (146) during the reset phase, the output of the operational amplifier will be corrected for the offset voltage during the computation phase.

Those skilled in the art will recognize that the offset compensation teaching of this example can be applied to any of the examples described herein to cancel operational amplifier offset voltage.

Example 3. Offset Compensated Sample and Hold Those skilled in the art will recognize that the inverting, fixed-gain amplifier of the preferred embodi¬ ment can also function as a sample and hold circuit. The sample and hold periods of the circuit operation can be adjusted by changing the widths of the phi and ph2 clocks, while maintaining the non-overlapping phases. Also, the offset compensated, inverting, fixed-gain amplifier of Figure 18 can also perform the offset compensated, sample and hold function. In addition, Figure 19 shows a simple offset compen¬ sated sample and hold circuit constructed with fewer components than the previous examples. This circuit also can be implemented using the non-overlapping clocks of Figure 7. When phi is high, gate (155) acquires voltage V_in + V_offset. When ph2 is high, the output voltage is therefore

'^in ⁺ ^offset) - V_offβet = V_in .

Example 4. Addition Circuit

A circuit for adding input signals can be constructed according the present invention and is shown in Figure 20. In this illustration, n input signals may be added. Any linear combination of the input signals can be made by adjusting the area ("capacitance") of gates (174-176) . As was shown in Equation 5 above, the output voltage in this example will be equal to - [Al(VI - V_ref) + A2(V2 - V_ref) + . . . + An(VN - V_ref)] /An+1.

Example 5. Subtraction Circuit

Similar to the addition circuit of Example 4, a subtraction circuit can be constructed by inverting the clock phase of the input signal(s) (180, 181) to be subtracted. For simplicity, the subtraction of two input signals is shown in Figure 21. But as in Figure 20, the array of input signals can be increased by adding addi¬ tional gates and the designer is free to choose the number of inputs to be subtracted.

Example 6. Integrating Amplifiers

Referring to Figure 22, an inverting, integrating offset compensated amplifier constructed according to the present invention is shown. The reader will note that the construction of the components for the inverting, inte¬ grating offset compensated amplifier is similar to an inverting, fixed-gain, offset compensated amplifier. The only differences are that FET (194) is connected to the ph2 clock, and the reset and offset compensation signals are controlled by ph3 and ph4, which act as global reset signals. The clocking scheme shown in Figure 23 is appropriate to operate this integrating amplifier.

Those skilled in the art will recognize that FET (194) should be constructed, and ph2 chosen, such that an electron barrier is created in the channel underneath FET (194) when V_ref is applied to the gate of FET (193) .

FET (194) also serves to decouple FET (193) from FET (195) , because FET (194) is being driven by an external voltage source.

A non-inverting, offset compensated integrating amplifier can also be constructed according to the teach¬ ing in Example 1 by swapping the clock signals to switches (190) and (191) .

Example 7. An Inverting. Offset Compensated Differentiating Amplifier

Referring to Figure 24, an inverting, offset compen¬ sated differentiating amplifier constructed according to the present invention is shown. The reader will note that the construction of the inverting, offset compensated differentiating amplifier is similar to the inverting, fixed-gain amplifier shown in Figure 16. To perform the differentiating function, additional gates are added. V_ouc can be connected to the gate of FET (209) when ph2 is high. When phi is high and ph2 is low, the gate of FET (209) is connected to V_ref. Again, the clocking scheme in Figure 23 is appropriate to implement this example. Those skilled in the art will recognize that FET (208) should be constructed so that an electron barrier is created in the channel underneath FET (208) when V_out is applied to the gate of FET (207) .

FET (208) also serves to decouple FET (207) from FET (209) , because FET (208) is being driven by an external voltage source. Those skilled in the art will recognize numerous modifications to the circuits presented here. For exam- pie, all transistors can be p-FETs and the computation charge can be holes instead of electrons. Furthermore, the circuits thus described have only been single-sided. A fully differential fixed gain inverting amplifier is shown in Figure 25.

Example 8. Digital-to-Analog Converter A digital-to-analog converter (DAC) can be construct¬ ed according to the teachings of Example 4, the addition circuit. Referring to Figure 26, the reader will note the similarities to Figure 20. A DAC may be structured to convert a digital word using a weighted array of capaci¬ tors. The output of the array of capacitors is sensed by an amplifier to generate the analog signal.

Figure 26 shows a 3-bit DAC constructed according to the present invention. As is standard for a weighted array of capacitors, the most significant bit of the digital word is applied to the largest gate (236) and the least significant bit is applied to the smallest gate

(238) . The linear combination of the voltages added to gates (236-238) causes charge to shift to the channel underneath gate (240) . The clocking for switches (230- 235) can be generated by the logic circuit shown in Figure 27.

The logic of Figure 27 selects which transition direction (either up or down) the input gates of the weighted capacitor array are driven during the computation phase of the circuit. The transition direction depends on the digital input word of the DAC.

This DAC can, of course, be expanded to convert larger digital words by adding progressively larger gates to the weighted array. Unit gates as shown in Figure 15 can also be used to implement this DAC. Further, offset compensation can be added to improve the accuracy of this circuit as was taught in Example 2. Those skilled in the art will recognize that this DAC is simply one illustra¬ tion of a DAC that can be implemented with channel coupled semiconductors and that numerous variations in the design and layout can be made to tailor the DAC to the intended performance specifications.

Example 9. Analog-to-Digital Converter _, A successive approximation analog-to-digital convert¬ er (ADC) can be constructed using components previously described in Examples 3 and 8. Figure 28 shows a block diagram of a conventional successive approximation ADC. See e.g., Gregorian and Temes, pp. 420-425. The DAC block (248) can be implemented with the DAC described in Example 8. The Sample and Hold block (246) can be implemented with the sample and hold circuit described in Example 3. The comparator (249) , successive approximation shift register (250) and switch logic (247) all can be imple- mented with conventional circuits.

More preferably, applicant constructs an ADC accord¬ ing to Figure 29. A logic circuit that is appropriate for generating the clock signals to switches (259-264) is shown in Figure 27. The circuit of Figure 29 is a cotn- bined DAC and comparator that compares the digital word input with the input voltage, V_in. In this illustration, the reader will note that the comparator (266) is used to determine whether the surface voltage has been raised above V_ref during the computation phase. Thus, the channel surface voltage is not kept constant during the perform¬ ance of the signal processing operation. Again, those skilled in the art will recognize the various additions and modifications that can be made without affecting the ADC function. Example 10. Switchable Gain Amplifier The unit gate configuration of Figure 15 can be modified to provide a switchable gain amplifier. Refer¬ ring to Figure 30, switches (278-280) have been added that allow the number of gates in the array to be added during the computation phase. The clock scheme of Figure 7 is appropriate to clock the phi and ph2 switches. Switches (278-280) may be controlled by signals generated from a switch logic circuit. Once again, the designer has great latitude in determining the signals to be generated depending upon the application and the function and performance desired.

Also, the reader will note that the switchable gain amplifier of Figure 30 can serve as the basis for an automatic gain control (AGC) system by adding a comparator function (298) to generate the switch logic signals (299) . Referring to Figure 30, the comparator (298) and switch logic (299) functionality can be implemented with conven¬ tional circuits, thereby permitting a channel coupled feedback AGC system.

Example 11. Analog Pixel Matrix

Referring to Figure 31, an analog pixel matrix for computing the linear transform of a matrix of analog values can also be constructed according to the present invention. Those skilled in the art will recognize that although some modifications have been made, the channel FETs are set to a fixed charge and the sense amplifier senses charge transferred within the channel. Further details for constructing a linear computation circuit can be found in United States Patent Application, Serial No. 08/186,372.

Example 12. Method of Manufacturing Charge Coupled Feedback Circuits

As has been described at length herein, many signal processing functions now can be implemented in digital IC fabrication processes that only provide for the construc¬ tion of field effect transistors. But applicant does emphasize that the use of a digital IC fabrication process is not a limitation of the present invention; rather, it is an advantage, since digital IC fabrication processes are the least expensive IC fabrication processes currently available. The IC designer may implement circuits of the present invention in any IC fabrication process that provides for field effect transistors, including specialty IC fabrication processes that provide high accuracy passive components.

Figure 32 shows a flow chart of a method that may be used to fabricate channel coupled feedback circuits. This method is merely one illustration and those skilled in the art will recognize that a variety of additions and modifi¬ cations may be made to this protocol.

Applicant has described a channel coupled feedback technology that can be used to implement a variety of signal processing functions. Those skilled in the art will recognize that the present channel coupled feedback technology can be used to implement other signal process¬ ing circuitry in which passive components, such as capaci¬ tors or resistors, are necessary using previous circuit designs, including signal processing circuits that have not been explicitly disclosed herein.

The present invention therefore provides the advanta¬ geous feature that monolithic circuit functionality, previously requiring passive components, can now be implemented solely with semiconductors, preferably FETs. Since these circuit functions only require FETs, conven¬ tional digital IC fabrication processes can be used that are less expensive than the special fabrication processes currently required to fabricate accurate monolithic capacitors and resistors. Because capacitors and resis- tors are not required, integration density of equivalent circuit functionality is improved, thereby reducing silicon requirements and further reducing the cost of implementing the desired circuit functionality. Also, since the surface of the channel is maintained at a constant voltage in most of the examples provided, the channel coupled semiconductors do not experience the first order non-linearity problems of substrate-to-polysilicon MOS capacitors.

Other aspects, uses and advantages of the present invention will be apparent to those skilled in the art upon review of the present disclosure. Those skilled in the art will also recognize that numerous changes can be made to the circuits described herein without departing from the spirit of the invention. For example, all of the n-FETs described in the circuits can instead be p-FETs and the computation charge can be holes insteads of electrons. The following claims set forth the scope of the present invention, which claims are not to be limited by the particular embodiments described above in the specifica¬ tion.

Claims

In the Claims:

1. A circuit for processing a first input signal into an output signal, comprising: an amplifier having at least one input terminal and at least one output terminal; a first channel coupled semiconductor (CCSC) device having a gate and a substrate region, wherein the gate of the first CCSC device can be electrically connected to the first input signal; a second CCSC device having a gate and a substrate region, wherein the gate of the second CCSC device is electrically connected to the input terminal of the amplifier; a third CCSC device having a gate and a substrate - region, wherein the gate of the third CCSC device is electrically connected to the output terminal of the amplifier, wherein the substrate regions of the first, second and third CCSC devices are electrically connected, and whereby the substrate regions of the first, second and third CCSC devices and the electrical connections between the substrate regions define a channel; and at least one channel reset device, wherein the channel reset device electrically connects a source of charge to the channel.

2. A circuit as in claim 1 wherein the amplifier, the first, second and third CCSC devices and the channel reset device are monolithically integrated.

3. A circuit as in claim 1 further comprising a fourth CCSC device having a gate and a substrate region, wherein the substrate region of the fourth CCSC device is electrically connected to the channel.

4. A circuit as in claim 3 wherein the fourth CCSC device serves as a means for electrically connecting the substrate regions of the first and second CCSC devices.

5. A circuit as in claim 4 further comprising a fifth CCSC device having a gate and a substrate region, wherein the fifth CCSC device is electrically connected to the channel.

6. A circuit as in claim 5 wherein the fifth CCSC device serves as a means for electrically connecting the substrate regions of the second and third CCSC devices.

7. A circuit as in claim 6 wherein a constant voltage is applied to the gates of the fourth and fifth CCSC devices.

8. A circuit as in claim 6 wherein a constant - voltage is applied to the fifth CCSC device and a two phase signal is applied to the gate of the fourth CCSC device, wherein one phase of the two phase signal causes a charge barrier to form in the substrate underneath the gate of the fourth CCSC device and the second phase permits electrons to be conducted in the substrate under¬ neath the gate of the fourth CCSC device.

9. A circuit as in claim 8 wherein the circuit provides an integrating function.

10. A circuit as in claim 6 wherein a constant voltage is applied to the fourth CCSC device and a two phase signal is applied to the gate of the fifth CCSC device, wherein one phase of the two phase signal causes a charge barrier to form in the substrate underneath the gate of the fifth CCSC device and the second phase permits electrons to be conducted in the substrate underneath the gate of the fifth CCSC device.

11. A circuit as in claim 10 wherein the circuit provides a differentiating function.

12. A circuit as in claim 1 wherein the amplifier has inverting and non-inverting input terminals and wherein the gate of the second CCSC device is electrically connected to the inverting input terminal of the amplifier and a reference voltage is electrically connected to the non-inverting input terminal of the amplifier, whereby the output signal is a fixed multiple of the input signal.

13. A circuit as in claim 1 wherein at least one of the CCSC devices is a field effect transistor.

14. A circuit as in claim 1 wherein the gate of at least one of the CCSC devices is comprised of polysilicon.

15. A circuit as in claim 1 wherein the substrate regions of the first, second and third CCSC devices are connected by an electrical connection means and wherein the electrical connection means is selected from the group consisting of a heavy ion diffusion implant, polysilicon, metal, a charge-coupled device and a field effect transis¬ tor biased to be conductive.

16. A circuit as in claim 1 wherein the channel reset device is selected from the group consisting of a field effect transistor, a bipolar transistor, a charge coupled device or a T-gate switch.

17. A circuit as in claim 1 wherein the circuit provides a sample and hold function.

18. A circuit as in claim 1 further comprising a sixth CCSC device having a gate and substrate, wherein the substrate is electrically connected to the channel and the gate can be connected to a second input signal.

19. A circuit as in claim 18 wherein the circuit provides a signal processing function selected from the group consisting of addition and subtraction.

20. A circuit as in claim 18 wherein the gates of the first and sixth CCSC device can be connected either to the first input signal and to the second input signal, the area of the gate of the first CCSC device is a multiple of the area of the gate of the sixth CCSC device and the circuit provides a digital to analog function.

21. A circuit as in any of claims 1-19 wherein the output wignal is offset compensated.

22. A sample and hold circuit, comprising: an amplifier having at least one input terminal and at least one output terminal; a first channel coupled semiconductor (CCSC) device having a gate and substrate region, wherein the gate is connected to an input signal in a first phase of operation and to the output terminal of the amplifier in a second phase of operation; a second CCSC device having a gate and substrate region, wherein the gate is connected to the input termi¬ nal and is connected to the output terminal of the ampli¬ fier in the first phase of operation and wherein the substrate regions of the first and second CCSC device are electrically coupled; and at least one channel reset device, wherein the channel reset device electrically connects a source of charge to the substrate regions of the first and second CCSC devices.

23. A sample and hold circuit as in claim 22 wherein at least one of the CCSC devices is a field effect tran¬ sistor.

24. An analog-to-digital converter, comprising: a comparator having at least one input terminal and one output terminal, wherein the comparator provides a digital output; a first channel coupled semiconductor (CCSC) device having a gate and a substrate region, wherein the gate can be connected to an analog input signal; a second and a third CCSC device, each having a gate and a substrate region, wherein the gates can be connected to one of two reference voltages; a fourth CCSC device having a gate and a substrate region, wherein the gate is connected to the input termi¬ nal of the comparator and wherein the substrate regions of the first, second, third and fourth CCSC devices are ^' electrically connected, whereby a channel is defined; and at least one channel reset device, wherein the channel reset device connects a source of charge to the channel.

25. An analog-to-digital converter as in claim 24 further comprising a fifth CCSC device having a gate and a substrate region, wherein the gate can be connected to one of the two reference signals and the substrate region is connected to the channel.

26. An analog-to-digital converter as in claim 25 wherein at least one of the CCSC devices is a field effect transistor.