WO1996026607A1

WO1996026607A1 - A system for transmitting data over a television channel

Info

Publication number: WO1996026607A1
Application number: PCT/IT1996/000032
Authority: WO
Inventors: Silvano Giuliani; Mosé GIACOMELLO; Maria Teresa Paroli; Giovanni Guardalben; Giannantonio Costermani; Stefano Sartori
Original assignee: Hs-Cast S.R.L.
Priority date: 1995-02-22
Filing date: 1996-02-21
Publication date: 1996-08-29
Also published as: IT1277858B1; AU4842096A; ITRM950108A0; ITRM950108A1

Abstract

A system for transmission of data over a television channel comprising: A) a transmission station, which deals with collecting and preparing the data for transmission and substantially includes: one or more Personal or equivalent kind of Computers, a data conversion software for management of the transmission and enable functions, a card for digital-analog conversion of the signals and their transfer to the transmitter, other accessory equipment, in particular an adapter assembly to the physical medium; B) at least a receive station, which deals with reception of data and substantially includes: a satellite or other standard television antenna or even a coaxial cable connection, a receiver, that can also be included in a Personal or other equivalent kind of Computer, in the form of a suitable card, a receive card for analog-digital conversion of the signals, for checking and correcting the transmission errors, for checking the user enable and passing the data to the Personal Computer, a Personal Computer station or even a simple printer station, as well as accessory equipment, in particular an adapter assembly to the physical medium.

Description

A SYSTEM FOR TRANSMITTING DATA OVER A TELEVISION CHANNEL

This invention broadly relates to a communications system and, more particularly, it concerns a system for transmitting and receiving information, data and video signals, via satellite over a television channel

As it is known, systems have already been suggested for transmitting information over television channels. Such systems have been designed for transmitting information and data together with the video and audio information of conventional television transmission. For instance, TELEVIDEO or TELETEXT systems can be mentioned, which utilize the black lines of the standard television signal.

The system that is subject-matter of this invention is being designed in view of the need to transmit a noticeable information amount, for instance, a newspaper, over a broadcasting type data channel, so as to reach a larger number of users than those that can be reached with existing systems. The commercially available systems, such as TELETEXT and all digital transmission systems, appear to be difficult to use; in fact, the former is unreliable and slow, the latter is expensive.

Within this frame, it is the broad object of this invention to propose a transmission system that is adapted to fulfill the requirements not only connected with transmission of a newspaper, but also with transmission of any kind of data, by means of the standard television channels.

The concerned system, considered in its whole structure, compπses: A) a transmission station, which deals with collecting and preparing the data for transmission and substantially includes: - one or more Personal or equivalent kind of Computers,

- a data conversion software for transmission and enable function management, - a card for digital-analog conversion of the signals and their transfer to the transmitter,

- other accessory equipment;

B) a receive station, which deals with reception of data and substantially includes: - a satellite television antenna or a standard television antenna or even a coaxial cable connection,

- a receiver, that can also be included in a Personal or other equivalent kind of Computer, in the form of a suitable card, - a card for analog-digital conversion of the signals, for checking and correcting the transmission errors, for checking the user enable and passing the data to the Personal Computer,

- a Personal Computer station or even a simple printer station.

From an operation view point, by the system according to this invention, the information containing signal is modulated within the video signal, while all television signal attributes are maintained unchanged. The transmission system utilizes the television signal as a means for transferring or conveying data. In this manner, the television images of a standard television transmission are substituted by signals "conveying" digital information and it should be understood that such information can also contain television images.

Still more particularly, the starting data supplied by a party offering the service and that, therefore, can be defined as the service supplier party, will be established as a set o files, that can be defined under the term "streams" or "flows", which the system organizes in block adapted to be transmitted, such blocks in turn, being divided into packets containing the elementary information. Each packet is not only adapted to contain the basic information, but additionally it contains a set of additional data by which it is possible to identify the users to which such data are addressed, as well as to correct the errors due to corruption of the signals during the transmission.

As concerns the transmission station, it should be noted that many structural approaches can be adopted for its implementation, in view of the fact that its functionality is strictly connected to the kind of services offered (broadcasting, interactive services,....). It is possible to provide transmission stations capable to supply a single service and, therefore, they consist of a single process and transmission unit, or it is possible to provide systems for collecting data coming from different service suppliers and for conveying them over a common transmission channel, for instance the satellite channel.

Aiming at simplifying the description of the concerned system, the case of a single processor dealing with transmitting a single service will be closely examined. The functions thereof can be divided as follows:

- splitting the data into Streams and Blocks: the elements to be transmitted (files, pages, and like) are split into Streams (complete units) , Block (sub- units) and Packets (minimum units) . They are subsequently coded by using a unique key generated by the system itself, and finally preset for transmission, generation of Enable Packets: for each enabled user (that is to say each user having an active subscription) a code is generated to be used in generating the decode key. All of the codes and the decode keys are then assembled into a packet assembly which will be transmitted before the data assembly itself, thereby allowing the receiver stations to enable suitable receive functions, transmission: the information assembly is subsequently transferred to the transmission card together with the sequences and the iterations belonging to the current utilized protocol. The choice of the protocol and, consequently, the selection of the retransmission number is carried out according to the desired safety level. The data sequence, after having been completed with additional data utilized during the reception stage to correct any errors, is transformed into a video luminance signal within the synchronization signals generated by a suitable electronic circuitry included in the same transmission card. The complete output video signal (Base Band Video Signal) is coupled to the television transmitter in order to be broadcast.

As above mentioned, it is possible to utilize satellite, ground (via air) or cable transmitters, without meeting with the need to modify the data transmission system.

As concerns the receiver apparatus and particularly referring to a satellite receiver apparatus, it comprises a receive parabolic antenna, an illuminator, a low noise converter (LNC) and an intermediate frequency television tuner: all of these components are per se known items. The characteristics of the parabolic antenna and of the converter, of course, can be varied according to the power and to the dispersion of the signal broadcast from the satellite transmitter. The intermediate frequency tuner specifically operates to select the signal of the desired channel, upon separating the audio subcarriers that are not utilized in this system. The standard output of the receiver, which could conventionally be utilized for connection to the television apparatus, is coupled to the receive card of the Personal Computer. As far as the receive card is concerned, as above mentioned, the signal received by the television tuner is filtered in the first place from the audio and color subcarπers in order to obtain a basic signal consisting of the luminance and of the horizontal and vertical synchronization components. The synchronization signals are utilized by the receive card in order to align the raster of the received data, while the luminance signal is divided into a variable number of bits (minimum information elements) according to the desired pass band and to the minimum quality of the signal.

Furthermore, some information sequences needed for self-calibration of the receive card (such as the white/black discrimination levels, or one/zero binary values) are included in the signals.

The bit sequence is then assembled into packets that, upon being suitably separated according to their type, are transferred to the data processing software (drive software) , before being definitively forwarded to the applications wherein they will be utilized.

The card drive software is designed in order to make the data reception independent of the physical time during which they are processed by the applications: therefore, it should permit the reception also when the Personal Computer is engaged in other processing activities. The detailed specific functions are as follows:

- recomposition of the data Stream. Since the information sequence transmitted by the main system is comprised of an information assembly addressed to di ferent users, the drive software should recompose the original information sequences addressed to all enabled users; under the term user, an applicative program within a receiver station should be meant, rather than the station itself. In other words, different applicative programs (users) designed for reception of information of different kinds can be included in a Personal Computer,

- Management of Enables and of Decodes. Each Packet sequence by which a complete information (Stream) is composed is preceded by one or more Packets that include the codes of all stations enabled to receive the concerned information. Thus, such information is combined with an enable code uniquely associated to each station. As it will be observed, the drive software processes its specifically associated code by utilizing a suitable hardware component of the card, thereby obtaining a decode key which will be subsequently applied to the received data

- Management of Multiple Applications. For the sake of completeness, it should be underlined that each applicative program that should receive data from the system according to this invention should also record its presence upon operating the program. The codes of the services utilized by each application are recorded by the drive software included in the receive card, thereby enabling the automatic filter function of the data to be received: n this manner, the data flow passing from the receive card to the resident software in the Personal Computer is minimized. A maximum number of ten applications can be contemporaneously present within the concerned system.

Summarizing the structure of the information, it is transmitted as a continuous sequence of bits in the areas subtended between the video synchronization signals and it is divided into Packets containing all logic information needed for correctly identifying the concerned data. A Packet Assembly, which is named Block, is used to identify a set of information items belonging to the same category and processable in extremely short times. Lastly, the Blocks are organized into Streams, which represent the complete information and are independent on the total time needed for reception. Since a Packet represents a minimum transmission unit and it just the item upon which the error correction algorithm is applied , it is believed convenient to supply some details thereof. A Packet is divided into four portions: an initial (header) physic segment (with synchronization function) , an initial logic segment (with identification function) , a user data area as well as an error correction area. The starting physical segment includes all needed information to identify the beginning section of the Packet: this information item, of course, is to be maintained as small as possible, by utilizing, if possible, the video synchronization signal to this effect.

The starting logic segment includes all necessary information needed to identify and to route the Packet: it includes, therefore, the kind identifier, the counter and the total number of Packets for the Stream and for the Block, as well as all information needed to identify the supplier and the kind of the supplied service.

The data area includes the user information that will be transferred from the card to the applicative program.

The error correction area, having preferably a maximum size not greater than 1/3 of the maximum size of the packet, includes all necessary information needed to restore the erroneous data included in the concerned packet. Its length, however, will depend on the utilized algorithm. The enable packet are particularly relevant. In fact, each data stream, before being transmitted, is preceded by a sequence of one or more "enable" packets wherein the lists of the users enabled to receive the concerned information are included. The drive software presets the card so as to receive only the enable packets of Suppliers/Services 8 for which active applications exist. Upon receiving an enabled sequence, the drive software analyses it in order to find out ts own code and, upon finding out its own code, it retrieves therefrom the enable key placed just after it: this key is then coupled to the converter electronic circuitry included in the card, which activates the data decoding algorithm. Any subsequently received information item, in connection with the same stream code, will be directly decoded by the card.

Various methods for transferring the information from the service suppliers to the service users are utilized in the system of this invention. These methods are called "protocols" and are divided into two categories: "broadcast protocols", which comprises all those methods that do not need any information from the users (the most relevant kind of information will presumably be included in th s category) ; and "checked protocols" which are designed for receiving an acknowledgment signal (usually over the land telephone lines) from a plurality or from all of the stations enabled to receive information.

The information transmitted by means of protocols belonging to the broadcast category are relayed to an indefinite (even if known) number of users, only having the capability to receive the service, but not having any possibility to send any message to the service suppliers. Of course, the receiver station shall be operative while the data are being transmitted. Three protocol kinds can be individuated within this method.

Single Broadcast Protocol: this is the main protocol for broadcasting the information each data packet is transmitted only once, with delay factors such that also low cost (and consequently low performance) systems are allowed to receive the complete set of information; Secure Broadcast Protocol: the data packets are transmitted two or more times according to the information responsivity and according to any need to cover areas wherein the satellite signal is particularly low and in broad not favorable conditions;

Continuous Broadcast Protocol: the information is transmitted upon being divided into segments, each of which can be up-dated in different times. As examples of this transmission kind, electronic boards up-dated in real time can be mentioned.

As concerns the "checked" type protocols, they include all those protocols designed to carry out a dialogue with stations enabled to acknowledge the correct reception of information addressed thereto. The return or acknowledgment channel is usually based upon land telephone lines, or it is implemented by utilizing data geographic networks. Three protocol kinds can be individuated within this "checked" category.

Point to point: the most elementary protocol of the "checked" category provides for sending the information to a single users and for waiting for a confirmation signal or an error indication. In this latter case, the information transmission is again carried out. Multi point: all of the users enabled to receive the information acknowledge correct and safe receipt of the information. All blocks not received by even one only user are transmitted again.

Broadcast with check: this method provides for a broadcast type transmission, but the safe and correct reception confirmation is acknowledged by one ore more

"strategic" users positioned in suitable locations in the concerned territory.

As concerns the organization structure of the receiving stations for a newspaper transmission system or like, the receiving stations are divided into three types, the sizes of which are designed according to the utilization requirements:

Print Centers: a satellite receiving equipment, a card and a Personal Computer comprise a basic receiving station wherein the digitized pages of a newspaper are stored, such pages being received by means of the transmission system. In the preferred embodiment, the concerned pages are printer upon a film tape by means of a high grade laser and are subsequently transferred to a print Center which provides for printing them by means of rotary machines the sizes of which are determined by the number of copies to be furnished.

Big Clients: the reception basic station is the same as the above described one and it additionally has a high grade laser printer connected thereto by which a basic copy will be produced operating as a hard copy to produce any further necessary copies.

Single Client: the service user utilizes a low cost receiving station, by means of which the user will be able to consult the newspaper in video and/or printed form, by means of a Personal Computer.

Further details and advantages of this invention will be evident from the following specification by referring to the enclosed drawings wherein the preferred embodiment is shown by way of illustration and not by way of limitation.

In the drawings:

Figure 1 shows a network topology of the transmission and reception system according to this invention;

Figure 2 shows in block diagram form the hardware of the transmission or reception card of the system according to this invention; Figure 3 shows the main blocks of the microprocessor control logic of the transmission card; Figure 4 shows a block diagram of the transmission (tx) logic of the transmission card of the system according to this invention;

Figure 5 shows a block diagram of the timing generator of the transmission card;

Figure 6 shows a block diagram of the time base generator of the transmission card;

Figure 7 shows a block diagram of the digital waveform generator of the transmission card of the system according to this invention;

Figure 8 shows a block diagram of the transmission data formatting section of the transmission card;

Figure 9 shows a block diagram of the digitally controlled modulator of the transmission card;

Figure 10 shows a block diagram of the analog conditioning logic of the transmission card;

Figure 11 shows a block diagram of the auxiliary logic of the transmission card; Figure 12 shows a connector for the B/N composite video signal relating to the transmission card;

Figure 13 shows a connector for the B/N composite video signals, the frame synchronization signals, the row synchronization signals and the transmission enabling signals of the transmission card; Figure 14 shows a block diagram of the reception (rx) logic of the reception card to be used in a system according to this invention; Figure 15 shows a block diagram of the analog conditioning logic of the reception card;

Figure 16 shows a block diagram of the timing generator of the reception card;

Figure 17 shows a block diagram of the time base generator of the reception card; Figure 18 shows a block diagram of the digital waveform generator of the reception card of the system according to this invention;

Figure 19 shows a block diagram of the reception data formatting section of the reception card;

Figure 20 shows a block diagram of the sin/cos digital generator of the reception card according to this invention; Figure 21 shows a block diagram of the auxiliary logic of the reception card;

Figure 22 shows a schematic view of a system for contemporaneous transmission of data and images according to this invention; and Figure 23 illustrates the operation principle of a system for contemporaneous transmission of data and images according to Figure 22.

By referring now to the drawings, the system for transmission of data over a television channel according to this invention is a communication system based upon plug-in additional cards for Personal Computer or other similar and equivalent computer. It is designed so as to employ two kinds of cards: a transmission card and a reception or receiver card. The network typology of the whole system is shown in Figure 1. It comprises a transmission system that transmits information to a number N of receiving systems which receive it in broadcast.

The transmission system comprises the following component sections: a Host operating Personal Computer, a transmission card, as well as a transmission adapter to the physical medium.

The reception system comprises the following component sections: a Host operating Personal Computer; a reception card, as well as a reception adapter to the physical medium. The main activity of the Host Personal Computer is to prepare and transmit Packets from its own memory to the buffer memory of the transmission card. It is a duty of the Host Personal Computer to supply the transmission card with the data to be transmitted with such an arrangement that any receiver has just the mean data flow that it can sustain.

A block diagram of the transmission or the reception card is shown in Figure 2. The core of the transmission card is a microcontroller, such as MOTOROLA 68360, which includes a 32 bit central processor CISC, an auxiliary processor RISC optimized for serial transmission and many necessary peripherals, among which we can mention: two DMA memories, four timers, and interrupt controller and a memory controller. The parallelism of the data bus included in the transmission card is 32 bits, while the address bus parallelism is 28 bits.

Four memory blocks can be individuated: a bootstrap memory, a data and program memory, a FIFO (first-m, first-out) type memory, a DPR (Dual Port RAM) memory.

The bootstrap memory consists of an EPROM or

Flash-EPROM or even EEPROM chip, of 8K x 8 bit size, but also sizes of 16/32/64/128K x 8 bits are possible.

This memory is only used during a bootstrap operation and, therefore, it can be a very slow access memory.

The data and program memory consists of four 34 K x 8 bit size SRAM chips, but also memories having a size of 128K x 8 bits can be used, for a total size of 32K x 32 bits. This memory is sufficiently fast for enabling a normal operation of the concerned microcontroller at zero wait states.

The FIFO type memory consists of four FIFO access SRAM chips of a size 4K x 8 bits, but also memories having a s ze of 8/16K x 8 bits can be used, for a total size of 4K x 32 bits. This memory is sufficiently fast for enabling a normal operation of the microcontroller at zero wait states and it is utilized as a buffer memory or a transit memory for transferring large blocks of data from the Personal Computer to the microcontroller.

The DPR memory consists of a dual access port

SRAM chip, having a size of IK x 8 bits, but also memories of sizes 2K x 8 bits can be used. This memory is sufficiently fast for enabling a normal operation of the microcontroller at zero wait states and it is employed for storing the pattern registers. Such registers can be contemporaneously accessed from the microcontroller as well as from the Personal Computer.

The block designated as interface control logic with ISA bus is utilized for managing the FIFO and DPR memories, besides permitting the interface with the ISA type bus of the Personal Computer.

Two blocks aid the microcontroller in its vital functions: an error search and elimination logic (debug) and a control logic. A transmission (tx) logic can be recognized in the block diagram, for implementing the front-end for matching to external transmission interface and an auxiliary logic that supports the microcontroller in its processing function.

The supplies within the card, both digital and analog supplies, are extracted from the ISA bus by means of a supply block, that can be implemented with linear type regulators or by switching type regulators. The control logic of the microcontroller provides the clock signal for operation as well as the power-up / reset under applied voltage functions.

By referring to Figures 2 and , it can be observed that the front-end for matching to the transmission interface is implemented by means of the transmission logic, as detailedly shown in Figure 4. It is connected to the microcontroller (μC) by means of two serial channels: a data channel CH D and a set-up channel CH S. The set-up channel is utilized to transmit the communication pattern parameters during the last interval available at the end of an even half- frame. The data channel is utilized for transmitting data during the remaining available intervals.

The following essential components can be recognized in the block diagram of Figure 4 : a timing generator; a transmission data formatting module; a video digital-analog converter (DAC) ; an analog conditioning module and an output connector C.

The timing generator can be implemented by means of an ASIC type device and it is designed in order to generate all timing signals needed in the transmission system, namely: 60 MHz: system clock; TCLKD: transmission clock for the data channel; TCLKD(?): transmission clock for the set-up channel; CTSD_: transmission enable signal for the data channel; CTSS_: transmission enable signal for the set-up channel; CSYNC: video synchronization composite signal CBLANK: video deletion composite signal; VSYNC vertical (or frame) synchronization signal; HSYNC horizontal (or row) synchronization signal; TXENA transmission enable signal. The transmission data formatting module can be made by an ASIC device and is utilized for formatting the data to be transmitted by generating a digital output; TDX (0 - 7) : data to be transmitted with a 8 bit resolution; according to the signals: TXDD: data item to be transmitted over the data channel; TXDS: data item to be transmitted over the set-up channel; RTSD_ : transmission request by the data channel; RTSS_: transmission request by the set-up channel.

The video DAC converter is a digital-analog converter with video speed and 8 bit resolution. It converts digital signal TXD (0 - 7) into an analog signal VIDSYNT, video composite B/W signal synthesized according to the timings furnished by signals 60 MHz, CSYNC and CBLANK.

The analog conditioning block is a completely analog block that is utilized to match the input signal VIDSYNT to the levels of the video composite B/W (VIDEO) signal.

Also two output connectors C and CC can be observed.

As concerns the timing generator, which is available in two embodiments for the PAL and the NTSC standards, respectively, as it can be observed in

Figure 5, it comprises a time base generator and a digital waveform generate.

The time base generator detailedly shown in Figure 6 generates the time bases of 60 MHz, 10 MHz and 6 MHz. The 60 MHz base is obtained by means of an oscillator, while the 10 MHz and 6 MHz bases are synthesized by means of synchronous counters. The 6 MHz counter is synchronized by signal SYNCRES. The digital waveform generator detailedly shown in Figure 6 generates the timing signals: TCLKD, TCLKS, CTSD_, (TSS_, CSYNC, CBLANK, VSYNC, HSYNK, TXENA; SYNCRES, based upon clock signals of 10 MHz and 6 MHz. The digital waveform generator is formed by a "run-length encoder" type machine, which generates an overassembly of all transitions of the video composite synchronization signal and by a set of state machines which, starting from such a signal, generate the output ones. The first machine is based upon two resettable counters and upon two ROM type memories, a first ROM memory wherein the durations of the high and low levels are stored and a second ROM memory that stores the numbers thereof.

The address encoder block enables the size of the first ROM memory to be reduced and the state machines are of the "one hot encoding" type. 17 The clock signals TCLKD and TCLKS are continuous. Signal CTSD_ permits the transmission only within the limits of the luminance modulation of complete and visible lines. In particular, all the rows around the frame synchronization point and the two uncompleted rows are excluded. The starting rows and the end row of the unavailable for data and addressed to the video image area are defined by two program registers. This information are also utilized for generating signal TXENA. Signal CTSS_ permits the transmission only within the limits of the luminance modulation of the last complete and visible last line of the even half-frame.

As concerns the transmission data formatting section, it comprises the component parts shown in Figure 8 and namely: a multiplexer for the transmission clock; a transmission data multiplexer; a multiplexer for a transmission request; a demultiplexer of the in- phase and the quadrature phase signals; a di ferential encoder; a delay line: a numerically or digitally controlled modulator.

The above mentioned three multiplexer circuits carry out a selection of the transmission clock TCLK, of the transmission data item and of the transmission request RTS_ among those pertaining to the data channel (TCLKD, TXDD, RTSD_) and those pertaining to the set-up channel (TCLKS, TXDS, RTSS_) . Such a selection is effected according to the transmission enable signals CTSD_ and CTSS_ coming from the timing generator. The above mentioned demultiplexer separates the in-phase data A(T) from the quadrature data B(T) for the QPSK type modulation. Signal TXD represents the input data, signal TCLK provides the operative clock, while signals CTSD_ and CTSS_ are utilized for initialization purposes.

The differential encoder module encodes the serial stream of data A(T) and B(T) in order to enhance the average distribution of the transmission power and in order to solve the ambiguity 0°- 180° for any receive decision. Signals PREI (T) and Q(T) bear the serial flow of the encoded data, signal TCLK furnishes the operation clock signal, while signals CTSD and CTSS_ are utilized for initialization purposes.

The delay line introduces a fixed delay between the in-phase data and the quadrature data so as to realize the so-called "offset keying" modulation as requested by the OK-QPSK variation of the QPSK type modulation. The delay line generates, starting from the input data PREI(T), a delayed replica I(T) based upon the clock signal TCLK.

The numerically controlled modulator generates the data to be transmitted TXD [0:7] coded with a resolution of 8 bits, based upon signals I (T) and Q(T) by utilizing signals RTS_, CTDS_ and CTSS_, for framing purposes, together with clock signals TCLK and 60 MHz. The numerically controlled modulator is detailedly illustrated in Figure 9 and it is designed so as to include the following components: state machine for phase control, a XOR matrix for inversion of the address, a ROM memory for the sinus function and a XOR matrix for inversion of the sign. The state machine for phase control is of the

"one shot encoding" type and is utilized to generate the addresses and the sign inversion command for reading the look-up table as implemented by the ROM memory containing the sinus function and by said two XOR matrices.

The analog conditioning block comprises the section illustrated in Figure 10, namely a low pass filter, a gain adjustment block, an offset adjustment block and a buffer/inverter. These block are completely analog blocks and are utilized to match the input signal VIDSYNT to the levels of the video composite B/W signal, namely the VIDEO signal. The low pass filter is used to interpolate the samples of the waveform synthesized by the digital/analog converter section (DAC) , to cut-off any spectral components outside the video band as well as to carry out the control function of the edge slope of the synchronization pulses.

The gain adjustment block is utilized to match the output signal amplitude, while the offset adjustment block is utilized for calibration of the reference level of same. The combined operations of the two adjustment blocks, by means of the selection VOUT_ RANGE, permits an output of 1 Volt on 75 ohms or 0.7 Volts on 75 ohms.

Lastly, the buffer/inverter block makes available the VIDEO modulation output positive or negative according to the VIDEOMOD selection.

The auxiliary functions of the transmission card are defined in Figure 11, namely the memory containing the unique serial number for each card and the encoder to be utilized for error detection and correction.

The memory can be designed as a serial EEPROM memory, protected against copying, or with a PAL

(Programmable Array Logic) device, with a safety fuse. For interfacing purposes, SPI (Serial Peripheral Interface) device of the microcontroller can be used. The EDAC (Error Detection And Correction) encoder can code the data to be transmitted according to one of the following modes: 16 bit CRC, 32 bit CRC, EDAC at Hamming distance. Suitable algorithms are available for all above transmission modes. Said EDAC encoder, controlled by said microcontroller and seen by the same as a memory mapped co-processor, can be realized by an ASIC type device. The ISA interface control logic permits the microcontroller to be interfaced to the Personal Computer by means of an ISA type bus. From a practical view point, such a logic assembly comprises the following functional blocks: control registers, status registers, DPR memory control logic, FIFO memory control logic, a logic for controlling the interrupt to/from said ISA bus, a logic for controlling the microcontroller DMA, a decode and buffer logic for interfacing to the ISA bus.

Also said ISA bus interfacing control logic can be realized by means of an ASIC type device. The pattern registers are utilized for containing the operation and initialization parameters of the transmission card. Read and write operations in said registers can be carried out both by the Personal Computer and by the microcontroller; said registers can be placed in said DPR memory.

The control registers are utilized in order to make the transmission card carry out certain operations. Write operations in said registers can be carried out by the Personal Computer, while read operations can be carried out therein by said microcontroller. They are located in the ISA interfacing control logic.

The status registers are utilized in order to let the Personal Computer get informed about the operation of the transmission card. Read operations can be carried out in these registers by the Personal

Computers, while write operations can be carried out therein by said microcontroller; they are located in the ISA interfacing control logic. The transmission interface of the transmission card is of a B/W composite video type. It is realized by means of a BNC type connector having a pin arrangement as indicated in Figure 12, and with a female 9 pole D type connector MIL-C-24308, having a pin arrangement as indicated in Figure 13. As concerns the B/W composite video signal of the transmission card, the relevant levels are those of a B/W composite video signal, standardized at 1 Volt on 75 ohms or 0.7 Volts on 75 ohms. The selection is carried out during the assembly of the transmission card. As concerns the frame synchronization signals, the row synchronization signals and the transmission enable signals, the transmission levels are the TTL levels.

The interface between Host Personal Computer and the transmission card is of ISA bus type with input/output on a 16 bit port. It is preferably realized by means of a card-edge type connector with a suitable pin arrangement.

As concerns the structure of the receive card, its block diagram is illustrated in Figure 14. The core of the receive card comprises a microcontroller, preferably of MOTOROLA 68360 type. It integrally includes a 32 bit central processor, a RISC auxiliary processor optimized for serial transmission and a number of necessary peripherals, among which, in particular, two DMA components, four timers, an interrupt control block and a memory control block can be mentioned.

The parallelism of the internal bus of said receive card amounts to 32 bits, while the parallelism of the address bus amounts to 28 bits. Four memory blocks can be individuated, namely a bootstrap memory, a data and program memory, a FIFO (First-In, First-Out) type memory and a DPR (Double Port RAM) memory.

The bootstrap memory is realized by means of a EPROM chip or a Flash-EEPROM or a 8K x 8 bit Size EEPROM, but sizes such as 16/32/64/128K x 8 bits are supported as well. This memory is utilized only during the bootstrap stage and, therefore, it can also be a very low access memory. The data and program memory is realized by means of 4 SRAM chips each having a size of 32K x 8 bits (but a memory having a capacity of 128K x 8 bits is supported, as well) for an overall capacity of 32K x 32 bits. This memory is sufficiently fast for enabling a normal operation of the microcontroller at zero wait states. The FIFO type memory is realized by means of 4

SRAM chips with FIFO type access, each having a capacity of IK x 8 bits (but a memory having a capacity of 2/4K x 8 bits is supported, as well) for an overall capacity or size of IK x 32 bits. This memory is sufficiently fast for enabling a normal operation of the microcontroller at zero wait states and it is utilized as a transit or buffer memory for transferring big blocks of data from the microcontroller to the Personal Computer. The DPR memory is realized by means of a SRAM chip with double-port access, having a capacity of IK x 8 bits, but also a memory with a capacity of 2K x 8 bits is supported, as well. This memory is sufficiently fast for enabling a normal operation of the microcontroller at zero wait states and it is utilized for storing the pattern registers. Such registers are contemporaneously accessible both from the microcontroller and from the Personal Computer.

The block designated as ISA interface control logic is utilized to manage the FIFO and DPR type memories, besides enabling interfacing the Personal Computer to the ISA type bus.

Two blocks help said microcontroller in carrying out its vital functions, namely the error searching and eliminating logic and the microcontroller control logic.

The reception logic implements the reception external interface matching front-end and the auxiliary logic helps the microcontroller in carrying out its processing unctions.

The supplies on board of the card, both the digital and the analog ones, are achieved by means of said ISA bus through the supply block, which can be realized by means of linear type or of switching type regulators.

Just as in the transmission card, the microcontroller control logic provides, the operation clock signal and the power-up/reset under voltage functions. The clock signal is a 25 MHz signal and it can be furnished either by means of an oscillator, or by means of a quartz item, in combination with the PLL/synthesizer of clock signal internally included to the microcontroller.

The front-end for matching to the receive external interface is realized by means of the receive logic. It is connected to the microcontroller by means of two serial channels: a data channel (that can be patterned as 6/3/1.5 Mbits/s) : and a set-up channel

(patterned as 1.5 Mbits/s).

The set-up channel is utilized for receiving the pattern parameters of the communication during the last interval available at the end of an even half- frame. The data channel is utilized in order to receive data during the other available intervals.

A block diagram of the receive logic is shown in Figure 1 . The following essential components can be identified therein: an input connector; an analog conditioning section; a synchronization separation; a luminance separator; a timing generator; a video analog/digital converter; a reception data formatting section. The video signal, namely the video composite

B/W signal is coupled to the input connector, according to the already set forth specifications related to the hardware interfaces.

The analog conditioning block is a completely analog block which is utilized in order to match the VIDEO input signal to the levels of the VIDEO signals, namely the video composite B/W signals containing only the synchronization information, and VIDEOL, namely the video composite B/W signals containing only the luminance information, these signals being utilized for the subsequent blocks. The synchronization signal separating block is a mainly analog block that is utilized to separate, from within the VIDEOS signals, the synchronization signals CSYNC, namely the synchronization video composite signal, VPULSE, namely the signal containing the vertical (or frame) synchronization pulse, and the ODD/EVEN signal, namely the signal indicating the presence of the odd/even half-frame.

Also the luminance separator block is a mainly analog block that is utilized to individuate, within the VIDEOL signal, the DATAIN signal, namely the signal containing the data encoded as luminance information, by employing the timing as furnished by the CBLANK signal, that is the blanking video composite signal.

The timing generator can be realized by means of an ASIC type device and it is utilized to generate all necessary timing signals needed in the receive stage: 30 MHz: the system clock; RCLKD: receive clock for the data channel; RCLKS: receive clock for the set¬ up channel; CDD_: receive enable for the data channel; CDS_: receive enable for the set-up channel; CBLANK; starting from the information furnished by CSYNC signals; VPULSE; ODD/EVEN; El: error in recognition of the in-phase signal; EQ: error in recognition of quadrature signal. The video ADC block comprises an analog/digital converter at video rate with 8 bits resolution. It converts the analog signal DATAIN into a digital signal DATAIN [0:7], that is the received data, encoded with 8 bit resolution, based upon the timing signals furnished by the 30 MHz signal.

The received data formatting section can be realized by means of an ASIC type device and it is utilized for formatting the received data. This section generates the following outputs: RDD: data item received from the data channel; RDS: data item received from the set-up channel; El; EQ; based upon the detain [0:7] signal, according to the timing signals provided by the 30 MHz signals RCLKD, LCLKS, CDD_, CDS_.

The analog conditioning section includes the components illustrated in Figure 15: the buffer/inverter; the gain adjustment block; the offset adjustment block and the anti-aliasing low-pass filter. These blocks are completely analog and are utilized to match the input signal VIDEO to the levels of signals VIDEOS and VIDEOL.

The buffer/inverter block enables an input with positive or negative video modulation to be used, according to the VIDEOMOD selection. Its output is signal is simply formed by said signal VIDEOS.

The gain adjustment block is utilized to match the input signal amplitude, while the offset adjustment block permits its reference level to be calibrated. The combined operation of the above two blocks, by means of the VIN_RANGE selection, permits a 1 Volt input on 75 ohms or a 0.7 Volt input on 75 ohm.

The anti-aliasing low-pass filter is utilized to cut off all those spectral components located outside the video band present in the input signal. Signal VIDEOL is the output signal of this block.

As far as the timing generator of the receive card is concerned, two different embodiment of the timing generator are possible more precisely an embodiment according to PAL standard and an embodiment according to NTSC standard. The structure is the same for both embodiment, but the generated timing signals are different. The timing generator is comprised of the components illustrated in Figure 16, namely a time base generator and a digital waveform generator. The time base generator, as detailedly illustrated in Figure 17, generates the time basis: 30 MHz, 10 MHz and 6 MHz.

The 30 MHz time is synthesized starting from a 60 MHz oscillator by means of two Digital Phase Locked

Loops (DDLL) . The first of these circuits, named "row"

DPLL generates an output clock signal in-phase with signal HSYNC. The second circuit, named "fine" DPLL generates the 30 MHz output clock signal in-phase with the received symbols. To obtain this result, it utilizes El and EQ information. The 10 MHz and 6 MHz timing signals are synthesized by means of synchronous counters. The counter used to generate the 6 MHz timing signal is synchronized by means of the synchronous reset signal SYNCRES.

The digital waveform generator, as detailedly illustrated in Figure 18, generates the timing signals: RCLKD, RCLKS, CDD_, CDS_, CBLANK, HSYNC, SYNCRES, based upon the 10 MHz and 6 MHz timing signals and based upon the information contained in signals CSYNC, VPULSE and ODD/EVEN.

The digital waveform generator is realized by means of a "run-length encoded" type machine that generates an overassembly of all transitions of the video composite synchronization signal and by means of a set of state machines that process said signal to produce the output signals. The starting state machine is utilized to align the synchronization signals synthesized within the timing signal generator to those contained in the received signal. The first above quoted machine is based upon two presettable counters and upon two ROM memories: a ROM memory containing durations of the high and low levels and a ROM memory containing the number of the high and low levels. An address encoder permits the size of the first ROM memory to be reduced and all other state machines are of the "one hot encoding" type. Clock signals RCLKD and RCLKS are continuous.

Signal CDD_ permits reception only within the luminance modulation range of the complete and visible lines. In particular, the rows in the frame synchronization range and the two incomplete rows are excluded . The begin row and the end row delimiting the range not available for the data and dedicated to the video image area are defined by means of two programming registers. Signal CDS_ permits reception only within the luminance modulation of the last complete and visible row of the even half frame.

The data formatting section is comprised of the components illustrated in Figure 19 and, more precisely, a multiplexer for the receive clock signal, a demultiplexer for the receive data, as well as a multiplexer for in-phase and quadrature data, a differential decoder, a delay line, a numeric sin/cos generator, a correlator for in-phase data, a correlator for quadrature data and a digital equalizer filter. The mentioned first multiplexer effects a receive clock selection RCLK between the data channel clock RCLKD and the set-up channel clock RCLKS. Such a selection is carried out according to the reception enable signals CDD_ and CDS_ from the timing generator. The mentioned duplexer separates the data pertaining to the data channel RDD from those pertaining to the set-up channel RDS according to the reception enable signals CDD_ and CDS_ from the timing generator. Signal RD represents the input data. The second mentioned multiplexer recombines the in-phase data A(T) with the quadrature ones B(T) for a QPSK type modulation. Signal RD represents the output data; signal RCLK provides the operation clock signal, while signals CDD_ and CDS_ are utilized for initialization.

The mentioned differential decoder effects the necessary differential decode operation upon said serial flow or stream of all received data. Signals I(T) and POSTQ(T) permit a serial flow of decoded data, signal RCLK supplies the operation clock signal, while signals CDD_ and CDS_ are utilized for initializing purposes.

The above mentioned delay line introduces a fixed delay between the in-phase and the quadrature data, so as to realign them after the so-called "offset keying" as requested by the OK-QPSK embodiment of the QPSK type modulation. The delay line generates, starting from the input data Q(T) , a delayed replica POSTQ(T) based upon the clock signal RCLK.

The numeric sin/cos generator generates the reference functions of sine sin [0:7] and of cosine cos [0:7] encoded with 8 bit resolution, by utilizing signals CDD_ and CDS_, together with said clock signals

RCLK and 30 MHz.

The details of the above numeric sin/cos are set forth in Figure 20 and the following components can be acknowledged: a phase control state machine, a XOR matrix for inverting the address of the sine function, a ROM memory for the sine function, a XOR matrix for inverting the sign of the sine function, a XOR matrix inverting the sign of the cosine function, a ROM memory for the cosine function and a XOR matrix for inverting the sign of the cosine function.

The state machine for phase control is of a "one shot encoding" type and it is utilized to generate the addresses, the address inversion command and the sign inversion command for reading the search look-up tables implemented by means of ROM memories containing the sine and cosine functions and by means of four XOR matrices.

The in-phase data correlator effects correlation between the input data DATA [O...] and the cosine function [0:7], in order to decide as to the value of the data item I (T) . The above mentioned correlator needs in its operation clock signal RCLK at 30 MHz and also generates a jitter error signal El which is utilized as a feedback to the above fine DPLL. The correlator for the quadrature data items carries out a correlation between the input data item DATA [0:7] and the sine function sin [0:7] in order to determine the value of data item Q(T) . The above mentioned correlator needs in its operation clock signals RCLK and 30 MHz and also generates a jitter error signal EQ which is utilized as a feedback to the above fine DPLL.

The digital equalization filter carries out a digital equalization filtering in order to enhance only the interest frequencies within the spectrum. As far as the auxiliary logic of the receive card, the auxiliary functions of such a card are defined in Figure 21, namely a memory containing the unique serial number for each card, an error detecting and correcting encoder, a fast table correlator and a decryption unit.

The memory can be realized as a serial EEPROM memory protected against copying or by means of a PAL

(Programmable Array Logic) device provided with a safety fuse. The SPI (Serial Peripheral Interface) interface of the microcontroller can be used for interfacing purposes. The error detecting and correcting decoder (EDAC) can decode the received data according to one of the following operation modes: CRC at 16 bits, CRC at 32 bits, EDAC at Hamming distance. The fast table comparator can rapidly check whether the introductory segment of a received packet is present in the enable tables. The decryption unit can decrypt the received data according to a given key. The EDAC decoder, the fast table comparator and the decryption unit, as controlled by said microcontroller and seen therefrom as a co-processor mapped in the memory, can be realized as an ASIC type device. The ISA interface control logic permits the microcontroller to be interfaced to the Personal

Computer by means of an ISA type bus. From a practical view point, such a logic assembly comprises the following functional blocks: control registers, status registers, a DPR memory control logic, a FIFO memory control logic, a logic for controlling the interrupt to/from said ISA bus, a logic for controlling the microcontroller DMA, a decode and buffer logic for interfacing to the ISA bus.

Also said ISA bus interfacing control logic can be realized by means of an ASIC type device.

The pattern registers are utilized for containing the operation and initialization parameters of the transmission card. Read and write operations in said registers can be carried out both by the Personal Computer and by the microcontroller; said registers can be placed in said DPR memory.

The status registers are utilized in order to let the Personal Computer get informed about the operation of the transmission card. Read operations can be carried out in these registers by the Personal Computers, while write operations can be carried out therein by said microcontroller; they are located in the ISA interfacing control logic.

The receive interface of the receive card is of a video composite B/W type. It is realized by means of a RCA type connector having the same pin arrangement as in Figure 12. As far as the video composite B/W signal is concerned, the levels are the same as in the video composite B/W signal standardized at 1 Volt on 75 ohms or at 0.7 Volt on 75 ohm. This selection is effected during the assembling stage of the receive card. The amplitude of the luminance signal modulated for data transmission should be at least 80% of the image modulation range, namely of the area defined between the white level and the black level. The interface between the Host Personal

Computer and the receive card is formed by an ISA bus with input/output on a 16 bit port. It is preferably realized by means of a card-edge type connector with suitable pin arrangement. The software related to the transmission system, considered in its whole, can be divided into three modules: a software module resident in the transmission card, a module for the device drivers resident in the Host Personal Computer and an applicative software module resident in said Host Personal Computer.

Also the software related to the receive system, considered as a whole, can be divided into three modules: a software module resident in the receive card, a module for the device drivers resident in the Host Personal Computer and an applicative software module resident in said Host Personal Computer.

As concerns the bootstrap procedure, is consists in that, after the reset stage in the transmission or reception card, the stoppage of the basic firmware contained in the bootstrap memory is started. Such firmware is automatically copied into the program memory and upon completing this step, the code execution step is carried out only in the program memory. OPERATION MODE OF THE TRANSMISSION CARD The transmission card receives the information card from the Host Personal Computer and, after having processed them transmits them to the receive systems. The transmission of the information to the receive systems is serially carried out by modulating a video composite B/W signal or by acting only upon the luminance signal.

The transmission card has only two operation modes: the test mode and the normal mode. In both operation modes, the modulation is carried out according to PAL or NTSC standard; this choice, however, is static, which means that the concerned card is factory prearranged in view of the requested standard.

When the operator wishes to dynamically manage the characteristics of the communication channel, he can select the desired transmission speed and a different error correction method can be associated to each packet. From a construction view point, each transmission card has a unique and not volatile serial number, that can be read and utilized by the software. The usual communication mechanism between Personal Computer and transmission card is of FIFO type. A further mechanism is available for transferring privileged packets within the transmission card thereby realizing less latency within the card itself. Such a mechanism is designated as HPC (High Priority Channel) . The Host Personal Computer transfers to the transmission card the complete packet together with some attributes, namely the indication whether the packet is to be processed in FIFO mode or in HPC mode, as well as the parameters relating to the error correction algorithm to be utilized. The Host Personal Computer is adapted to read both the status of the FIFO buffer and the status of the packet buffer within the card. The following sources can be associated to the interrupt line toward the Host Personal Computer: void FIFO buffer, half- filled FIFO buffer, filled FIFO buffer, N packets in the packet buffer within the card. In the test mode, the transmission card continuously transmits test packets without any intervent of the Host Personal Computer.

In the normal operation mode, the transmission card transmits the data packets transferred thereto from the Host Personal Computer. When the transmission buffer in the card is void, the packets are transmitted in order that no pause is inserted in the transmission. Furthermore, it is possible to define a transmission interleaf factor between the packets furnished by the Personal Computer and the test packets inserted from the card. As far as the time diagrams of the transmission card are concerned, the data for the video interface are outputted only upon the luminance signal and consequently within the intervals existing in the row synchronization signals. As it is defined in the PAL and NTSC standards, only complete and visible rows are utilized for transmission of data. In particular, all rows near the vertical synchronization signal are excluded together with the two incomplete rows of the even and odd half-frames. The transmission of a packet always starts at the begin of a row and, if it terminates before the end of a row, the remaining portion of the row itself is not utilized for transmission of another packet. The last interval available at the end of an even half-frame is dedicated to transmission of the communication pattern parameters for the subsequent frame. Among the communication pattern parameters, one can mention the speed, the beginning row of an area not available for data and the end row of an area not available for data. A transmission of these parameters is carried out with such a procedure as to guarantee a correct reception. This procedure is a static one and in particular the operation speed is the lowest speed among all available speeds, for compatibility reasons. Since the luminance signal is exclusively modulated, the video composite B/W signal generated by the transmission card is adapted to be received by any device compatible with the PAL and NTSC standards, according to the kind of timing generator utilized therein. The video output of the card is presettable both in respect of the timing signals and in respect of the video modulation among the option available under the television broadcasting rules.

Both the transmission of data rows and the transmission of video image rows can co-exist within a frame synchronization interval. The video image is defined as an interval existing between a beginning row and an end row. The data row are located in those portions of the frame that are free from images.

The system for contemporaneous transmission of data is illustrated in Figure 22 and its operation principle is illustrated in Figure 23.

As concerns the modulation method of the useful area of the luminance signal for transmission of data, the modulation kind during the transmission should fulfill the following requirements: very large available video band and noise immunity (in particular the noise affecting the amplitude of the signals) , as well as the performance invariability on different television media (land VHF/UHF, satellite 10 - 12 GHz, cable TV) and the television broadcasting rules set forth the extension of the video band for modulation of the luminance signal. To fulfill all these requirements and to optimize the utilization of the capacity of the concerned channel, it is preferable to utilize a QPSK type modulation.

OPERATION MODE OF THE RECEIVE CARD The receive card receives information transmitted by the transmission card and, after having processed them, makes them available to its Host Personal Computer. The reception of the information coming from the transmission card is serially carried out by demodulating a composite video B/W signal or by decoding only the luminance signal.

Just as the transmission card, the receive card has two operation modes, as well : the test mode and the normal mode. Both operation modes effect demodulation in PAL or NTSC standard; however, such option is a static one, since the card is preset for the requested standard during manufacturing thereof in factory. The receive buffer management is based upon a mixed interrogation/interruption mechanism in order to furnish information regarding the void, filled or full state of the buffer.

Aiming at dynamically menage the characteristics of the communication channel, the receive card automatically retrieves the transmission mode of the transmission card for the subsequent frame by reading the communication pattern parameters contained in the last available interval at the end of an even half frame.

From a construction point of view, each receive card has an unique and not volatile serial number, that can be read and utilized by the involved software.

An interrupt synchronization mode exists to notify the availability of information to be read to the device drivers. When the Host Personal Computer permits the receive card to completely fill its buffer component with packets, starting from that instant all new packets are lost, unless further room is made available in the above mentioned concerned buffer.

In a normal operation mode, the receive card processes the information received and compares the packet headers with some enable tables. Only those packets that are considered from such tables are made available to the Host Personal Computer. Furthermore, the following operation are carried out: - the overall count of the received packets is computed,

- the count of the accepted packets sorted according their status is computed,

- the count of any packets lost or received and not processed due to overrun is computed.

As concerns the video interface, the data items are exclusively received on the luminance signal, that is to say in the intervals existing between the row synchronization signals. Only complete and visible rows as defined in the PAL and NTSC standards are utilized for receiving data. In particular, the rows existing about the vertical synchronization signal as well as the two incomplete rows of the even and odd half frames are excluded. The last interval available at the end of an even half frame contains the communication pattern parameters for the subsequent frame.

Among the communication pattern parameters, the speed, the beginning row of an area not available for the data and the end row of an area not available for the data can be mentioned. The reception of these parameters takes place according to the above already defined operation mode.

Since the luminance signal is exclusively demodulated, the receive card receives a composite video B/W signal generated by devices compatible with either PAL or NTSC standards, according to the type of the installed timing generator. The video input of the card is presettable either in respect of the timing or in respect of the video modulation type among the options furnished by the television broadcasting rules. Of course, on installing the receive card, the operator should match the timing patterns and the video modulation type in order that they re coherent to the associated transmission card. Both the data row transmission and the video image transmission can coexist within the frame synchronization slot. The video image is defined as an interval interposed between a beginning row and an end row. The data rows, therefore, are connected with those portions of the frame that are left free of images. The receive card receives the data rows and it does not consider the video image rows. During reception, the synchronization signals are not regenerated and, therefore, any loss of synchronization pulses cannot be tolerated.

As far as the signal demodulation during reception is concerned, the receive card demodulates the QPSK type received signals in variant OK-QPSK with a symbol frequency of 3 MHz. The capacity of such a communication channel is 6 Mbits.

The preferred embodiment of this invention has been hereinbefore described and some modification have been suggested, but it should be understood that those skilled in the art can make other variations, modifications and changes to the details and to the components to be used without departing from the protection scope of this invention.

Claims

CLAIMS 1.- A system for transmission of data over a television channel comprising:

A) a transmission station, which deals with collecting and preparing the data for transmission and substantially includes:

- one or more Personal or equivalent kind of Computers,

- a data conversion software for management of the transmission and enable functions,

- a card for digital-analog conversion of the signals and their transfer to the transmitter,

- other accessory equipment, in particular an adapter assembly to the physical medium; B) at least a receive station, which deals with reception of data and substantially includes: a satellite or other standard television antenna or even a coaxial cable connection,

- a receiver, that can also be included in a Personal or other equivalent kind of Computer, in the form of a suitable card,

- a receive card for analog-digital conversion of the signals, for checking and correcting the transmission errors, for checking the user enable and passing the data to the Personal Computer,

- a Personal Computer station or even a simple printer station,

- as well as accessory equipment, in particular an adapter assembly to the physical medium.

2.- A system for transmission of data over a television channel according to claim 1, characterized in that said transmission and receive cards, respectively, are based upon a microcontroller that integrally includes a central processor, an auxiliary processor and peripheral functions comprising two DMA memories, four timers, an interrupt controller and a memory controller, said microcontroller having associated thereto:

- a bootstrap memory,

- a data and program memory, - a FIFO type memory,

- a DPR type memory, a logic block for controlling the ISA interface which deals with managing said FIFO and DPR type memories and with interfacing with the ISA bus of the Personal Computer,

- a logic block for searching and correcting errors,

- an auxiliary logic block,

- a microcontroller control logic block for providing the operation clock function as well as the power-up/reset under voltage, and

- a transmission logic block or a receive logic block, respectively, by which the front-end for matching to the external transmission or receive interface, respectively, is implemented.

3.- A system for transmission of data over a television channel according to claim 2, characterized in that said bootstrap memory consists of an EPROM or Flash-EPROM or even EEPROM chip, of 8/16/32/64/128K x 8 bits, it is only used during a bootstrap operation and it can be a very slow access memory.

4.- A system for transmission of data over a television channel according to claim 2 , characterized in that said data and program memory consists of four 34/128K x 8 bits, for a total size of 32K x 32 bits and it is sufficiently fast for enabling a normal operation of the concerned microcontroller at zero wait states.

5.- A system for transmission of data over a television channel according to claim 2, characterized in that said FIFO type memory consists of four FIFO access SRAM chips of a size 4/8/16K x 8 bits for a total size of 4K x 32 bits and it is sufficiently fast for enabling a normal operation of the microcontroller at zero wait states and it is utilized as a buffer memory or transit memory for transferring large blocks of data from the Personal Computer to the microcontroller.

6.- A system for transmission of data over a television channel according to claim 2, characterized in that said DPR memory consists of a dual access port SRAM chip, having a size of 1/2K x 8 bits, it is sufficiently fast for enabling a normal operation of the microcontroller at zero wait states and it is employed for storing the pattern registers.

7.- A system for transmission of data over a television channel according to claim 2, characterized in that the transmission logic block of the transmission card substantially comprises a timing generator module; a transmission data formatting module; a video digital-analog converter (DAC) ; an analog conditioning module and an output connector (C) .

8.- A system for transmission of data over a television channel according to claim 7, characterized in that said timing generator can be implemented by means of an ASIC type device and it is designed in order to generate all timing signals needed in the transmission system, namely: 60 MHz: system clock TCLKD: transmission clock for the data channel; TCLKS transmission clock for the set-up channel; CTSD_ transmission enable signal for the data channel; CTSS_ transmission enable signal for the set-up channel CSYNC: video synchronization composite signal; CBLANK video deletion composite signal; VSYNC: vertical (or frame) synchronization signal; HSYNC: horizontal (or row) synchronization signal; TXENA: transmission enable signal.

9.- A system for transmission of data over a television channel according to claim 7, characterized in that said transmission data formatting module can be made by an ASIC device comprising a time base generator and a digital waveform generator and it is utilized for formatting the data to be transmitted by generating a digital output; TDX (0 - 7) : data to be transmitted with a 8 bit resolution; according to the signals: TXDD: data item to be transmitted over the data channel; TXDS: data item to be transmitted over the set-up channel; RTSD_ : transmission request by the data channel; RTSS_: transmission request by the set-up channel.

10.- A system for transmission of data over a television channel according to claim 7, characterized in that said video DAC converter is a digital-analog converter with video speed and 8 bit resolution and it converts digital signal TXD (0 ÷ 7) into an analog signal VIDSYNT, video composite B/W signal synthesized according to the timings furnished by signals 60 MHz, CSYNC and CBLANK.

11.- A system for transmission of data over a television channel according to claim 7, characterized in that said analog conditioning block is a completely analog block that is utilized to match the input signal

VIDSYNT to the levels of the video composite B/W

(VIDEO) signal and substantially comprises a low-pass filter, a gain adjusting block, an offset adjusting block and a buffer/inverter.

12.- A system for transmission of data over a television channel according to claim 7, characterized in that said time base generator generates the time bases of 60 MHz from an oscillator and of 10 MHz and 6

MHz from respective synchronous counters.

13.- A system for transmission of data over a television channel according to claim 7, characterized in that said digital waveform generator generates the timing signals: TCLKD, TCLKS, CTSD_, CTSS_, CSYNC, CBLANK, VSYNC, HSYNK, TXENA; SYNCRES, based upon clock signals of 10 MHz and 6 MHz and it is realized by means of a "run-length encoder" type machine, which generates an overassembly of all transitions of the video composite synchronization signal and by^' a set of state machines which, starting from such a signal, generate the output ones, the first machine being based upon two resettable counters and upon two ROM type memories, a first ROM memory wherein the durations of the high and low levels are stored and a second ROM memory that stores the numbers thereof.

14.- A system for transmission of data over a television channel according to claim 7, characterized in that said data formatting blocks substantially comprises a multiplexer for the transmission clock; a transmission data multiplexer; a multiplexer for a transmission request; a demultiplexer of the in-phase and the quadrature phase signals; a differential encoder; a delay line: a numerically controlled modulator.

15.- A system for transmission of data over a television channel according to claim 1 , characterized in that said three multiplexer circuits carry out a selection of the transmission clock (TCLK) , of the transmission data item and of the transmission request

(RTS_) among those pertaining to the data channel (TCLKD, TXDD, RTSD_) and those pertaining to the set-up channel (TCLKS, TXDS, RTSS__) , such a selection being effected according to the transmission enable signals

(CTSD_ and CTSS_) coming from the timing generator.

16.- A system for transmission of data over a television channel according to claim 14, characterized in that said demultiplexer separates the in-phase data

(A(T)) from the quadrature data (B(T)) for QPSK modulation.

17.- A system for transmission of data over a television channel according to claim 14, characterized in that said differential encoder module encodes the serial stream of data A(T) and B(T) in order to enhance the average distribution of the transmission power and in order to solve the ambiguity O^c- 180° for any receive decision.

18.- A system for transmission of data over a television channel according to claim 14, characterized in that said delay line introduces a fixed delay between the in-phase data and the quadrature data so as to realize the so-called "offset keying" modulation as requested by the OK-QPSK variation of the QPSK type modulation.

19.- A system for transmission of data over a television channel according to claim 14, characterized in that said numerically controlled modulator generates the data to be transmitted TXD [0:7] coded with a resolution of 8 bits, based upon signals I(T) and Q(T) by utilizing signals RTS_, CTDS_ and CTSS_, for framing purposes, together with clock signals TCLK and 60 MHz and substantially comprises the following components: state machine for phase control, a XOR matrix for inversion of the address, a ROM memory for the sinus function and a XOR matrix for inversion of the sign.

20.- A system for transmission of data over a television channel according to claim 11, characterized in that said low pass filter is used to interpolate the samples of the waveform synthesized by the digital/analog converter section (DAC) , to cut-off any spectral components outside the video band as well as to carry out the control function of the edge slope of the synchronization pulses.

21.- A system for transmission of data over a television channel according to claim 11, characterized in that said gain adjustment block is utilized to match the output signal amplitude, while the offset adjustment block is utilized for calibration of the reference level of same, the combined operations of the two adjustment blocks, by means of the selection V0UT_ RANGE, permits an output of 1 Volt on 75 ohms or 0.7 Volts on 75 ohms.

22.- A system for transmission of data over a television channel according to claim 11, characterized in that said buffer/inverter block makes available the

VIDEO modulation output positive or negative according to the VIDEOMOD selection.

23.- A system for transmission of data over a television channel according to claim 2, characterized in that the receive logic block of the receive car substantially comprises the following components: an input connector; an analog conditioning section; a synchronization separation; a luminance separator; a timing generator; a video analog/digital converter; a reception data formatting section.

24.- A system for transmission of data over a television channel according to claim 23, characterized in that said analog conditioning block is a completely analog block which is utilized in order to match the VIDEO input signal to the levels of the VIDEOS signals, namely the video composite B/W signals containing only the synchronization information, and VIDEOL, namely the video composite B/W signals containing only the luminance information, these signals being utilized for the subsequent blocks and substantially comprises a buffer/inverter block, a gain adjustment block, an offset adjustment block and an anti-aliasing low-pass filter.

25.- A system for transmission of data over a television channel according to claim 23, characterized in that said synchronization signal separating block is a mainly analog block that is utilized to separate, from within the VIDEOS signals, the synchronization signals CSYNC, namely the synchronization video composite signal, VPULSE, namely the signal containing the vertical (or frame) synchronization pulse, and the ODD/EVEN signal, namely the signal indicating the presence of the odd/even half-frame.

26.- A system for transmission of data over a television channel according to claim 23, characterized in that said luminance separator block is a mainly analog block that is utilized to individuate, within the VIDEOL signal, the DATAIN signal, namely the signal containing the data encoded as luminance information, by employing the timing as furnished by the CBLANK, namely the blanking video composite signal.

27.- A system for transmission of data over a television channel according to claim 23, characterized in that timing generator can be realized by means of an ASIC type device comprising a time base generator and a digital waveform generator and it is utilized to generate all necessary timing signals needed in the receive stage: 30 MHz: the system clock; RCLKD: receive clock for the data channel; RCLKS: receive clock for the set-up channel; CDD_: receive enable for the data channel; CDS_: receive enable for the set-up channel; CBLANK; starting from the information furnished by CSYNC signals; VPULSE; ODD/EVEN; El: error in recognition of the in-phase signal; EQ: error in recognition of quadrature signal.

28.- A system for transmission of data over a television channel according to claim 23, characterized in that said video ADC block comprises an analog/digital converter at video rate with 8 bits resolution which converts the analog signal DATAIN into a digital signal DATAIN [0:7], that is the received data, encoded with 8 bit resolution, based upon the timing signals furnished by the 30 MHz signal.

29.- A system for transmission of data over a television channel according to claim 23, characterized in that said received data formatting section can be realized by means of an ASIC type device and it is utilized for formatting the received data, said section generates the following outputs: RDD: data item received from the data channel; RDS: data item received from the set-up channel; El; EQ; based upon the detain [0:7] signal, according to the timing signals provided by the 30 MHz signals RCLKD, LCLKS, CDD_, CDS_.

30.- A system for transmission of data over a television channel according to claim 23, characterized in that said buffer/inverter block enables an input with positive or negative video modulation to be used, according to VIDEOMOD selection.

31. - A system for transmission of data over a television channel according to claim 24 , characterized in that said gain adjustment block is utilized to match the input signal amplitude, while the offset adjustment block permits its reference level to be calibrated, the combined operation of the above two blocks, by means of the VIN_RANGE selection, permits a 1 Volt input on 75 ohms or a 0.7 Volt input on 75 ohms.

32.- A system for transmission of data over a television channel according to claim 2 , characterized in that said anti-aliasing low-pass filter is utilized to cut off all those spectral components located outside the video band present in the input signal.

33.- A system for transmission of data over a television channel according to claim 27, characterized in that the time base generator generates a time base of 30 MHz by means of two digital phase locked loop circuits (DPLL) and the time bases of 10 MHz and 6 MHz by means of synchronous counters driven by a 60 MHz oscillator.

3 . - A system for transmission of data over a television channel according to claim 27, characterized in that said digital waveform generator is realized by means of a "run-length encoded" type machine that generates an overassembly of all transitions of the video composite synchronization signal and by means of a set of state machines that process said signal to produce the output signals, among which the starting state machine is utilized to align the synchronization signals synthesized within the timing signal generator to those contained in the received signal, the first above quoted machine is based upon two presettable counters and upon two ROM memories: a ROM memory containing durations of the high and low levels and a ROM memory containing the number of the high and low level .

35.- A system for transmission of data over a television channel according to claim 23, characterized in that said data formatting section is comprised of the following essential components: a first multiplexer for selecting the clock signal between the data channel and the set-up channel, a demultiplexer for separating and routing the received data between the data channel and the set-up channel, as well as a second multiplexer for recomposition of the in-phase and quadrature data for the QPSK modulation, a differential decoder for the stream of the received data, a delay line, a numeric sin/cos generator, a correlator for in-phase data, a correlator for quadrature data and a digital equalizer filter.

36.- A system for transmission of data over a television channel according to claim 35, characterized in that said delay line introduces a fixed delay between the in-phase and the quadrature data, so as to realign them after the so-called "offset keying" as requested by the OK-QPSK variant of the QPSK type modulation.

37.- A system for transmission of data over a television channel according to claim 35, characterized in that said numeric sin/cos generator generates the reference functions of sine sin [0:7] and of cosine cos [0:7] encoded with 8 bit resolution and comprises the following components: a phase control state machine, a XOR matrix for inverting the address of the sine 48 function, a ROM memory for the sine function, a XOR matrix for inverting the sign of the sine function, a XOR matrix inverting the sign of the cosine function, a ROM memory for the cosine function and a XOR matrix for inverting the sign of the cosine function.

38.- A system for transmission of data over a television channel according to claim 37, characterized in that said state machine for phase control is of a

"one shot encoding" type and it is utilized to generate the addresses, the address inversion command and the sign inversion command for reading the search look-up tables implemented by means of ROM memories containing the sine and cosine functions and by means of four XOR matrices.

39.- A system for transmission of data over a television channel according to claim 37, characterized in that said in-phase data correlator effects correlation between the input data DATA [0:7] and the cosine function cos[0:7], in order to decide as to the value of the data item I(T) .

40.- A system for transmission of data over a television channel according to claim 37, characterized in that said correlator for the quadrature data items carries out a correlation between the input data item DATA [0:7] and the sine function sin [0:7] in order to determine the value of data item Q(T) .

41.- A system for transmission of data over a television channel according to claim 35, characterized in that said digital equalization filter carries out a digital equalization filtering in order to enhance only the interest frequencies within the spectrum.

42.- A system for transmission of data over a television channel according to claim 2, characterized in that the auxiliary logic of the receive card comprises a memory containing the unique serial number for each card, an error detecting and correcting encoder, a fast table correlator and a decryption unit.

43.- A system for transmission of data over a television channel according to claim 2, characterized in that said ISA interface control logic permits the microcontroller to be interfaced to the Personal Computer by means of an ISA type bus and comprises the following functional blocks: control registers, status registers, a DPR memory control logic, a FIFO memory control logic, a logic for controlling the interrupt to/from said ISA bus, a logic for controlling the microcontroller DMA, a decode and buffer logic for interfacing to the ISA bus.

44.- A system for transmission of data over a television channel according to any one of the preceding claims, characterized in that pattern registers are utilized for containing the operation and initialization parameters of the transmission card, read and write operations in said registers can be carried out both by the Personal Computer and by the microcontroller; said registers can be placed in said DPR memory.

45.- A system for transmission of data over a television channel according to any one of the preceding claims, characterized in that said control registers are utilized in order to make the transmission card carry out certain operations, write operations in said registers can be carried out by the Personal Computer, while read operations can be carried out therein by said microcontroller, said registers being located in the ISA interfacing control logic.

46.- A system for transmission of data over a television channel according to any one of the preceding claims, characterized in that said status registers are utilized in order to let the Personal Computer get informed about the operation of the transmission card, read operations can be carried out in these registers by the Personal Computers, while write operations can be carried out therein by said microcontroller; these registers being located in the ISA interfacing control logic.

47.- A system for transmission of data over a television channel according to any one of the preceding claims and substantially as described in the specification and shown in the enclosed drawings.