WO1996015585A1

WO1996015585A1 - Rf transmitter

Info

Publication number: WO1996015585A1
Application number: PCT/GB1995/002637
Authority: WO
Inventors: David James Mccabe
Original assignee: At & T Wireless Communications Products Limited
Priority date: 1994-11-10
Filing date: 1995-11-09
Publication date: 1996-05-23
Also published as: GB9422683D0

Abstract

An IQ modulator in which digital I (155) and Q (153) signals, which are quadrature representations of a modulating function, are connected into corresponding analogue I (165) and Q (163) signals using a first (156, 135) and second (154, 135) sigma-delta Digital-to-Analogue Converter (DAC). The analogue I and Q signals are then combined with analogue quadrature representations of a carrier signal (160) using two multiplying circuit elements (166, 164) and an adding circuit element (168) to form an output signal substantially at the same frequency as the carrier signal but modulated by the modulating function. Each sigma-delta DAC includes both an adder having a carry output which toggles between a high and a low level at a rate much higher than the bandwidth of the analogue signal to be generated, and a low pass filter arrangement (135).

Description

RF TRANSMITTER

The invention relates to RF transmitters and in particular to a subsystem of an RF transmitter which is realised in a novel way giving particular advantages.

It is known practice to realise an RF transmitter system using an IQ modulator. This technique is used to superimpose a modulation of amplitude, phase, or frequency on a constant carrier waveform. To achieve this, two signals (usually denoted I and Q) are generated which represent the modulating function, but centred on zero frequency. The two signals are quadrature representations of the modulating function, i.e. their corresponding frequency components are all separated by 90° phase. These signals are then multiplied by quadrature carriers (usually constant amplitude and frequency sine and cosine waves) , and the two results summed. The output is a carrier at the frequency of the original carriers, but with the modulation function from the I and Q signals applied to it.

Figure 1 illustrates the operation of a conventional IQ frequency modulator. Input signals I and Q are input along lines 65 and 63 to two circuit elements 66 and 64. Two further inputs 60,61, one to each circuit element, originate from the same input line 60 but one of these has a 90° phase shifter 62 located before the circuit element 66. The outputs of the two circuit elements 66 and 64 are inputted to a third circuit element 68 and the output of the modulator is passed out from here along output line 71. The I and Q signals correspond to sine and cosine waves which are frequency modulated about zero frequency, and these are multiplied by sine and cosine waves at 100MHz. This results in an output which is a frequency modulated wave at 100MHz. In order to see that this will indeed be the case one simply needs to consider the well known trigonometric identity: -

Equation 1) : sin(c + m) = sin(c) x cos (m) + cos (c) x sin(m) ; where c = the carrier frequency, and = the modulating frequency (ie. the frequency of the I and Q signals) .

The first, second and third circuit elements 64, 66, 68 of Figure 1 act as operators which correspond directly to the algebraic operations in Equation 1) . That is, first 64 and second 66 circuit elements act to multiply together the two input signals 60, 63; 61, 65 to each element 64, 66 . The Q signal is input to the first circuit element 64 via line 63 together with a 100MHz sine wave carrier signal which is sent along line 60; the Q signal corresponds to the cos(m) term of Equation 1) while the carrier signal corresponds to the sin(c) term. Similarly the I signal (corresponding to the sin ( ) term) sent along line 65, and the 100MHz cosine wave carrier signal (corresponding to the cos(c) term) formed by passing the sine wave carrier signal through a π/2 phase- shifting circuit element 62 sent along line 61, are inputted to the second circuit element 66. The output product signals are then inputted to the third circuit element 68 which simply adds the two signals together. The output sum signal sent along line 71 is the 100MHz sine wave carrier signal, frequency modulated by the frequency of the I and Q signals as required, and corresponds to the sin(c + m) term of Equation 1) .

It will be noted that this process requires in phase and quadrature versions of both the carrier and the modulating signals. This technique avoids the need to directly modulate the frequency of the carrier wave, which can be troublesome if it is synthesised or derived from a crystal.

Typically, radio transmitters seeking to transmit a digitally encoded signal have used conventional digital-to-analogue converters (DAC's) based on a combination of scaled resistor values.

Generally in these DAC's the resistors double in value and are respectively connected to the outputs of, for example, a register, from which the output signals correspond to the bits of a binary number, stored in the register, which it is desired to convert into an analogue voltage. These conventional DAC's require matching of values to achieve high accuracy output. Generally it is difficult to achieve matching between the resistive elements used better than about 1%; this corresponds to about 6 bits of resolution (on an analogue chip process) . This can be improved by using larger area components or by trimming, both of which, however, incur extra cost. Generally it is convenient to use digital chip processes whenever possible since this will reduce the costs involved and increase the choice of IC vendor. However, the sort of components available on digital IC's for use in a conventional DAC are even cruder.

According to the present invention there is provided an IQ modulator comprising digital to analogue conversion means for receiving a digital I and a digital Q signal, which are quadrature representations of a modulating function, and converting said digital I and Q signals into corresponding analogue signals and combination means for combining said analogue signals with analogue, quadrature representations of a carrier signal having a constant carrier frequency to form an output, analogue signal substantially at the carrier frequency but modulated by the modulating function, wherein the digital to analogue conversion means includes a first and second sigma-delta DAC for converting said digital I and Q signals respectively into corresponding analogue signals.

Preferably the sigma-delta DAC includes an adder having a first input to which a binary number to be converted is applied and a carry output which may toggle between a high and a low level and a low pass filter connected to the carry output. The adder repeatedly adds the binary number to be converted to an accumulating total applied to a second input of the adder until the accumulating total exceeds the maximum number which the adder may output . At this point the carry output goes high.

The adder preferably has a sum output connected to the second input via a register. The sum output is generally a binary number equal to the sum of the two numbers input at the first and second inputs of the adder. The register is clocked and repeatedly presents the sum output of the previous clock cycle to the second input of the adder as the accumulating total. When the sum of the two inputs exceeds the maximum number which may be output e zr. :.-." :^" output, the carry output goes high a. :r.e -~ :- p t wraps around as explained below.

The carry output is preferac.y σa ci :y Demg passed into a simple flip-flop which is preferably clocked at the same rate as the register such chat the output of the flip-flop is high for a whole clock cycle whenever the carry output goes high. The low pass filter is then preferably connected to the output of the flip-flop.

Preferably the low pass filter has a breakpoint frequency, at which frequency the ratio of the amplitude of a signal passing into the filter to the amplitude of the output signal would be 1//2, which breakpoint frequency is lower than the rate at which the register connected to the adder is clocked. Preferably before the low pass filter the carry output of each adder is split into two branch lines and each DAC further includes a notch filter arrangement comprising a delaying shift register located on one of said branch lines for delaying the signal along said one of said branch lines by a predetermined amount, and a reconstruction filter arrangement in which the signals along said two branch lines are recombined. The low pass filter and the reconstruction filter arrangement may conveniently be combined to form a low-pass, reconstruction filter.

The IQ modulator is preferably incorporated into a radio transmitter for use in a radio telecommunication system; preferably the radio transmitter will be a CT2 radio transmitter.

In the preferred system to be described, the baseband I and Q signals are generated using a form of sigma-delta DAC which can be implemented in a particularly simple way if only moderate signal to noise ratios are required as is usual in digital communication systems. In such systems the data can be easily recovered without error in the presence of a small amount of noise. In order that the present invention may be better understood embodiments thereof will now be described by way of example only with reference to the accompanying drawings in which:-

Figure 1 is a diagrammatic representation of a known arrangement of an IQ modulator for performing frequency modulation;

Figure 2 is a diagrammatic representation of a sigma-delta Digital-to-Analogue Converter (DAC) ;

Figure 3 is a diagrammatic representation of an arrangement for adding a notch-filter response to the output of a sigma-delta DAC; Figure 4 is a diagrammatic graph of signal amplitude vs. signal frequency showing the effect of a notch filter; and

Figure 5 is a diagrammatic representation of a CT2 radio transmitter incorporating an IQ modulator according to the present invention.

Figure 2 illustrates the operation of a sigma-delta DAC. In a sigma-delta DAC, the raw converter output is digital, and toggles between only two levels (denoted 0 and 1) . The digital output DO toggles at a rate much higher than the bandwidth of the analogue signal to be generated, the rate being controlled by a system clock 20. This output is low pass filtered at a frequency slightly larger than the bandwidth of the analogue signal to obtain the output waveform 19. The converter is controlled by logic such that the duty cycle of the output corresponds to the required output level . Thus for a low output the converter digital output DO spends most of its time at 0 ^an< f°^{r a} high output it is mostly 1. By varying the duty cycle, any voltage between the two extremes can be obtained. Unlike pulse width modulation schemes, the digital output is only high or low for whole periods of the DAC clock. The accuracy and repeatability of the DAC output mainly comes from the stability of the output buffer voltage supply and the clock frequency, and is relatively independent of external component values, which is advantageous.

A simple realisation of the sigma-delta DAC is shown in Figure 2. A number N representing the output value is input at input terminal 10 to a register 11 and forms the input signal to the sigma- delta DAC. It represents the output level to be produced by the DAC. It is updated periodically to make the output waveform. This number is fed to an adder 21, where a number A repeatedly has N added to itself (A := N + A) . This process is effected by taking the sum output 24 of the adder 21 and inputting it to a further register 12. In each clock cycle the sum from the previous cycle is shifted to the output of the further register 12 and applied to one of the inputs of the adder 21. This occurs at the rate of the system clock 20 which is higher than the rate at which N is changed which is determined by the sample clock 23. The number A increases until the register 21 overflows, whereupon the number 'wraps around' to A modulus (M+l) , where M is the maximum value the register 21 can hold. The signal 22 from the adder 21 which indicates overflow is retimed by a simple flip- flop 13, and is used as the DAC output, when suitably buffered by an output buffer 14. The duty cycle of this signal is directly proportional to the number N, and so the low-pass filtered voltage derived from it is proportional to N. The low-pass filter 15 shown here simply comprises a resistor 16 and a capacitor 17 connected to ground 18. The signal is retimed so that the finite propagation delays in the logic to generate the carry output do not affect the duty cycle.

In the implementation to be described, the converter is realised with a normal logic output buffer as is commonly found on any digital IC, together with a discrete RC post-filter. This realisation has the particular advantage that the analogue IQ function may be realised on a purely digital IC, thus reducing costs and widening the choice of IC vendor. In addition, the sigma-delta technique has advantages of inherent monotonicity and (provided the output is loaded by a relatively high impedance) well controlled accuracy and offset. By suitable choice of output buffer, its impedance can be made low compared to the load of the post filter, and acceptably small errors result. One reason why it is particularly advantageous in the present invention that the chosen DAC's should achieve good linearity and monotonicity is because the I and Q waveforms at any instant will have very different values (because they are a quarter of a cycle out of phase) . If the DAC's do not have good linearity and monotonicity the digital I and Q signals will not be correctly converted into analogue signals which differ only in their phase . Such errors in conversion cause spurious products in the modulated output. Figure 3 shows a notch filter which is specially adapted for use with a sigma-delta DAC. This has the advantage that well controlled filtering of the I and Q signals may be obtained by simple manipulation of the digital signals feeding an output filter 35. In the particular implementation of interest, the logic signal output (I or Q) from the sigma-delta DAC is split into two signals which are presented to 2 output buffers 33, 34, one via a delaying shift register 30 which introduces a delay of several clock cycles. The two outputs are summed in the reconstruction filter 35. This delay and sum action imparts a notch filter response on the analogue output. Frequencies where the delay of the shift register 30 is an odd number of half cycles are cancelled. The cancellation frequencies depend only on the frequency of the system clock 20 and are thus extremely repeatable. The depth of the cancellation notch depends on the matching of the two summing resistors 37, 38. The graph of Figure 4 illustrates the effect of a notch filter. The output signal from an IQ modulator is shown with its amplitude (A) along the vertical axis plotted against its frequency (F) along the horizontal axis. The output signal is plotted both without the notch filter applied (U) and with (V) . In both cases it can be seen that the wanted part of the signal (S) has the largest amplitude and is centred around the carrier frequency (fc) . However, in the case of the unfiltered signal (U) the amplitude of the noise (N) only falls off slowly away from the wanted part of the signal (S), whilst the noise in the filtered signal (V) falls off very rapidly to zero at frequencies of ±500kHZ either side of the carrier frequency (fc) . In this case the filter has a depth of 100% which would require the two summing resistors 37, 38 of Figure 3 to have equal resistances.

Figure 5 shows the currently preferred IQ modulator and notch filter arrangement incorporated into a CT2 radio transmitter. A microphone 102 initially detects an audio signal and converts it into an analogue electrical signal which is amplified by an initial amplifier 104. The amplified analogue speech signal 105 is then passed into a speech encoder 106. The resulting signal is a 32 k bit/s digitally encoded speech signal 107. This signal is passed into a speech buffer 108 which re-transmits the signal at a faster bit rate in short bursts. These bursts of speech signals are then combined with signalling data 110 and synchronisation data 111 in a CT2 burst formatter to produce CT2 format bursts at a bit rate of 72 k bit/s.

In order to radio transmit the information contained in the CT2 format bursts, the bursts are converted into suitable modulating signals and used to modulate a carrier signal at the desired carrier frequency suitable for radio-transmission. This is done in two stages by the IQ modulator. Firstly analogue I and Q signals are generated by a first part 150 of the IQ modulator. These are quadrature representations of a modulating signal (such as a sine wave) frequency modulated about zero Hz by a modulating function representative of the information stored in the CT2 bursts. Then these analogue I and Q signals are combined with a carrier signal to produce the required modulated signal by a second part 162, 164, 166, 168 of the IQ modulator.

In the first part 150 of the IQ modulator, the CT2 format signal bursts are firstly processed by a digital IQ signal generator 152 which outputs a digital I signal 155 and a digital Q signal 153. The digital I and Q signals essentially represent "sample values" of the values which the analogue I and Q signals, which it is desired to create, should have at the discrete

"sampling" times. In the present embodiment 20 such sample values are produced for each section of the I and Q signals representing one bit of the CT2 format signal entering the digital IQ signal generator 152. The "sample" values take the form, in the present embodiment, of 8-bit binary numbers. These are then input into the sigma-delta DAC,s 154, 156. Being updated 20 times for every CT2 bit, amounts to a rate of 1.44 M bit/s; this corresponds to the rate of the sample clock 23 of Figure 2.

Meanwhile, the output signals 129, 131 from the sigma-delta DAC's 154, 156, are toggling at a rate of 7.2 M bit/s. However, the maximum frequency which the I and Q signals need have is 36 kHz thus the requirement that the digital output DO should toggle at a rate much higher than the bandwidth of the signal to be generated is easily satisfied in this case; in fact the digital output DO toggles at a rate about 2 orders of magnitude greater than the bandwidth of the I and Q signals being generated.

The digital output signals, whose duty cycles correspond to the analogue I and Q signals required, are buffered and then passed through low- pass, reconstruction filters 135. The outputs from the filters are the required analogue I 165 and Q 163 signals. The I signal 165 is then combined with the carrier signal 160 (an 866 MHz sine wave) , having passed through a it/ 2 phase shifter 162, by multiplication in a first multiplying circuit element 166. Similarly the Q signal 163 is combined with the carrier signal 160 (without having passed through a phase-shifter) in a second multiplying circuit element 16 . The outputs of the two multiplying circuits are then added together in an adding circuit 168 to produce an 866 MHz frequency modulated signal. Finally this signal is amplified in an RF power amplifier 170 and transmitted via an aerial 172.

As was mentioned above, other forms of modulation can be performed utilising the same basic IQ modulation structure as shown in Figure 5. For example single side-band amplitude modulation can be performed if the digital I and Q signals simply take the form of quadrature representations of an audio type signal. The resultant effect is to increase the frequencies of the audio type signal by the carrier frequency (ie. the signal is translated along the frequency spectrum by the frequency of the carrier signal) .

The main advantages of IQ modulation over other forms of modulation are that the modulating waveforms can be generated at a low frequency (which is easier) , and the need to modulate the carrier signal places no requirements on the carrier signal generation system which is entirely separate.

Claims

1. An IQ modulator comprising digital to analogue conversion means for receiving a digital I and a digital Q signal, which are quadrature represen¬ tations of a modulating function, and converting said digital I and Q signals into corresponding analogue signals and combination means for combining said analogue signals with analogue, quadrature represen- tations of a carrier signal having a constant carrier frequency to form an output, analogue signal substan¬ tially at the carrier frequency but modulated by the modulating function, wherein the digital to analogue conversion means includes a first and second sigma- delta DAC for converting said digital I and Q signals respectively into corresponding analogue signals.

2. An IQ modulator as claimed in claim 1 wherein each sigma-delta DAC includes: an adder having a first input to which a binary number to be converted is applied, said adder having a carry output; and a low pass filter connected to the carry output whereby the adder repeatedly sums the binary number to be converted and an accumulating total applied to a second input of said adder, and whereby the carry output is high, or low, depending upon whether the sum of the binary number and the accumulating total exceeds, or does not exceed, respectively a predetermined maximum number.

3. An IQ modulator as claimed in claim 2 wherein the adder of each sigma-delta DAC has a sum output which is connected to said second input via a register which is clocked by a system clock, said register being operable to generate said accumulating total from the sum output of said adder.

4. An IQ modulator as claimed in claim 3 wherein each sigma-delta DAC further comprises a flip-flop which is connected to the carry output of the adder and is clocked at the same rate as the register whereby whenever the carry output goes high the flip-flop goes high for a whole clock cycle.

5. An IQ modulator as claimed in any one of claims 2 to 4 wherein the carry output of each adder is split into two branch lines before the low pass filter and each sigma-delta DAC further includes a notch filter arrangement comprising a delaying shift register located on one of said branch lines for delaying the signal along said one of said branch lines by a predetermined amount, and a reconstruction filter arrangement in which the signals along said two branch lines are recombined.

6. An IQ modulator as claimed in claim 5 wherein said low pass filter and said reconstruction filter arrangement are combined into a single low pass, reconstruction filter.

7. An IQ modulator as claimed in any cne cf claims 2 to 5 wherein each sigma-delta 3AC i-:t:." comprises one or more buffers connected et ^er. * r.e carry output of the adder and the lew p-aβε t . -:c: 8. A radio transmitter incorpcrat.ιr.3 a:, i; modulator as claimed in any one of the precedir.g claims.