WO1996014660A1 - Method for fabricating a self-limiting silicon based interconnect for testing bare semiconductor dice - Google Patents
Method for fabricating a self-limiting silicon based interconnect for testing bare semiconductor dice Download PDFInfo
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- WO1996014660A1 WO1996014660A1 PCT/US1995/014483 US9514483W WO9614660A1 WO 1996014660 A1 WO1996014660 A1 WO 1996014660A1 US 9514483 W US9514483 W US 9514483W WO 9614660 A1 WO9614660 A1 WO 9614660A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/06711—Probe needles; Cantilever beams; "Bump" contacts; Replaceable probe pins
- G01R1/06733—Geometry aspects
- G01R1/06738—Geometry aspects related to tip portion
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/073—Multiple probes
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/073—Multiple probes
- G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
- G01R1/07314—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13016—Shape in side view
- H01L2224/13018—Shape in side view comprising protrusions or indentations
- H01L2224/13019—Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0367—Metallic bump or raised conductor not used as solder bump
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0373—Conductors having a fine structure, e.g. providing a plurality of contact points with a structured tool
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09045—Locally raised area or protrusion of insulating substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/325—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49453—Pulley making
Definitions
- This invention relates generally to semiconductor manufacture and more particularly to methods for fabricating an interconnect suitable for testing the operability of integrated circuitry on a bare, discrete semiconductor die.
- Multi-chip modules are being increasingly used in computers to form PC chip sets and in telecommunication items such as modems and cellular telephones.
- consumer electronic products such as watches and calculators typically include multi-chip modules.
- non-encapsulated dice i.e., chips
- electrical connections are then made directly to the bond pads on each die and to electrical leads on the substrate.
- the multi-chip module is favored because it provides significant cost and performance characteristics over packaged dice. It has been estimated that by the year 2000, 25% of all dice will be utilized in their bare or unpackaged form.
- test apparatus for conducting burn-in tests for discrete die are disclosed in U.S. Patent No. 4,899, 107 to Corbett et al. and U.S. Patent No. 5,302,891 to Wood et al., which are assigned to Micron Technology, Inc.
- Other test apparatus for discrete die are disclosed in U.S. Patent No. 5,123,850 to Elder et al., and U.S. Patent No. 5,073,117 to Malhi et al., which are assigned to Texas Instruments.
- bond pads provide a connection point for testing the integrated circuitry of the die.
- Bond pads on semiconductor dice are typically formed of either aluminum, gold or solder using different pad metallurgies.
- a bond pad may have a flat planar configuration or it may be formed as a raised bump.
- the test apparatus for discrete die employ different techniques for making a non permanent connection to the bond pads of the die.
- the previously cited Wood et al. device employs a die contact member that utilizes non-bonded TAB (tape automated bonding) technology.
- the Elder et al. device utilizes a flexible interconnect member having an arrangement of probe bumps or members for contacting the bond pads.
- the Malhi et al. device uses an arrangement of cantilevered probe tips to contact the bond pads.
- non permanent wire bonding may be employed to effect the electrical connection.
- U.S. Patent No. 5, 173,451 to Kinsman assigned to Micron Technology, Inc. describes a method in which each die is mounted in a carrier and bond wires are non permanently attached to the bond pads using ultrasonic wedge bonding. The carrier and die are placed in the test apparatus and the bond wires are connected to external test circuitry for testing the integrated circuits on the die. Following completion of the test procedure, the temporary bond wires are separated from the bond pads and the die is separated from the carrier. In addition to wire bonding, TAB connections and probe tips, other interconnect structures have been used to connect the bond pads on a die with the circuitry of a test apparatus. As an example, U.S. Patent No.
- a test apparatus that includes a probe card for making electrical contact with the bond pads of a die.
- the probe card is an interconnection structure formed of a semiconducting material such as silicon.
- the Liu probe card includes pointed silicon protrusions coated with a conductive film for contacting the bond pads.
- U.S. Patent No. 5,207,585 to Byrnes et al. describes an interconnect structure formed as a flexible pellicle having electrodes for making a temporary connection with bond pads formed as a flat pad or as a conductive bump.
- a bond pad typically includes a metal oxide layer that must be penetrated to make an ohmic contact.
- Some prior art interconnect structures such as probe cards, scrape the bond pads which wipes away this oxide layer and causes excessive damage to the bond pads. Probe tips may pierce both the oxide layer and the metal bond pad and leave a deep gouge. Other interconnect structures, such as probe bumps, may not even pierce the oxide layer preventing the formation of an ohmic contact.
- KGD testing Another important consideration in KGD testing is the effect of thermal expansion during the test procedure.
- burn-in testing a die is heated to an elevated temperature. This causes thermal expansion of the die and test fixture. If the bond pads and the interconnect structure expand by a different amount, stress may develop between these components and adversely effect the electrical connection there between. This may also lead to excessive damage of bond pads.
- current physical testing apparatus for testing discrete semiconductor die have become the limiting factor in providing KGD at optimal yields. As is apparent, improved testing methods and structures for discrete die are needed in the art that are cost effective and that can be incorporated into the existing technology of large scale semiconductor manufacture.
- a method of fabricating a temporary interconnect suitable for use in testing bare, discrete semiconductor dice includes a silicon substrate having projecting contact members adapted to contact bond pads or other contact locations on a die.
- the contact members are formed integrally with the substrate in a pattern that matches the size and spacing of the bond pads on the die.
- the tip of each contact member is covered with a conductive layer.
- the conductive layer may be formed of a metal or a suicide.
- Conductive traces or runners are formed in electrical contact with the conductive layer. Bond wires are attached to the conductive traces to provide a conductive path to external test circuitry.
- each contact member includes one or more raised projections covered with the conductive layer and adapted to pierce the bond pads of the die to establish an ohmic contact.
- the raised projections are formed as sharpened blades or knife edges.
- the penetration depth of the raised projections into the bond pad is self-limiting by the dimensions and structure of the contact members and raised projections. Specifically, a top surface of the contact members acts as a penetration stop plane for the raised projections.
- the method of the invention comprises a method for forming the contact members, the conductive layer on the tips of the contact members and the conductive traces to the conductive layer.
- the conductive layer formed at the tip of each contact member is separated from the silicon substrate of the interconnect by an insulating layer.
- a silicon containing layer e.g., polysilicon, amorphous silicon
- a metal layer e.g., platinum, titanium
- a silicide e.g., PtSi2, TiSi2
- the silicon containing layer and the metal layer are then removed by etching selectively with respect to the silicide layer.
- a conductive layer e.g., aluminum
- patterned to form the conductive traces is patterned to form the conductive traces.
- interconnects are formed on a single substrate or wafer.
- This substrate can then be diced (e.g., saw cut) to singulate the interconnects.
- the method of the invention stated in detail comprises the steps of: forming an array of raised contact members on a substrate each having a projecting apex (e.g., knife edge, pointed projection) for penetrating a bond pad of the die; forming an insulative layer (e.g., oxide) on the contact members and substrate; forming a silicon containing layer on the insulating layer; forming a second insulating layer over the silicon containing layer; removing the second insulating layer on the contact member to expose the underlying silicon containing layer; depositing a first metal layer on the contact members and substrate; sintering the first metal layer and the silicon containing layer to form a silicide layer; selectively etching the first metal layer selective to the silicide layer to leave the contact member covered by the silicide layer; selectively etching the second insulating layer and silicon containing layer selective to the silicide layer; depositing a second metal layer on the substrate in contact with the silicide layer; and then etching the second metal layer from
- This process allows the contact members to be easily formed with a self aligned, low resistivity silicide layer.
- this process employs standard photoresist patterning methods, providing simplicity and cost reduction.
- the conductive traces to the silicide layer have a low resistivity.
- Figure 1 is a schematic cross sectional view of a portion of a semiconductor substrate, showing an initial process step for forming an interconnect in accordance with the invention
- Figure 2 is a schematic cross sectional view of the substrate showing another step of the method of the invention.
- Figure 3 is a plan view of Figure 2;
- Figure 4 is a schematic cross sectional view of the substrate showing another step in the method of the invention.
- Figure 5 is a schematic cross sectional view of the substrate showing another step in the method of the invention.
- Figure 6 is a plan view of Figure 5;
- Figure 7 is a schematic cross sectional view of the substrate showing another step in the method of the invention.
- Figure 8 is a schematic cross sectional view of the substrate showing another step in the method of the invention;
- Figure 9 is a schematic perspective view showing another step in the method of the invention illustrating partially completed contact members
- Figure 10 is a schematic cross sectional view showing another step in the method of the invention for forming a conductive silicide layer on the tip on the contact member;
- Figure 11 is a schematic cross sectional view showing another step in the formation of the silicide layer
- Figure 12 is a schematic cross sectional view showing another step in the formation of the conductive silicide layer
- Figure 13 is a. schematic cross sectional view showing another step in the formation of the silicide layer
- Figure 14 is a schematic cross sectional view showing the completed contact member and conductive traces
- Figure 15 is a schematic cross sectional view showing an interconnect constructed in accordance with the invention in electrical contact with the bond pads of a semiconductor die during testing of the die;
- Figure 16 is a schematic cross sectional view showing an alternate embodiment of the completed contact member and conductive traces.
- FIG 17 is a plan view of the completed interconnect with a die superimposed thereon.
- the interconnect 10 includes a substrate 12 formed of a semiconducting material such as monocrystalline silicon.
- the substrate 12 includes a planar outer surface 14 having a mask layer 16 of a material such as silicon nitride (Si 3 N 4 ) formed thereon.
- a typical thickness for the mask layer 16 is about 500A to 3000A.
- the mask layer 16 may be formed using a suitable deposition process such as CVD.
- the mask layer 16 is patterned and etched selective to the substrate 12 to form a hard mask that includes masking blocks 18, 20, 24 and 26.
- this etch step may be performed using a wet or dry etch.
- a layer of silicon nitride may be etched using hot (e.g., 180°C) phosphoric acid.
- ⁇ 26 are formed in a parallel spaced array and are sized and shaped to fit within the perimeters of a generally rectangular or square shaped bond pad of a semiconductor die (e.g., lOO ⁇ m x lOO ⁇ m).
- a parallel spaced array is merely exemplary and other configurations are possible.
- Other suitable arrangements for the masking blocks include enclosed rectangles, squares triangles, T-shapes and X-shapes.
- a wet or dry isotropic or anisotropic etch process is used to form projecting apexes 40, 42, 44, 46 on the substrate.
- an etchant solution containing a mixture of KOH and H 2 0 may be utilized. This isotropic etch results in the formation of triangular tips as shown in Figure 5. This is a result of the different etch rates of monocrystalline silicon along the different crystalline orientations.
- an etchant solution containing a mixture of HF, HN0 3 and H 0 may be utilized.
- the substrate may be subjected to an oxidizing atmosphere to oxidize portions of the substrate 12 not covered by the masking blocks 18, 20, 24, 26, of the mask layer 16.
- the oxidizing atmosphere may comprise steam and 0 2 at an elevated temperature (e.g. 950°C).
- the oxidizing atmosphere oxidizes the exposed portions of the substrate 12 and forms an insulating layer 49 (e.g., silicon dioxide).
- projecting apexes 40, 42, 44 and 46 are formed under the masking blocks.
- the projecting apexes 40, 42, 44, 46 may also be formed by a deposition process out of a different material than the substrate 12.
- the masking blocks 18, 20, 24, 26 are stripped using a wet etchant such as H 3 PO 4 that is selective to the substrate 12.
- a wet etchant such as H 3 PO 4 that is selective to the substrate 12.
- a suitable wet etchant such as HF.
- the steps of patterning and etching and stripping form projecting apexes 40, 42, 44, 46 which are in the form of parallel spaced knife edges.
- the projecting apexes 40, 42, 44, 46 form an apex group 43 which has an overall peripheral dimension which falls within the boundaries of a generally rectangular or square bond pad of a semiconductor die.
- multiple knife edges are formed for each bond pad, it is to be understood that a single knife edge per bond pad would also be suitable.
- the projecting apexes 40, 42, 44, 46 project from a surface 56 of the substrate 12 and include tips 58 and bases 60.
- Bases 60 of adjacent projecting apexes 40, 42, 44, 46 are spaced from one another a distance sufficient to define a penetration stop plane 62 there between.
- Example spacing between apexes would be 10 ⁇ m, while an example length of an individual stop plane 62 would be from 3 to 10 ⁇ M.
- the function of the penetration stop plane 62 will be apparent from the continuing discussion.
- the tip 58 and base 60 of each projecting apex 40, 42, 44, 46 are spaced apart by a protecting distance that is preferably about one-half the thickness of a bond pad on a semiconductor die.
- this projecting distance will be on the order of .5 to 1 ⁇ M.
- additional etching may be used to further sharpen the apexes 40, 42, 44, 46.
- a nitride masking layer 64 covers all of the projecting apexes 40, 42, 44, 46 in apex group 43 and photopatterned.
- the substrate 12 is etched around the masking layer 64 to form raised contact members 65.
- Typical etching techniques comprise wet anisotropic etching with a mixture of KOH:H 2 O. This type of etching is also known in the art as bulk micro-machining.
- the contact members 65 are sized and shaped to contact a bond pad of a semiconductor die. Each contact member 65 viewed from above has a generally square rectangular peripheral configuration and is dimensioned to fall within the perimeter of a bond pad.
- the contact members 65 can also be formed in other peripheral configurations such as triangles, polygons or circles.
- the height of each contact member 65 will be on the order of 50-100 ⁇ m and the width on each side about 40-80 ⁇ m.
- Figure 9 shows two adjacent contact members 65a and 65b extending from the substrate. The spacing of the contact members 65a and 65b matches the spacing of adjacent bond pads on a semiconductor die (e.g. , 50 to lOO ⁇ m).
- the method of the invention is adapted to form a conductive silicide layer 78A ( Figure 14) on the tip of each contact member 65.
- conductive traces 80 ( Figure 14) are formed to provide a conductive path to the silicide layer 78A ( Figure 14). This segment of the process is illustrated in Figures 10-14.
- an insulating layer 68 (e.g., SiO 2 ), is formed on the substrate 12 and contact members 65.
- the insulating layer 68 is formed by oxidation of the substrate 12 and may be accomplished by exposing the substrate 12 and to an oxidizing atmosphere for a short time.
- SiO 2 can also be deposited using CVD.
- Another commonly used insulator suitable for this purpose is Si 3 N 4 .
- a silicon containing layer such as polysilicon layer 70 is formed on the insulating layer 68.
- the polysilicon layer 70 is required to form a silicide with a metal layer 78 ( Figure 13) during subsequent processing.
- The. polysilicon layer 70 may be formed of doped or undoped polysilicon. Alternately, other silicon containing layers such as doped or undoped amorphous silicon may be employed in place of polysilicon. However, polysilicon is preferred for most applications because of lower resistivity and better electrical and structural properties and because it lends itself to simpler etching processes.
- the polysilicon layer 70 may be deposited on the insulating layer 68 using a suitable deposition process such as chemical vapor deposition (CVD) or by using an epitaxial growth process.
- a typical thickness for the polysilicon layer 70 would be from about 500A to 3000A.
- a second insulating layer 72 (e.g., SiO 2 ) is formed on the polysilicon layer 70.
- the second insulating layer 72 may be deposited using CVD techniques or formed by exposing the polysilicon layer 70 to an oxidizing environment.
- a typical thickness for the second insulating layer 72 would be from about 500A to 3000A.
- a layer of photoresist 74 is formed on the substrate 12 by spin-on or other suitable deposition process.
- the photoresist 74 is then developed such that the contact members 65 are exposed. This is relatively easy to accomplish because the photoresist 74 will tend to puddle on the lower portions of the structure, such as surface of the substrate 12, leaving the projecting contact members 65 exposed.
- the second insulating layer 72 Following development of the photoresist 74, the second insulating layer 72
- the photoresist 74 is removed and a metal layer 78 is deposited on the exposed polysilicon layer 70.
- the metal layer 78 covers the polysilicon layer 70 on the tip and sidewalls of the contact member 65 and completely covers the apex group 43.
- the metal layer 78 covers the second insulating layer 72 on the substrate 12.
- the metal layer 78 can be deposited to a thickness of about 500A to 3000 A using a suitable deposition process such as low pressure chemical vapor deposition (LPCVD), or using standard metal sputtering or evaporation techniques.
- LPCVD low pressure chemical vapor deposition
- the metal layer 78 is formed of a metal that will react with the polysilicon layer 70 to form a metal silicide.
- Suitable metals include the refractory metals, such as titanium (Ti), tungsten (W), tantalum (Ta), platinum (Pt) and molybdenum (Mo).
- silicides of these metals WSi2, TaSi 2 , MOSi 2 , PtSi 2 and TiSi 2
- Other suitable metals include cobalt (Co), nickel (Ni), molybdenum (Mo), copper (Cu), gold (Au) and iridium (Ir).
- a sintering process is performed in which the metal layer 78 is heated and reacts with the polysilicon layer 70 to form a silicide.
- This type of sintering process is also known in the art as salicide sintering.
- Such a salicide sintering step can be performed by heating the polysilicon layer, 70 and metal layer 78 to a temperature of about 650° to 820°C for typical thicknesses in thousands of angstroms (e.g., 2000A - 3000A). This sintering process can be performed in one single step or using multiple temperature steps.
- a silicide layer 78 A forms at the interface of the metal layer 78 and the polysilicon layer 70.
- the unreacted portions of the metal layer 78 and the polysilicon layer 70 are removed while the silicide layer 78A is left at the tip of the contact member 65.
- This can be done by etching the metal layer 78 and the polysilicon layer 70 selective to the silicide layer 78 A.
- a wet etchant such as a solution of ammonia and hydrogen peroxide, or a H 2 SO , H 2 0 2 mixture, that will attack the metal layer 78 and not the silicide layer 78A, can be used.
- a dry etch process with an etchant species such as Cl 2 or BC1 3 can be used to etch the metal layer 78 selective to the silicide layer 78 A.
- a wet etchant such as an HF:HN0 3 :H 2 0 acid mixture (typical ratios of 1:10:10) can be used to remove the unreacted portion.
- a wet isotropic etchant can also be used for this purpose.
- the polysilicon layer 70 may etched selective to the silicide layer 78A using a dry etch process and an etchant such as NF 3 at low pressures (typically 30m torr) or CLj and HBr at 130 m torr.
- the remaining second insulating layer 72 on the substrate 12 needs to be etched away prior to the polysilicon etch described above.
- the completed interconnect 10 includes the silicide layer 78A which covers the tip of the contact member 65 and the apex group 43 and a portion of the sidewalls of the contact member 65.
- the silicide layer 78 A can be extended to cover part of the base of the contact member 65 as shown in Figure 16.
- the resistivity of the silicide layer 78A may be lowered using an annealing process. This may be accomplished by heating the substrate 12 and silicide layer 78 A to a temperature of between about 780 °C to 850 °C for several minutes.
- conductive traces 80 may be formed on the substrate 12 to provide a conductive path in electrical contact with the silicide layer 78 A.
- the conductive traces 80 are formed by depositing and etching a second metal layer comprising a highly conductive metal such as aluminum, copper or alloys thereof, or a refractory metal such as titanium, tungsten, tantalum and molybdenum or alloys of these metals. Other conductive materials such as polysilicon may also be employed to form the conductive traces 80.
- the conductive traces 80 may be formed using a standard metallization process such as a blanket CVD deposition or sputtering followed by photopatterning and etching.
- a wet etchant such as H 3 PO 4 can be used to etch a patterned aluminum layer selectively from desired areas on substrate 12 to form aluminum conductive traces 80.
- Figure 17 shows an exemplary layout for the conductive traces 80 and contact members 65 in the completed interconnect 10. Such a layout will depend on the bond pad configuration of a die under test. Preferably a large number of interconnects 10 can be formed using semiconductor circuit fabrication techniques on a single substrate or wafer (not shown). The wafer can then be sawed (i.e., diced) to singulate the interconnects 10.
- bond wires 82 are wire bonded to the conductive traces 80 utilizing a conventional wire bonding process (e.g., solder ball) to provide a conductive path from the completed interconnect 10 to external test circuitry.
- a conventional wire bonding process e.g., solder ball
- each conductive trace includes a bonding site 92 for wire bonding the bond wires 82.
- other conductive paths such as external connector pads, slide connectors and other mechanical connector arrangements may be utilized (not shown).
- the interconnect 10 is shown engaging a semiconductor die 85 as a die under test (DUT).
- the die 85 includes a substrate 86 and an arrangement of exposed bond pads 88.
- a protective layer 90 covers the die 85 such that only the bond pads 88 are exposed.
- the bond pads 88 have a thickness of "A" and may be covered by a thin layer of oxide (not shown) depending on the metallization used for the bond pads.
- the projecting apexes 40, 42, 44, 46 represented by apex group 43 of a contact member 65, pierce the bond pad 88 and its oxide coating. The penetration of the apex group 43 is limited by the stop plane 62 ( Figure 8) formed by the surface of the contact member 65.
- the force required to press the apex group 43 into the bond pad 88 can also be monitored as an indication of the penetration depth.
- the apex group 43 extends about half way through the thickness of the bond pad 88 (i.e. , 1/2 of the distance A in Figure 15). This provides a low resistance ohmic contact between the silicide layer 78A and the bond pad 88.
- a penetration depth into the bond pad 88 is limited by the dimensions of the projecting apexes 40, 42, 44, 46 and by the stop plane provided by the top surface of the raised constant member 65.
- the conductive trace 80 and bond wire 82 provide a connection from the silicide layer 78A to test circuitry for testing the die 85.
- the opposite end of the bond wire 82 may be connected to a temporary holder for the die 85 adapted to be placed along with the interconnect 10 in a test apparatus (not shown).
- the test apparatus may include a connection to the temporary holder and to test circuitry.
- the invention provides a method for forming an interconnect useful in establishing an electrical connection to the bond pads of a semiconductor die for testing and other purposes.
- preferred materials have been described, it is to be understood that other materials may also be utilized.
- the method of the invention has been described with reference to certain preferred embodiments, as will be apparent to those skilled in the art, certain changes and modifications can be made without departing from the scope of the invention as defined by the following claims.
Abstract
Description
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Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
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AT95940644T ATE238606T1 (en) | 1994-11-07 | 1995-11-06 | PRODUCTION OF A SILICON-BASED TEST HEAD FOR TESTING NAKED SEMICONDUCTOR CHIPS |
JP51550196A JP3195359B2 (en) | 1994-11-07 | 1995-11-06 | Method for fabricating a silicon-based self-contained depth-of-depth interconnect for testing unpackaged semiconductor dies |
KR1019970703033A KR100285224B1 (en) | 1994-11-07 | 1995-11-06 | Method for fabricating a self limiting silicon based interconnect for testing bare semiconductor dice |
DE69530509T DE69530509T2 (en) | 1994-11-07 | 1995-11-06 | PRODUCTION OF A SILICON-BASED TEST HEAD FOR TESTING BARE SEMICONDUCTOR CHIPS |
AU42323/96A AU4232396A (en) | 1994-11-07 | 1995-11-06 | Method for fabricating a self-limiting silicon based interconnect for testing bare semiconductor dice |
EP95940644A EP0792518B1 (en) | 1994-11-07 | 1995-11-06 | Method for fabricating a self-limiting silicon based interconnect for testing bare semiconductor dice |
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US08/335,267 US5483741A (en) | 1993-09-03 | 1994-11-07 | Method for fabricating a self limiting silicon based interconnect for testing bare semiconductor dice |
US08/335,267 | 1994-11-07 |
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- 1995-11-06 AU AU42323/96A patent/AU4232396A/en not_active Abandoned
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- 1995-11-06 JP JP51550196A patent/JP3195359B2/en not_active Expired - Fee Related
- 1995-11-06 EP EP95940644A patent/EP0792518B1/en not_active Expired - Lifetime
- 1995-11-06 DE DE69530509T patent/DE69530509T2/en not_active Expired - Lifetime
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US7368924B2 (en) | 1993-04-30 | 2008-05-06 | International Business Machines Corporation | Probe structure having a plurality of discrete insulated probe tips projecting from a support surface, apparatus for use thereof and methods of fabrication thereof |
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US6504152B2 (en) | 1997-08-27 | 2003-01-07 | Imec Vzw | Probe tip configuration and a method of fabrication thereof |
US6995582B2 (en) | 2000-01-13 | 2006-02-07 | Infineon Technologies Ag | Testing device with a contact for connecting to a contact of a semiconductor component |
WO2001051935A1 (en) * | 2000-01-13 | 2001-07-19 | Infineon Technologies Ag | Test device for a semiconductor component |
US7142449B2 (en) | 2004-01-16 | 2006-11-28 | Hewlett-Packard Development Company, L.P. | Low temperature silicided tip |
US7838952B2 (en) | 2006-10-20 | 2010-11-23 | Seiko Epson Corporation | MEMS device and fabrication method thereof |
US8552512B2 (en) | 2006-10-20 | 2013-10-08 | Seiko Epson Corporation | MEMS device and fabrication method thereof |
US9865569B2 (en) | 2014-02-22 | 2018-01-09 | International Business Machines Corporation | Planarity-tolerant reworkable interconnect with integrated testing |
US9391040B2 (en) | 2014-10-17 | 2016-07-12 | International Business Machines Corporation | Planarity-tolerant reworkable interconnect with integrated testing |
Also Published As
Publication number | Publication date |
---|---|
JPH10506196A (en) | 1998-06-16 |
ATE238606T1 (en) | 2003-05-15 |
AU4232396A (en) | 1996-05-31 |
EP0792518A1 (en) | 1997-09-03 |
DE69530509D1 (en) | 2003-05-28 |
KR100285224B1 (en) | 2001-04-02 |
KR970707578A (en) | 1997-12-01 |
EP0792518B1 (en) | 2003-04-23 |
JP3195359B2 (en) | 2001-08-06 |
DE69530509T2 (en) | 2004-03-04 |
US5483741A (en) | 1996-01-16 |
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