WO1996003006A3 - Telecommunication exchange comprising a processor system, and a processor system - Google Patents

Telecommunication exchange comprising a processor system, and a processor system Download PDF

Info

Publication number
WO1996003006A3
WO1996003006A3 PCT/IB1995/000545 IB9500545W WO9603006A3 WO 1996003006 A3 WO1996003006 A3 WO 1996003006A3 IB 9500545 W IB9500545 W IB 9500545W WO 9603006 A3 WO9603006 A3 WO 9603006A3
Authority
WO
WIPO (PCT)
Prior art keywords
processor system
modules
group
processor
operate
Prior art date
Application number
PCT/IB1995/000545
Other languages
French (fr)
Other versions
WO1996003006A2 (en
Inventor
Antonius Gerardus Jose Seesing
Putte Marinus Van
Original Assignee
Philips Electronics Nv
Philips Norden Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Electronics Nv, Philips Norden Ab filed Critical Philips Electronics Nv
Priority to JP8504851A priority Critical patent/JPH09503115A/en
Priority to DE69534316T priority patent/DE69534316T2/en
Priority to EP95922693A priority patent/EP0724813B1/en
Publication of WO1996003006A2 publication Critical patent/WO1996003006A2/en
Publication of WO1996003006A3 publication Critical patent/WO1996003006A3/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54508—Configuration, initialisation
    • H04Q3/54516—Initialization, software or data downloading
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
    • H04Q3/5455—Multi-processor, parallelism, distributed systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/1305—Software aspects
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13109—Initializing, personal profile
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13376—Information service, downloading of information, 0800/0900 services

Abstract

A telecommunication exchange (1) is described for switching through telecommunication links, which is controlled by a processor system (5). The processor system (5) comprises a plurality of parallel-arranged modules (10, 20, 30, 40) which have each a processor (11, 21, 31, 41). In an operating mode of the processor system (5) the processors (11, 21, 31, 41) operate mutually synchronously. The processor system utilizes a fault-tolerant code. As a result, the entire processor system (5) continues to operate even if faults occur in certain modules. The processor system (5) is further arranged for operating in a software load mode. In this mode, the processor system (5) is subdivided into two groups of modules. The processors of the modules of each group operate mutually synchronously. The modules of each group use the code section generated by the modules of that particular group to operate. The software load mode makes it possible to feed new software to the processor system without the need to put the entire system out of order, either group is loaded with software while the other group continues to take over the working tasks of the processor systems. The fault redundancy, however, has strongly diminished or is even no longer present at all.
PCT/IB1995/000545 1994-07-15 1995-07-07 Telecommunication exchange comprising a processor system, and a processor system WO1996003006A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP8504851A JPH09503115A (en) 1994-07-15 1995-07-07 Telecommunication switching center having a processing system and processing system
DE69534316T DE69534316T2 (en) 1994-07-15 1995-07-07 TELECOMMUNICATION SYSTEM WITH A PROCESSOR SYSTEM AND A PROCESSOR SYSTEM
EP95922693A EP0724813B1 (en) 1994-07-15 1995-07-07 Telecommunication exchange comprising a processor system, and a processor system

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP94202068 1994-07-15
EP94202068.6 1994-07-15

Publications (2)

Publication Number Publication Date
WO1996003006A2 WO1996003006A2 (en) 1996-02-01
WO1996003006A3 true WO1996003006A3 (en) 1996-03-14

Family

ID=8217042

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB1995/000545 WO1996003006A2 (en) 1994-07-15 1995-07-07 Telecommunication exchange comprising a processor system, and a processor system

Country Status (5)

Country Link
US (1) US5734695A (en)
EP (1) EP0724813B1 (en)
JP (1) JPH09503115A (en)
DE (1) DE69534316T2 (en)
WO (1) WO1996003006A2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19529434B4 (en) * 1995-08-10 2009-09-17 Continental Teves Ag & Co. Ohg Microprocessor system for safety-critical regulations
JP2000507019A (en) * 1996-12-13 2000-06-06 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Redundant data processing system having two programmed logic controllers operating in series
JP4101368B2 (en) * 1998-08-24 2008-06-18 松下電器産業株式会社 Button telephone apparatus, maintenance method thereof, and recording medium
US6757244B1 (en) * 1998-10-01 2004-06-29 Samsung Electronics Co., Ltd. Communication bus architecture for interconnecting data devices using space and time division multiplexing and method of operation
EP1585350B1 (en) * 1999-10-14 2015-11-18 Nokia Technologies Oy A method and system for software updating
GB2359385B (en) * 2000-02-16 2004-04-07 Data Connection Ltd Method for upgrading running software processes without compromising fault-tolerance
US6556660B1 (en) * 2001-04-25 2003-04-29 At&T Corp. Apparatus for providing redundant services path to customer premises equipment
US20030039256A1 (en) * 2001-08-24 2003-02-27 Klas Carlberg Distribution of connection handling in a processor cluster

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5327418A (en) * 1988-10-28 1994-07-05 Siemens Aktiengesellschaft Circuit arrangement for centrally controlled telecommunications exchanges

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1297593C (en) * 1987-10-08 1992-03-17 Stephen C. Leuty Fault tolerant ancillary messaging and recovery system and method within adigital switch
US5410703A (en) * 1992-07-01 1995-04-25 Telefonaktiebolaget L M Ericsson System for changing software during computer operation
DE59309391D1 (en) * 1993-01-18 1999-04-01 Siemens Ag Real time control system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5327418A (en) * 1988-10-28 1994-07-05 Siemens Aktiengesellschaft Circuit arrangement for centrally controlled telecommunications exchanges

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IEEE TRANSACTIONS ON COMPUTERS, Volume C-35, No. 4, April 1986, T. KROL, "(N,K) Concept Fault Tolerance", especially page 340-348. *
PHILIPS TECHNICAL REVIEW, Volume 41, No. 1, 1983, TH. KROL, "The (4,2) Concept' Fault-Tolerant Computer", especially page 4-11. *

Also Published As

Publication number Publication date
US5734695A (en) 1998-03-31
WO1996003006A2 (en) 1996-02-01
EP0724813A1 (en) 1996-08-07
JPH09503115A (en) 1997-03-25
EP0724813B1 (en) 2005-07-20
DE69534316D1 (en) 2005-08-25
DE69534316T2 (en) 2006-04-20

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