WO1995035581A3 - Non-volatile sidewall memory cell method of fabricating same - Google Patents

Non-volatile sidewall memory cell method of fabricating same Download PDF

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Publication number
WO1995035581A3
WO1995035581A3 PCT/IB1995/000359 IB9500359W WO9535581A3 WO 1995035581 A3 WO1995035581 A3 WO 1995035581A3 IB 9500359 W IB9500359 W IB 9500359W WO 9535581 A3 WO9535581 A3 WO 9535581A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory cell
volatile
array
cell method
line direction
Prior art date
Application number
PCT/IB1995/000359
Other languages
French (fr)
Other versions
WO1995035581A2 (en
Inventor
Howard Pein
Original Assignee
Philips Electronics Nv
Philips Norden Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Electronics Nv, Philips Norden Ab filed Critical Philips Electronics Nv
Priority to KR1019960700804A priority Critical patent/KR960704358A/en
Priority to JP8501865A priority patent/JPH09504655A/en
Priority to EP95916816A priority patent/EP0714554A1/en
Publication of WO1995035581A2 publication Critical patent/WO1995035581A2/en
Publication of WO1995035581A3 publication Critical patent/WO1995035581A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
    • H01L29/7885—Hot carrier injection from the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30612—Etching of AIIIBV compounds
    • H01L21/30617—Anisotropic liquid etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/05—Etch and refill

Abstract

A non-volatile memory cell and array of such cells is provided. The memory cell includes a single transistor floating gate cell fabricated on a sidewall of a silicon pillar etched into a silicon substrate. The memory cells are arranged in an array of rows extending in a bit line direction and columns extending in a word line direction. A substantially smaller cell and array size is realized by limiting the dimension of the pillar and the bit line in the word line direction to be the minimum line width as limited by the lithography.
PCT/IB1995/000359 1994-06-17 1995-05-16 Non-volatile sidewall memory cell method of fabricating same WO1995035581A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019960700804A KR960704358A (en) 1994-06-17 1995-05-16 Non-volatile sidewall memory cell method of fabricating same
JP8501865A JPH09504655A (en) 1994-06-17 1995-05-16 Nonvolatile sidewall memory cell and manufacturing method thereof
EP95916816A EP0714554A1 (en) 1994-06-17 1995-05-16 Non-volatile sidewall memory cell method of fabricating same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/261,511 1994-06-17
US08/261,511 US5432739A (en) 1994-06-17 1994-06-17 Non-volatile sidewall memory cell method of fabricating same

Publications (2)

Publication Number Publication Date
WO1995035581A2 WO1995035581A2 (en) 1995-12-28
WO1995035581A3 true WO1995035581A3 (en) 1996-02-08

Family

ID=22993634

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB1995/000359 WO1995035581A2 (en) 1994-06-17 1995-05-16 Non-volatile sidewall memory cell method of fabricating same

Country Status (6)

Country Link
US (2) US5432739A (en)
EP (1) EP0714554A1 (en)
JP (1) JPH09504655A (en)
KR (1) KR960704358A (en)
TW (1) TW275715B (en)
WO (1) WO1995035581A2 (en)

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Also Published As

Publication number Publication date
US5432739A (en) 1995-07-11
WO1995035581A2 (en) 1995-12-28
JPH09504655A (en) 1997-05-06
US5563083A (en) 1996-10-08
EP0714554A1 (en) 1996-06-05
KR960704358A (en) 1996-08-31
TW275715B (en) 1996-05-11

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