WO1995032524A1

WO1995032524A1 - Semiconductor device in silicon carbide with passivated surface

Info

Publication number: WO1995032524A1
Application number: PCT/SE1994/000482
Authority: WO
Inventors: Christopher I. Harris; Erik Janzén; Andrei O. Konstantinov
Original assignee: Abb Research Ltd.
Priority date: 1994-05-24
Filing date: 1994-05-24
Publication date: 1995-11-30

Abstract

The present invention relates to a semiconductor component comprising a pn-junction (11) where both the p-conducting layer (10) and the n-conducting layer (12) constitute doped layers of silicon carbide (SiC) and where also the edges (16) of the pn-junction (11) are passivated by means of a semi-insulating layer (20, 21) which, if reverse voltage is applied over the pn-junction (11), shunts a weak current in the reverse direction of the pn-junction, thereby reducing the electrical field at the edges (16) of the junction. The invention also includes passivation of a silicon carbide surface by means of a semi-insulating layer (24). The process to achieve passivation of the surface of a semiconductor component made of silicon carbide according to the invention is characterized in that the electrical and structural properties at the surface of the silicon carbide are modified in a chemical process in which the surface of the component to be passivated is arranged to constitute part of one (1) of the electrodes in an electrolysis reaction during which the surface of the silicon carbide is illuminated by UV-light (6) so that the surface of the silicon carbide is etched to a resistive layer (20, 21, 24) whose insulating properties are determined by the voltage and current applied during the electrolysis and the intensity of the UV-light on the surface of the silicon carbide.

Description

Semiconductor device in silicon carbide with passivated surface .

TECHNICAL FIELD

The present invention relates to semiconductor component with silicon carbide as base material, where the risk of voltage breakthrough due to a strong electrical field at the edges of a pn-junction is reduced by providing the edges of the pn-junction with a shunted semi- insulating layer by means of a process entailing passivating the edge of the pn-junction on the component by means of photo-electrochemical etching of the surface of the silicon carbide. The invention also relates to the etching process itself.

BACKGROUND ART

Semiconductor components using silicon carbide as base material are continuously developed for use at high temperatures, in high power applications and under high radiation conditions - circumstances under which conventional semiconductors do not work satisfactorily. Evaluations indicate that SiC semiconductors of power MOSFET type and diode rectifiers based on SiC would be able to operate over a great voltage and temperature interval, e.g. up to 650 - 800°C, and show better breaker properties, such as lower losses and higher working frequencies, and still have a volume 20 times smaller than equivalent silicon components. The improvements are based on the favourable material properties of silicon carbide as compared with silicon such as, for instance, a higher breakthrough field (up to 10 times higher than silicon), higher thermal conductivity (more than 3 times higher than silicon) and a higher energy band gap (2.9 eN for 6H-SiC, one of the crystal structures of SiC).

Since SiC semiconductor technology is relatively young and in many respects not optimized, many critical manufacturing problems remain to be solved before SiC semiconductor devices can be realized experimentally and manufactured on a larger scale. This is especially true for components intended for use in high power and high-voltage applications. Difficulties requiring a solution are that the background doping concentration for the voltage-absorbing layer in the component must be reduced if a component is to be able to withstand voltages of several kilovolt, that the technology for surface-passivating silicon carbide must be optimized and that the number of critical defects in the silicon carbide material must be reduced if it is to be possible, for instance, to manufacture high-current components with large area. Other areas requiring development are, for instance, methods of manufacturing good ohmic contacts to the material, methods for doping with e.g. implantation, process methods for etching, etc.

High voltage diodes manufactured from 6H-SiC with epitaxially formed pn-junctions and Schottky junctions have been produced experimentally (see e.g. M. Bhatnagar and B. J. Baliga, IEEE Trans. Electron Devices, vol. 40, No. 3, pages 645 - 655, March 1993, or P. G. Neudeck, D. J. Larkin, J. A. Powell, L. G. Matus and C. S. Salupo, Appl. Phys. Lett. vol. 64, No. 11, 14 March 1994, pages 1386-1388). Some of the problems mentioned are thus solved, e.g. reducing the doping concentration, and the first ever 2000 V silicon carbide diodes have been reported. This achievement has been possible thanks to progress made in the manufacture of substrate material in silicon carbide.

One of the difficulties in manufacturing high voltage diodes or other semiconductor components with a voltage-absorbing pn-junction in

SiC is to obtain suitable passivation of the edge of the pn-junction. The electrical field over the edge of the pn-junction is extremely large when a high reverse voltage is applied over the pn-junction. This problem has not been solved in the known diodes mentioned above. Many of the problems still remaining to be solved in the development of semiconductor components in SiC are strongly reminiscent of those existing when such silicon components first appeared. However, it is not possible to apply the same methods for solving the specific problems related to the manufacture of silicon carbide components as in the solutions now known for corresponding production of silicon components. It may be mentioned, for example, that doping through diffusion is not feasible for SiC since diffusion coefficients are negligible below about 2270°K. Even ion implantation of doping elements, a common technique when manufacturing silicon components, is difficult to master and not fully developed for silicon carbide.

A high reverse bias generating a strong electric field at the edge of the pn-junction entails a great risk of voltage breakthrough or flash-over at the edge of the pn-junction. Where the pn-junction comes up to the surface on a component, an increase in the electrical field occurs in comparison with the conditions existing if the pn-junction is further into the component. This is due to the changeover from more homogeneous conditions inside the crystal of the component to the abrupt step out of the crystal lattice at the surface. It is therefore important to reduce the field concentration at the surface and passivate the surface. Combined with efforts to passivate the surface of a silicon component, measures are also taken to flatten out the electric field at the surface by influencing how the pn-junction emerges at the surface, for instance. As an example lapping (grinding) the surface of the edge at a certain angle through the pn-junction in order to flatten out the field is known from power components. It is also usual to gradually decrease the doping of the conducting area up towards the surface in a ring about the component area (known as Junction Termination Extension) in order to reduce the field concentration at the surface. These methods, known from silicon technique, are difficult to apply to SiC material since the material is so hard, doping through diffusion is impossible, and so on.

The problem of passivating a pn-junction has not been solved for pn- junctions made of SiC-based material. In corresponding pn-junctions with silicon as base material it is known, for instance, to provide the edge of the pn-junction with a semi-insulating layer, this layer leading a weak current in reverse direction via the semi-insulating layer when a high reverse voltage is applied to the pn-junction, so that the electrical field decreases at the edge of the pn-junction and the risk of voltage breakthrough is eliminated. No method of achieving such a semi-insulating layer on a SiC-based pn-junction is currently known, nor any SiC-based semiconductor component in which the edge of a pn-junction is provided with such a semi- insulating layer. The object of this invention is to provide a solution to this problem.

An example of a method used today for etching in order to manufacture components, e.g. to create pn-junctions by means of mesa-etching is RIE-etching (Reactive Ion Etching), which is a dry- etching method. SiC is otherwise almost inert to the normal etching liquids. Wet-etching has been tried using molten metals or molten salts at high temperature, but is not very practical. Experiments have also been performed using photo-electrochemical etching methods. The following may be mentioned as references: J. S. Shor, X. G. Zhang, A. D. Kurtz and R. M. Osgood, Springer Proceedings in Physics, Vol. 71, Amorphous and Crystalline Silicon Carbide IB, 1992, pages 356-361. "Photo-electrochemical Etching and Dopant Selective Etch-Stops in SiC", as well as J. S. Shur, I. Grimberg, B. Z. Weiss, A. D. Kurtz, Appl. Phys. Lett., Vol. 62, No. 22, 31 May 1993, pages 2836-2838, "Direct observation of porous SiC formed by anodization in HF". However, neither of these references takes up the problem of creating a passivating layer for the components, or of insulating or semi- insulating properties in a passivated layer.

DESCRIPTION OF THE INVENTION

The invention consists of a semiconductor component comprising a pn-junction where both the p-conducting layer and the n-conducting layer are produced as doped layers of silicon carbide (SiC) and where the edges of the pn-junction are passivated by means of a semi- insulating layer which, if reverse voltage occurs on the pn-junction (11), shunts a weak current in the reverse direction of the pn-junction, thereby reducing the electrical field at the edges of the junction. The invention also comprises passivating a silicon carbide surface with a semi-insulating layer.

The process for passivating the surface of a semiconductor component made of silicon carbide according to the invention is characterized in that the electrical and structural properties at the surface of the silicon carbide are modified in a chemical process in which the surface of the component to be passivated is masked off, the component is arranged to constitute one of the electrodes in an electrolysis reaction during which the surface of the silicon carbide is illuminated with UN-light, whereby the silicon carbide surface is etched to a resistive layer whose insulating properties are determined by the voltage applied during the electrolysis and the intensity of the UN-light on the surface of the silicon carbide.

The advantage of a passivating semi-conducting layer on the edges of the pn-junction is that the above-mentioned risk of flash-over or breakthrough at the edges of the pn-junction decreases while maintaining voltage in the reverse direction. By providing an etched pn-junction in a mesa, for instance, with a passivating semi-insulating layer at the edges of the pn-junction according to the invention, the voltage over the pn-junction before breakthrough occurs can be considerably increased (2 - 3 times greater).

The semi-insulating layer at the edges of the pn-junction is thus achieved by electrochemical and photo-electrochemical etching of the silicon carbide (SiC) surface. Several separate electrolysis reactions may be used such as ΝH4F.H2O or HF.C2H5OH. The resistivity of the insulating layer can be determined to the desired level with, e.g. constant photo-excitation intensity, by varying the current for the electrolysis. Low current density will produce a layer with high resistivity whereas higher current density will produce a layer with lower resistivity. Pure etching of SiC can be achieved with high electrolysis voltage and thus high current density. This technique is thus very suitable for producing desired patterns with mesa structure on silicon carbide substrate.

Reducing the excitation intensity makes the etching less efficient and an incomplete layer (in which, as mentioned, the desired resistivity can be varied by controlling the current density) is formed on the SiC surface. As mentioned above, the exact properties of the etched layer are strongly dependent on the process parameters (voltage and light intensity). At relatively high photo-excitation intensity the incomplete layer produced can be given high resistivity. This possibility of producing a strongly insulating layer on the silicon carbide surface by structurally modifying the surface of a SiC object electrochemically reveals an ideal way of passivating surfaces in the production of SiC components. A SiC component, with pre-defined contours, masked off in accordance with known lithographic technique, is thus passivated in a process involving electrochemical etching. It is thus possible in a single process step to perform first mesa-etching of the pn-junction and then, by altering the light intensity (or the current density), passivate the edge of the pn-junction by creating the semi-insulating "incomplete" layer.

The technique according to the invention has other advantages besides its simplicity. Since the layer is not deposited, as in the case of SIPOS or other similar layers, no growth equipment is required and the electrochemical etching thus follows normally after the preceding lithographic steps in the process. This enables a simpler and less expensive process for manufacturing the components. Furthermore, the passivated layer is chemically identical to the material of the component. It is produced directly from the component and does not constitute a layer deposited subsequently on the component. This eliminates any possibility of degeneration due to contamination from the encapsulating etched surface layer. The thermal and mechanical properties will thus be better suited to each other since component and layer are formed from the same piece of material.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 schematically depicts an apparatus for photo-electrochemical etching in a process where a surface of silicon carbide is restructured and thus surface-passivated.

Figure 2 schematically depicts a semiconductor diode of silicon carbide with a voltage-absorbing pn-junction edge-terminated with a so-called mesa etching. Figure 3 shows the same semiconductor diode where the edge of the pn-junction has been passivated using the etching process according to the invention.

Figure 4 shows a variant of the process with a planar structure on a semiconductor diode, where no preceding mesa etching has been performed prior to passivation.

Figure 5 shows deep-etching according to the process, of a structure as shown in Figure 4.

Figure 6 shows an example in principle of a Schottky diode without edge termination.

Figure 7 shows the Schottky diode of Figure 6 passivated according to the process of the invention.

DESCRIPTION OF EMBODIMENTS

The invention is described by way of example in a number of embodiments, with reference to the accompanying drawings.

The process for restructuring the surface of a silicon carbide component is illustrated in Figure 1 where the silicon carbide component, usually contained in a silicon carbide sample 1 is placed in a container 2 with electrolyte 3. The SiC sample 1 is, for instance, masked off by known lithographic methods and brought into contact with a copper electrode

4 which, in the example shown, constitutes a positive electrode in the electrolytic process that follows. The negative electrode consists of a platinum electrode 5. The electrolyte 3 in the example may consist of

HF: ethanol. To achieve the photo-electrochemical etching of the surface of the SiC sample the sample 1 may be illuminated with focused UV-light from a light source, the light being focused by a lens 7. The platinum electrode 5 may be annular to allow passage of light to the sample 1. With the aid of the device described photo-electrochemical etching can be performed on the surface of the SiC sample in order to passivate it (6H-SiC-structure). In a mode of etching with no light supplied and performed for a longish period of time with high anode voltage (20-25 V), a semi-porous layer is formed that has a fibre-like structure with pores between the fibres. High porosity, seen as a fibrous surface consisting of small fibres, is obtained with UV photo-excitation (0.2 W), e.g. with an argon ion laser, at low current densities (2-5 mA/ cm²). The etched material containing fibre sizes with small fibre diameters exhibits extremely high resistivity suitable for insulating components. If slightly higher current density (5 mA/ cm²) is chosen, the etched porous layer will have lower resistivity. Full etching occurs if the current density is substantially increased (>10 mA/cm²). The electrical properties, such as the resistivity of the layer of fibres etched in this way is strongly dependent on the fibre diameter and this can be controlled by means of the current density in combination with the light intensity.

For the sake of simplicity a semiconductor diode is shown in Figure 2 to exemplify the technique, this diode being of silicon carbide with a highly doped p-conducting layer 10 that forms a pn-junction 11 to an n- conducting layer 12 with low doping. The n-conducting layer 12 with low doping is adjacent to a highly doped n-conducting layer 13 in order to create better contact with the contact 14 which constitutes the cathode of the diode and is connected to the n-layer. A contact 15 is connected to the p-conducting layer 10 and thus forms the anode. The diode shown in Figure 2 is an example of a ready-etched and shaped mesa with a non-terminated edge 16 which thus has the drawbacks described earlier, e.g. risk of breakthrough at the edge 16 when a high voltage is applied to the diode in reverse direction.

Figure 3 shows how the surface of said SiC diode in the form of the mesa structure in Figure 2 is passivated by means of etching according to the process described in Figure 1 so that the edge 16 of the pn- junction is coated with a highly resistive or semi-insulating layer. This semi-insulating layer 20 serves to encapsulate the pn-junction 11 at its edge 16, while at the same time the layer 20 can conduct a weak current in the reverse direction past the pn-junction 11 when the latter has a voltage in reverse direction. The electrical field at the edge 16 is thus reduced in known manner. The figure also shows in principle how the depletion area 22 is extended laterally in the etched semi-insulating layer upon reverse voltage, so that a higher breakthrough voltage is achieved.

Another example of etching on the surface of the silicon carbide with the aid of the process according to the invention in order to achieve passivation is illustrated in Figures 4 and 5. This example starts with a planar diode structure as in Figure 4, where no preceding mesa etching has been performed, as shown in Figure 2. Instead, the photo- electrochemical etching is effected to a greater depth directly through the p⁺-layer 10 of the component down into the n-layer 12 with low doping, in order to produce a thicker insulating layer 21. In this case also, thus, edge termination of the pn-junction 16 in the diode is obtained. This method therefore enables both edge termination and passivation of the pn-junction to be performed simultaneously in one process step.

Figures 6 and 7 show a Schottky diode in which the exposed n- conducting layer 23 at the surface of the component is passivated using the process according to the invention, to produce an insulating layer 24 at the surface of the n-conducting layer 23. In this case also the electrical field between the anode 15 and the n-conducting layer 23 is decreased by the passivation.

Naturally the method for passivating parts of the surface of silicon carbide as described in the examples can be used on a sheet of silicon carbide with a large number of semiconductor components spread over the sheet. The technique is also suitable for all types of SiC semiconductor components in which a voltage-absorbing pn-junction is to be passivated.

A couple of experiments illustrate the efficiency of the insulating layer 20, 21, 24 formed. In an experiment to investigate the breakthrough voltage for the Schottky barrier of a point contact it was found that this amounted to approximately 20-25 V for the crystalline silicon carbide material, whereas the insulating material obtained by etching showed less than lOOnA current at a pre- voltage amounting to 400 V, and breakthrough occurred at even higher voltages. Similar experiments have also been performed on a simple mesa-etched pn-junction. When the pn-junction was treated with an insulating edge layer 20, 21, 24 in accordance with the invention, the breakthrough voltage was increased from approximately 250 V to approximately 600 V. The balance between full etching and the creation of an insulating layer is mastered by controlling a parameter, e.g. the current density. Consequently, etching and passivation can be achieved in a single process step by controlling the light intensity during etching. Automatic edge passivation can be obtained by the use of a mask having varying transparency. A mask is used during the etching process to define the areas to be photo-excited, using semi-transparent surfaces in the mask at the periphery of the sample, for instance. A protective insulating layer is thus formed at the same time.

Claims

1. A semiconductor component comprising a pn-junction (11) where both the p-conducting layer (10) and the n-conducting layer (12) constitute doped layers of silicon carbide (SiC), characterized in that the edges (16) of the pn-junction (11) are passivated with a semi- insulating layer (20) which, if reverse voltage occurs on the pn- junction (11), shunts a weak current in the reverse direction of the pn- junction, thereby reducing the electrical field at the edges (16) of the junction.

2. A semiconductor component as claimed in claim 1, characterized in that the edges (16) of the pn-junction (11) are passivated with a semi-insulating silicon carbide layer (20) which, if reverse voltage occurs on the pn-junction (11), shunts a weak current in the reverse direction of the pn-junction, thereby reducing the electrical field at the edges (16) of the junction.

3. A semiconductor component as claimed in claim 1, characterized in that the semiconductor component consists of either a diode, MOSFET-transistor, bilateral transistor, thyristor or an IGBT- transistor.

4. A semiconductor component comprising a conducting surface layer (23) doped with silicon carbide, characterized in that the conducting layer (23) is passivated so that a semi-insulating layer (24) appears at the surface.

5. A semiconductor component as claimed in claim 4, characterized in that the conducting layer (23) is passivated so that a semi-insulating layer (24) of silicon carbide appears at the surface.

6. A process to passivate a surface of a semiconductor component (1) made of silicon carbide, characterized in that the electrical and structural properties at the surface of the silicon carbide are modified in a chemical process in which the surface of the component (1) to be passivated is arranged to constitute one of the electrodes in an electrolysis reaction during which the surface of the silicon carbide is illuminated by light (6), the magnitude of the applied voltage and current during the electrolysis and the intensity of the light (6) on the surface of the silicon carbide allowing the silicon carbide surface to be completely etched or restructured by means of incomplete etching, to form a resistive layer (20, 21, 24) whose insulating properties are determined by the voltage and current applied during the electrolysis and the intensity of the light (6) on the surface of the silicon carbide.

7. A process as claimed in claim 6, characterized in that the light (6) used in the electrolytic process is UV light.

8. A process as claimed in claim 6 or 7, characterized in that the etching is effected on a planar semiconductor structure comprising a pn-junction (11), the etching being arranged to be performed to a greater depth through the layer (10) of the component of a first charge type, down into a layer (12) of a different charge type located below, whereby edge termination of the pn-junction (11) and passivation thereof are performed in one process step.

9. A process as claimed in claim 6 or 7, characterized in that a constant photo-excitation intensity during the etching, simultaneously with low current density, produces high resistivity in the insulating layer (20, 21, 24), whereas a high current density produces complete etching of the silicon carbide surface.

10. A semiconductor component manufactured according to the process claimed in claim 6 or 7 or 8, characterized in that it comprises a pn-junction where both the p-conducting layer (10) and the n- conducting layer (12) in the pn-junction (11) are produced as doped layers of silicon carbide (SiC) and that the edge (16) of the pn-junction (11) is adjacent to a semi-insulating layer (20, 21) of SiC.

11. A semiconductor component as claimed in claim 10, characterized in that the semiconductor component consists of either a diode, MOSFET-transistor, bilateral transistor, thyristor or an IGBT- transistor.

12. A semiconductor component manufactured according to the process claimed in claim 6, characterized in that it comprises a conducting layer (23) doped with silicon carbide and that the conducting layer (23) is passivated so that a semi-insulating layer (24) appears at the surface.

13. A semiconductor component as claimed in claim 12, characterized in that the semiconductor component consists of a Schottky diode.