WO1995031003A1

WO1995031003A1 - Manufacture of electronic circuit device

Info

Publication number: WO1995031003A1
Application number: PCT/JP1995/000823
Authority: WO
Inventors: Yuuichi Hamamura; Yasuo Nakagawa; Fumikazu Ito; Tateoki Miyauchi; Yasuhiko Hara
Original assignee: Hitachi, Ltd.
Priority date: 1994-05-06
Filing date: 1995-04-26
Publication date: 1995-11-16
Also published as: JPH07302826A; JP3367201B2

Abstract

An electronic circuit device manufacturing method and system by which an electronic circuit device having desired electronic circuit characteristics can be manufactured. After an arbitrary step of forming a layer of the electronic device, the shape of the pattern or the physical values of the layer are measured, or the monitoring information during the step about the manufacturing system are collected. The manufacturing process after the step is predicted by a simulator using the monitoring information to optimize the manufacturing conditions after the step or to correct the patterns. Since the manufacture process of the electronic circuit device is progressed by making necessary correction on patterns or manufacturing conditions, defective electronic circuit devices which have been discarded are recovered as nondefective products, resulting in an improvement in yield and a reduction in developing time.

Description

Specification

Manufacturing method of electronic circuit device

The present invention relates to a method of manufacturing an electronic circuit device such as a semiconductor and an SI, a TFT, etc., and particularly measures a pattern shape and a physical property value on a wafer or a substrate in the middle of a manufacturing process, and obtains the measured information, The present invention relates to a manufacturing method for stably manufacturing an electronic circuit device with a high yield by optimizing processes after the manufacturing process based on information monitored by a manufacturing device. Background art

In recent years, the miniaturization of electronic circuit devices and the increase in the number of layers in the vertical direction of the substrate have increased the difficulty of manufacturing, and the development and manufacturing have been extended for a long time. The conventional method of inspecting and selecting non-defective products after the completion of manufacturing not only does not provide a sufficient yield, but also leads to a longer period of development and manufacturing due to failure measures being taken after the completion of manufacturing. Would.

Therefore, recently, various simulators that predict the manufacturing process at the time of design have been developed, and are contributing to high yield and shortening the development period.

Japanese Patent Application Laid-Open No. 63-249328 discloses a method of simulating the optimum manufacturing conditions of a semiconductor currently manufactured in the next and subsequent processes by using processing history information and semiconductor inspection information for each process in a semiconductor manufacturing line. The method to be determined by the application is shown.

However, this known example is an invention in which the variation in the manufacturing conditions in the previous process is corrected only in the subsequent process steps without making any correction for the portion where the processing is completed. Such miniaturization and multilayering In advanced semiconductors, as the design changes in the next process and subsequent steps are repeated, the burden on the subsequent manufacturing increases (for example, the difficulty of the subsequent processes increases and the yield decreases). However, issues such as how to make defective parts non-defective, which cannot be addressed only by optimizing the manufacturing conditions after the next process, remain unsolved. Disclosure of the invention

An object of the present invention is to provide a method of manufacturing an electronic circuit device which solves this problem.

According to the present invention, after an arbitrary manufacturing process of the electronic circuit device, the measurement results of the shape and physical property values of the processed pattern and the monitor information of the manufacturing history up to the arbitrary manufacturing process are used. Information on the actual pattern state of the layer is obtained, and the manufacturing process of the next layer and subsequent layers is simulated to predict whether the product will be good or defective, and if it is predicted to be defective,

(1) Modify the part where processing is completed

(2) Optimize processing conditions to be received thereafter

Based on the options, the most appropriate processing is provided by a simulator and a database.

According to the present invention, defects caused by difficult manufacturing, variations in manufacturing equipment, long-term fluctuations, etc., are either time-consuming or economical. It is possible to shorten the development period and reduce manufacturing costs, not to mention high yield, because it is possible to judge products by considering whether they are efficient and technically reliable or not. BRIEF DESCRIPTION OF THE FIGURES FIG. 1 is a flowchart of a manufacturing method according to a first embodiment of the present invention. FIG. 2 is a diagram showing a manufacturing system according to a first embodiment of the present invention. FIG. 3 is a flowchart of a detailed processing procedure of the first embodiment of the present invention. FIG. 4 is a flowchart of the manufacturing method according to the first embodiment of the present invention. FIG. 5 is a sectional view of an LSI according to a first embodiment of the present invention. FIG. 6 is a sectional view of an LSI according to a first embodiment of the present invention. FIG. 7 is a plan perspective view from above of the LSI according to the first embodiment of the present invention. FIG. 8 is an LSI cross-sectional view of the first embodiment of the present invention. FIG. 9 is a sectional view of an LSI according to a first embodiment of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Example 1)

Fig. 1 shows an example of applying this manufacturing method to an LSI manufacturing line. The LSI manufacturing line 11 includes a first step 1 to a final step 10. After completion of this optional n-th step 2, pattern inspection and measurement 3 are performed, and simulation is performed to determine whether the next step and subsequent steps will be non-defective or non-defective by processing under the preset process conditions. Predict. In the case of a non-defective product, perform the n + 1 process as scheduled. In the case of defective products, determine whether the cause of this defect can be eliminated by correcting the pattern 8 or whether the correction will be made by optimizing the manufacturing conditions (hereinafter, recipe) 7 after the n + 1 step In addition, there is a feature of the present invention in executing. Fig. 2 shows the manufacturing system of this embodiment.

As shown in FIG. 2, the production line 11

(I) Various manufacturing apparatuses such as an oxidation furnace, a mask manufacturing apparatus, an exposure apparatus, a film forming apparatus, an etching apparatus, and an ion implantation apparatus.

(B) Optical inspection equipment, STM, AFM, TEM, measuring SEM, focusing An inspection device 22 that measures the shape of a pattern such as a cross-sectional observation device using an electron beam, and measures physical properties using an analyzer such as an Auger or ion microanalyzer.

(C) a transfer device 26 for transferring a wafer between these devices;

(Ii) In case of repairing the wafer after inspection, it is composed of a correction device 23 such as a focused ion beam processing device or a laser CVD device. A computer 27 that controls the individual devices and a host computer 28 that controls these devices are provided. Computer 2 7

(a) Control signals for the transfer order between manufacturing equipment,

(β) Recipe information such as dimensions (eg mask CAD information), processing temperature, processing time, gas pressure, energy, raw materials, etc.

(7) Send information such as inspection locations and inspection conditions, and control the transport device 26, manufacturing device 20, and inspection device 22.

On the other hand, the manufacturing apparatus 20 monitors the film formation conditions such as the film formation temperature and time during film formation, the etching speed 'time during etching, the oxidation / diffusion temperature, The information monitored and measured during the manufacturing process, such as the energy and dose of ion implantation (hereinafter referred to as device monitor information), is sent back to the host computer 28. The relationship between the device monitor information and the result measured by the inspection device 22 is stored in the database 29.

By the way, LSI design is performed using a process simulator incorporated in the simulator 32 and a device simulator, etc., and a physical model (hereinafter referred to as a work model) of the pattern shape and physical properties in each process is created in advance. And record it in database 31. The completed SI threshold voltage and frequency characteristics (hereinafter, electrical characteristics) are stored in database 33, and recipes are stored in database 35. The above-mentioned various simulators and various databases are all managed by the host computer 28.

The detailed processing procedure by this manufacturing system will be described with reference to FIG.

First, in the nth step,

(1) A process 45 of converting the obtained device monitor information 42 into a shape / physical property value is performed in the database 29, and the n-process shape and physical property value information 46 after this process,

After the end of the nth process,

(2) n-process completed wafer shape and physical property value information 4 3 collected by the inspection device 2 2

(3) For the shapes and physical properties of the patterns that are not actually inspected, using the work model (predicted version) 44 of the n-th process already stored in the database 31,

The work model of the n-th process, which approximates the actual pattern as much as possible, is determined by the work model analysis computer 30, which is used as the n-process work model (determined version) 48 and stored in the database 31. . next,

(a) Work model of this n-th process (final version) 48

(b) Work model (final version) 40 from the 1st process to the n-1st process already stored in database 31;

(c) Using the recipe (provisional version) 41 from the (n + 1) th process onwards stored in the database 35, a work model (predicted version) is created by the process simulator until the final process is completed. Perform processing 49.

Using the work model (predicted version) 50 up to the completion of this final process, the electrical characteristics are predicted 51 by the device simulator 27.

Using these prediction results, the database 33 If the predicted electrical characteristics satisfy the design values, the recipe (provisional version) 4 1 after the (n + 1) th process should be changed from (preliminary version) 5 3 to The work model (expected version) for the (n + 1) th and subsequent steps will be updated, and the (n + 1) th step 9 will be continued. If the predicted electrical characteristics do not satisfy the design values,

(A) Whether satisfactory electrical characteristics can be obtained,

(B) Is a stable yield expected?

(ゥ) Based on the database, it is determined whether it is advantageous to change the recipe from the viewpoint of maintaining low cost, etc., or it is advantageous to modify the n-process completed wafer. If high yield and low cost can be expected, {Start Step A}

In the work model analysis computer 30, a failure cause analysis 57 was performed by comparing the n-process work model (predicted version) 44 with the n-process work model (final version) 48. Change the recipe after n + 1 process 5 8

(i) The modified process recipe for the (n + 1) th and subsequent steps (modified version) 60,

(i i) Work model (final version) 40 from 1st to nth — 1 process,

(iii) Using the work model of the nth process (final version) 48

The electrical characteristics are predicted again, and the quality of the electrical characteristics is determined.

{End of step A}

Then, repeat {Step A} until the electrical characteristics satisfy the design values. If the design values are satisfied, register the recipe (modified version) 5 9 for the (n + 1) th process and later in the (confirmed version) 53 Based on this, the manufacturing of the (n + 1) th and subsequent steps is performed. When it is determined that the change of the recipe is inappropriate in the determination 54, the correction conditions for the n-step completion wafer are obtained and the correction 8 is executed. In this case, this fix 5 5 It is necessary to update the n-process peak model (final version) 48 on the peak model analysis computer 30 using, and save it back to the database 31. In decision 5 4 above, recipe optimization 7 and correction 8 were selected based on the database. Before making this decision 5 4, perform {Step A} to determine whether recipe optimization 7 is possible. There are ways to judge and, if possible, take action.

There is also a method of storing only the correction information 55 and performing correction after the end of the final process 10 based on this. It is also possible to combine such modification 8 with recipe optimization 7. In other words, a method for optimizing the recipe 7 for a certain part and correcting the remaining part 8 and a method for optimizing the recipe 7 taking the correction information 5 5 into account after performing the correction 8 Can be considered.

Here, FIG. 4 shows a flow chart of the whole manufacturing method of this embodiment. After completing the final process 10 of the production line while optimizing and modifying the recipes 7 and 8 as described above, the electrical characteristics of this electronic circuit device were actually evaluated using an electric circuit tester, electron beam tester, etc. Do 1 3 In the case of a defective product, the cause of the defect is estimated by using a debugging tool or the work model obtained so far, and a failure analysis is performed using a visual inspection device, a cross-sectional observation device, an analysis device, etc., and thereafter. Implement measures 15 to reflect in the manufacturing conditions of any process of the product to be manufactured. In addition, by performing local correction of the LSI after the completion of the final process using a focused ion beam processing device or laser CVD device, etc. It can be reflected in the design data and in the manufacturing conditions of any process of the products manufactured thereafter.

Also, products that have a similar pattern to those once manufactured by this method In the case of remanufacturing products, measures such as the shape and physical properties of patterns that have been inspected and measured 3 in the past are used to implement countermeasures. it can.

Specific examples using the recipe optimization method 7 are shown in Figs. 5, 6, and 7 using general LSI.

First, FIG. 5 shows a cross-sectional structure of the LSI, and FIG. 5a shows a cross-section at the time of design. It is assumed that the design value of the implantation depth of the impurity into the source 72a and the drain 73b is d, and that the actual inspection 3 results in d + α as shown in FIG. 5b. Therefore, as shown in Equations 1 and 2, the gate length may be changed from L g to L g + 2σα in order to keep the transfer conductance Gm as designed.

G m = Z / L eff-μ C (V g · V th) (Equation 1) G m; transfer conductance

Z: Gate width

L eff; effective gate length

β; carrier mobility

V g; Gate voltage

V th; threshold voltage

C: capacitance per unit area

L eff = L g-2 σ d (Equation 2)

L g Gate length

d Junction depth

And the ratio of the diffusion constant in the horizontal direction to the vertical direction Also, if the design value of the thickness of the gate insulating film 71 is t and the value of the actual inspection 3 is kXt as shown in FIG. Gate length

k L g-2 σ d (k-1).

C X t = con st t. (Equation 3)

C: capacitance per unit area

t: Thickness of gate insulating film If the photomask information is affected by a change in the gate length, the optimization is realized only after procedures such as design change and manufacturing of the photomask. This cannot be achieved only by changing the recipe of the manufacturing apparatus that forms the target.

Also, even if the next process change can be optimized as described above, it is possible that this design change will affect the subsequent parts. For example, if the gate length was L g in the initial design as shown in Fig. 6a, but L g + α as shown in Fig. 6b, the wiring on both sides was used. Since a and 75b are obstacles, the position of the contact hole 76 for connecting the wiring to the wiring 75 and the source 72 and the drain 73 must be changed. Furthermore, as shown in Fig. 7 (this figure is a perspective plan view from above the LSI), if the contact hole cannot be sufficiently moved by parallel movement of the contact hole alone, it is shown in Fig. 7b. Therefore, it is necessary to make use of the extra space of drain 73 to increase the contact area. As described above, changing the process recipe of one process has a chain effect on the subsequent processes, so that the process simulation 49 predicts the work model 50 up to the final process, and Electrically powered by its model 50 That is, it is necessary to confirm whether or not it works by using the device simulation 51.

Figure 8 shows examples of other optimizations. If the contact hole to be wired to the diffusion layer is not formed as designed as shown in Fig. 8a and there is an etching residue 78 as shown in Fig. 8b, contact between this diffusion layer 77 and wiring 75g The stakes become too large. Here, the amount of increase in the resistance is calculated based on the result of the inspection 3, and the thickness T or the width of the wiring is changed to reduce the resistance of the wiring itself by the increased amount.

Next, an example of Modification 8 is shown. FIG. 9 shows an example in which optimization 7 was performed when the impurity concentration of the diffusion layer was low. However, SI uses a manufacturing method in which impurity ions are implanted using the gate 70 as a mask. After the impurity implantation, it is assumed that the impurity concentration is insufficient when actually measured. (Figure 8a) In this case, utilizing the fact that the gate 70 serves as a mask, the wafer is returned to the implantation apparatus again, and correction is performed by additionally implanting the missing impurity ions. I do. It is also possible to carry out the correction 8 by performing additional etching in the same manner on the remaining etching 7 8 as shown in FIG. It is also possible to perform local correction using a focused ion beam device or laser CVD device.

In this embodiment, only the manufacture of the LSI has been described, but the present invention can be applied to the manufacture of all other electronic circuit devices such as semiconductors and thin film devices such as TFT.

The production line of the present embodiment can be applied to both a prototype line and a mass production line, and can be a production method that enables mass production without trial production. As production progresses, it is possible to achieve high yields, such as returning defective electronic circuit devices to non-defective products, and shorten the development period.

Claims

The scope of the claims

1. A method of manufacturing an electronic circuit device, comprising: processing a substrate of the electronic circuit device to form an electronic circuit on the substrate; The state of the apparatus during the processing of the substrate is monitored, and after the substrate is processed by the processing apparatus, the surface shape and physical property values of the processed substrate are measured. Based on the information obtained by the measurement and the information of the process design of the manufacturing process after the manufacturing process in the middle, the completion state of the electronic circuit device is predicted by simulation, and based on the result of the prediction. A method for manufacturing an electronic circuit device, characterized in that the electronic circuit device is manufactured by optimizing process conditions in steps after the intermediate manufacturing process.

2. Based on the result of predicting the completed state of the electronic circuit device by simulation, the process condition of each process up to the intermediate manufacturing process is optimized to manufacture the next electronic circuit device. The method for manufacturing an electronic circuit device according to claim 1, wherein

3. Inspecting the electronic circuit device manufactured by optimizing the process conditions of the processes after the intermediate manufacturing process, and feeding back the inspection result to the manufacturing process of the electronic circuit device. The method for manufacturing an electronic circuit device according to claim 1, wherein

4. A method of manufacturing an electronic circuit device, comprising: processing a substrate of the electronic circuit device to form an electronic circuit on the substrate; The state of the apparatus during the processing of the substrate is monitored, and after the substrate is processed by the processing apparatus, the surface shape and physical property values of the processed substrate are measured. The information obtained by the measurement, and the process design of the manufacturing process after the manufacturing process in the middle Based on this information, the completion state of the electronic circuit device is predicted by simulation, and as a result of the prediction, even if the process conditions of the processes after the manufacturing process in the middle are optimized, the electronic circuit device is desired. If it is determined that the characteristics of the electronic circuit device cannot be obtained, the cause of the failure to obtain the desired characteristics is analyzed, the electronic circuit device processed by the processing device is corrected, and the cause is removed. A method for manufacturing an electronic circuit device, comprising: performing the steps after the manufacturing process described above to manufacture the electronic circuit device.

5. Based on the result of predicting the completed state of the electronic circuit device by simulation, the process condition of each process up to the intermediate manufacturing process is optimized to manufacture the next electronic circuit device. 5. The method for manufacturing an electronic circuit device according to claim 4, wherein:

6. A method of manufacturing an electronic circuit device, the method comprising: processing a substrate of the electronic circuit device to form an electronic circuit on the substrate; The state of the apparatus during the processing of the substrate is monitored, and after the substrate is processed by the processing apparatus, the surface shape and physical property values of the processed substrate are measured. A physical model up to the intermediate manufacturing process is created based on the information obtained by the measurement.- A process simulation is performed based on the physical model and predetermined design information of the manufacturing process after the intermediate manufacturing process. A physical model of the completed electronic circuit is predicted, and the electrical characteristics of the completed electronic circuit are analyzed by device simulation based on the predicted physical model of the electronic circuit, and a non-defective electronic circuit is analyzed. Is completed or a defective electronic circuit is completed. If it is confirmed that a non-defective product is completed, the processing device is determined based on the predetermined design information of the manufacturing process after the intermediate manufacturing process. When the electronic circuit device is manufactured by performing the steps after the above-mentioned manufacturing process on the substrate processed in the above, and it is confirmed that a defective product is completed, the cause of the defect is analyzed and the failure is analyzed. Force to correct the substrate processed by the processing apparatus so that the good cause is removed, or change the design information of the manufacturing process after the intermediate manufacturing process, and perform the process after the intermediate manufacturing process, A method of manufacturing an electronic circuit device, comprising manufacturing the electronic circuit device.

7. The method for manufacturing an electronic circuit device according to claim 1, wherein a local correction is performed after the completion of the manufacturing process.

8. The method of manufacturing an electronic circuit device, wherein the electronic circuit device is manufactured through a plurality of processing steps, wherein the processing apparatus performs the processing in the middle of the plurality of processing steps. Using the monitor information that monitors the state of processing and the measurement information obtained by measuring the surface shape and physical property values of the electronic circuit device in the middle of the plurality of processing steps processed by the processing device, By creating a physical model of the electronic circuit device halfway, and comparing the created physical model with a physical model up to the halfway processing step predicted in advance based on design information of the electronic circuit device, It is determined whether to correct the electronic circuit device that has been processed up to the intermediate processing step or to change the design information of the processing steps subsequent to the intermediate processing step, based on the determined result. Method of manufacturing an electronic circuit device, which comprises processing the electronic circuit device are.

9. A plurality of manufacturing means corresponding to a plurality of manufacturing steps for manufacturing the electronic circuit device, and the electronic circuit device is manufactured by at least one manufacturing step in the middle of the plurality of manufacturing steps. Monitoring means for monitoring physical information during processing; inspection means for measuring the shape and physical property values of the pattern of the electronic circuit device processed by the manufacturing means and having a pattern formed on a surface; and the manufacturing means The processing means connected to each of the inspection means and storing the processing conditions of the manufacturing means and the inspection conditions of the inspection means; Computer means for controlling the inspection means; physical information monitored by the monitoring means; information on the shape and physical properties of the pattern of the electronic circuit device measured by the inspection means; A process simulation for predicting a shape of a circuit pattern finally formed in the electronic circuit device based on processing conditions of the manufacturing means in a manufacturing process after a manufacturing process; and the predicted circuit. A device simulator for predicting the electrical characteristics of the electronic circuit device based on the shape of the pattern; controlling the computer means, the process simulator and the device simulator, and controlling the predicted electrical characteristics. The electronic circuit device is manufactured by modifying processing conditions of the manufacturing means in at least one manufacturing process after the manufacturing process based on characteristics. Manufacturing system of the electronic circuit apparatus characterized by comprising a host computer means for.

10. A plurality of manufacturing means corresponding to a plurality of manufacturing steps for manufacturing the electronic circuit device, an inspection means for measuring the shape and physical property values of the pattern of the electronic circuit device during the manufacturing of the electronic circuit device, Correcting means for the electronic circuit; monitoring means built in the manufacturing means for monitoring physical information during processing; computer means connected to each of the manufacturing means, the inspection means, and the correcting means; A process simulation for predicting the shape of a circuit pattern formed on the electronic circuit device using the processing conditions of the manufacturing means, and a device for predicting the electrical characteristics of the electronic circuit device based on the shape and physical properties of the pattern A simulation, wherein the information monitored by the monitoring means, the information inspected by the inspection means, and the processing conditions of the manufacturing means in a manufacturing process after the manufacturing process. The shape of a circuit pattern finally formed in the electronic circuit device is predicted by the process simulator based on the process simulator, and based on the predicted shape of the circuit pattern finally formed in the electronic circuit device. Then, the device simulator predicts the electrical characteristics of the electronic circuit device. And correcting the electronic circuit device manufactured up to the intermediate manufacturing process by the computer means based on the result of the predicted electrical characteristic, or designing the manufacturing process after the intermediate manufacturing process. A system for manufacturing an electronic circuit device, comprising: determining whether to change information; and processing the electronic circuit device based on a result of the determination.

11. Create a physical model up to the desired process from the shape and physical property values of the electronic circuit up to the desired process measured by the inspection means and monitor information up to the desired process measured by the manufacturing means. Then, a physical model of the completed electronic circuit is predicted by a process simulation based on the physical model and predetermined design information of a manufacturing process subsequent to the desired process, and the predicted electronic circuit The electrical characteristics of the completed electronic circuit are analyzed by device simulation based on the physical model, and it is checked whether a good electronic circuit is completed or a defective electronic circuit is completed. If it is confirmed that a good electronic circuit is manufactured based on the design information of the manufacturing process subsequent to the desired manufacturing process determined in advance and a defective product is completed, The cause of the failure is analyzed to determine whether to correct the electronic circuit device up to the desired process so as to remove the cause of the failure, or to change design information of a manufacturing process subsequent to the desired manufacturing process. The electronic circuit device, wherein the electronic circuit device is manufactured by performing the following and subsequent manufacturing of the desired manufacturing process.