WO1995014269A1

WO1995014269A1 - A high-performance host interface for networks carrying connectionless traffic

Info

Publication number: WO1995014269A1
Application number: PCT/US1994/013379
Authority: WO
Inventors: C. Brendan S. Traw; Jonathan M. Smith
Original assignee: The Trustees Of The University Of Pennsylvania
Priority date: 1993-11-19
Filing date: 1994-11-18
Publication date: 1995-05-26

Abstract

Disclosed is a method for use by a host interface in receiving connection-based or connectionless data that has been segmented into a plurality of cells, wherein each cell comprises at least a virtual circuit identifier (VCI) and a cell body. The method comprises the steps of: storing each cell body in a dual port reassembly buffer (20-8); generating and storing in a pointer memory (20-7) a linked list comprising a plurality of pointers, wherein each pointer identifies where in the dual port reassembly buffer a corresponding one of the cell bodies is stored; and storing in a content addressable memory (CAM 20-2) a VCI at a location that refers to a location in the pointer memory at which the linked list is accessible. Each linked list is accessible by referring to its corresponding VCI. In addition, the linked list is organized as a first item and a plurality of nodes with each node identifying a storage location of a corresponding cell body and the first item identifying the last node in the linked list, the first node in the linked list, and the number of cells represented by the linked list.

Description

A HIGH-PERFORMANCE HOST INTERFACE FOR NETWORKS CARRYING

CONNECTIONLESS TRAFFIC

CROSS-REFERENCE TO RELATED APPLICATION

This is a continuation-in-part of copending U.S Patent Application Serial No. 708,775, filed May 28, 1991, titled "A High-Performance Host Interface for ATM Networks," now U.S. Patent No. 5,274,768, issue date December 28, 1993, which is hereby incorporated by reference as if fully set forth herein. FIELD OF THE INVENTION

The present invention relates to an interface between a telecommunications network and a network element, e.g., a host computer. The present invention may be employed for segmentation and reassembly of either connection-based traffic (e.g., virtual circuit traffic) or connectionless traffic (e.g., datagram traffic) . BACKGROUND OF THE INVENTION

One preferred embodiment of the present invention is disclosed in the above-cited application serial no. 708,775, now U.S. Patent No. 5,274,768. The disclosure of preferred embodiments in that application emphasized, but did not restrict the disclosed invention to, use of the host interface in connection with the segmentation and reassembly of connection-based asynchronous transfer mode (ATM) data including a virtual circuit identifier (VCI) . The instant specification describes a presently preferred embodiment of the invention that acts as a host interface for receiving and transmitting Class 4 ATM Adaptation Layer (AAL4) cells, which constitute connectionless traffic. However, it should be noted that, except where they are expressly so limited, the claims at the end of this specification are by no means limited to applications of the invention involving AAL4 cells. For example, the Class 5 ATM Adaptation Layer is another known mechanism for supporting connectionless traffic. Moreover, connectionless traffic is not necessarily limited to Class 4 and Class 5 ATM Adaptation Layer formats, as other AALs may be developed to carry this traffic. Briefly, the difference between a connection- based system and connectionless system can be explained as follows: The interface between a node of a communications network and a network element, such as a host computer, may provide virtual circuit and/or datagram service. With a virtual circuit interface, the user performs a call request to set up a virtual circuit between a source and a destination. The user may use sequence numbers to exercise flow control and error control. However, virtual circuits do not necessarily require sequence numbers or flow control. The interface attempts to deliver packets of data in the proper sequence. With datagram service, the interface only attempts to handle packets independently. It does not construct a dedicated path (virtual circuit) between endpoints. A major advantage of datagram service is its robustness and flexibility. If nodes or links in the interface are unavailable, datagrams can be routed around the affected area. In contradistinction, the loss of a node could destroy a virtual circuit. Similarly, the datagram mechanism can react more quickly to congestion by making routing decisions on a per-packet basis. With virtual circuits, routing decisions are usually made only during call setup. Of course, virtual circuits can be changed dynamically by expending processing overhead. An advantage of the virtual circuit mechanism is that it minimizes per-packet overhead, since routing decisions need only be made once per virtual circuit. In addition, virtual circuits provide sequenced packet delivery, which is an asset if the external network provides virtual circuit service. Moreover, regarding the external network, the datagram method may allow for efficient use of the network, since no call setup or disconnection is required and there is no need to hold up packets while a packet in error is being retransmitted. The latter feature is important in some real-time applications. The virtual circuit mechanism, on the other hand, can provide end-to- end sequencing, flow control, and error control. However, in many cases these services are provided by a higher level protocol and need not be duplicated by the network service. Therefore, there are advantages and disadvantages associated with both the connection-based (virtual circuit) and connectionless (datagram) systems.

Figure 1 depicts the formats of an ATM cell 10 and an AAL4 cell 12. As shown, both the ATM cell 10 and AAL4 cell 12 include a cell body portion and an ATM header portion, the latter composed of five bytes, two of which form a VCI and three bits of which form a Payload Type field. The cell body portions of the two cell formats are different in that the cell body of the connection-based ATM cell format includes forty-eight bytes of user data whereas the cell body of the connectionless AAL4 cell format includes an AAL4 header, a payload comprising forty-four bytes of user data, and an AAL4 trailer. The AAL4 header includes, among other things, a Segment Type Identifier and a Multiplexing Identifier (MID) . The AAL4 trailer includes a Length Indicator and a CRC-10 error code. In comparison, the Class 5 ATM Adaptation Layer provides connectionless data transfer without the overhead associated with the AAL4. The AAL5 lacks the AAL header and trailer in the ATM cell body and, instead, relies on specific values of the Payload Type field in the ATM header to determine datagram framing. The reader is referred to application Serial No. 708,775, now U.S. Patent No. 5,274,768, for further background on high speed ATM networks. SUMMARY OF THE INVENTION A goal of the present invention is to provide an interface between a network element and a telecommunications network that operates at near Gbps speeds, is compatible for use with the ATM transmission technique, and may be employed in both connection-based and connectionless systems.

The present invention provides a reassembler for use in reassembling received data that has been segmented into a plurality of cells each of which comprises at least a virtual channel identifier (VCI) and a cell body. According to the invention, the reassembler comprises first means for separating each cell body from its corresponding VCI and determining respective linked list reference addresses for the VCIs; a reassembly buffer storing the cell bodies; and a linked list manager storing linked list data indicative of addresses at which the cell bodies are stored in the reassembly buffer. In preferred embodiments of the invention, the first means, reassembly buffer, and linked list manager operate in parallel and form a cell processing pipeline. One presently preferred embodiment of the invention is adapted for use in reassembling connectionless data. The connectionless data comprises data that has been segmented into a plurality of cells each of which comprises a VCI, a multiplex identification (MID), and a length indicator. However, it is noted that the MID and length indicator are not always required. What is needed is datagram framing information. In the case of AA 4, this information is determined from the Segment Type field in the AAL header whereas, in the case of AAL5, framing information is determined from the Payload Type field in the ATM header. The present invention is not limited to these examples. In preferred embodiments, the linked list manager comprises a pointer table storing the linked list data. In addition, in preferred embodiments the reassembly buffer comprises a reassembly memory for storing the cell bodies, and a reassembly controller for writing/reading cell bodies to/from the reassembly memory. Preferably, the reassembly memory comprises a dual port random access memory. Furthermore, in preferred embodiments the first means comprises a cell manager for separating each cell body from its corresponding VCI and detecting whether the VCI has been corrupted; a content addressable memory (CAM) storing the VCIs and providing pointers into the linked list data; and a look-up controller for writing the VCIs to the CAM. The present invention also provides a method for reassembling received data. According to one embodiment of the invention, the method comprises the steps of separating each cell body from its corresponding VCI and determining respective linked list reference addresses for the VCIs; storing the cell bodies; and storing linked list data indicative of addresses at which the cell bodies are stored.

Another embodiment of the present invention provides a method, for use by a host interface between a network node and a host device, for receiving data that has been segmented into a plurality of cells, wherein each cell comprises at least a VCI and a cell body. This method comprises the steps of: storing each cell body in a first memory; generating and storing in a second memory a linked list comprising a plurality of pointers, wherein each pointer identifies where in the first memory a corresponding one of the cell bodies is stored; and storing in a third memory an identifier that indicates a location in the second memory at which the linked list is accessible. In one presently preferred embodiment of this method, the third memory is a CAM and each of the identifiers corresponds to a VCI. Accordingly, each linked list is accessible by referring to its corresponding VCI. In addition, in the preferred embodiment, the linked list is organized as a first item and a plurality of nodes, with each node identifying a storage location of a corresponding cell body and the first item identifying the last node in the linked list, the first node in the linked list, and the number of cells represented by the linked list.

Other features of the present invention are disclosed below. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic depiction of the formats of an ATM cell and an AAL4 cell.

Figure 2 is a block diagram of a Segmenter in accordance with the present invention.

Figure 3 is a block diagram of a Reassembler in accordance with the present invention.

Figure 4 is a schematic depiction of a control structure for virtual circuit reassembly in accordance with the present invention.

Figure 5 is a schematic depiction of a control structure for connectionless traffic (e.g., CS-PDU) reassembly in accordance with the present invention. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Figure 2 is a block diagram of a Segmenter 18 in accordance with the present invention. As shown, the Segmenter 18 is adapted for connection to a MicroChannel Bus 14 via a MicroChannel Bus interface 16. The MicroChannel Bus does not form part of the present invention and is not disclosed in detail herein. The MicroChannel Bus Interface 16 is described in detail in the above-cited application serial No. 708,775, now U.S. Patent No. 5,274,768. As shown, the Segmenter 18 comprises a data buffer 18-1, which in presently preferred embodiments includes a 512 by 32 FIFO; a Class 4 AAL Generator 18-2; a Segmentation Controller 18-3; an ATM header Generator 18-4; and a Physical Layer Board 18-5 comprising a SONET framer and an electrical to optical converter that converts electrical signals to OC-3c optical signals. The Segmentation Controller 18-3 is responsible for controlling the generation of ATM cells. It monitors the FIFO data buffer 18-1; extracts cell bodies from the FIFO data buffer; controls the generation of an ATM header and, if necessary, an AAL4 header and trailer for the cell body; and, finally, hands the completed cell off to the Physical Layer 18-5 at the appropriate time.

Figure 3 is a block diagram of a Reassembler 20 in accordance with the present invention. Like the Segmenter 18, the Reassembler 20 is adapted for connection to the MicroChannel Bus 14 via the MicroChannel Bus Interface 16. As shown, the Reassembler 20 comprises a Cell Manager 20-1; a Content Addressable Memory (CAM) Lookup Controller 20-2; a Linked List Manager 20-3; a Dual Port Reassembly Buffer Controller 20-4; and a Physical

Layer Board 20-5 comprising a SONET framer and an optical to electrical converter. In addition, the CAM Lookup Controller 20-2 includes, in presently preferred embodiments, two 256 by 48 Content Addressable Memories 20- 6, providing a total of 512 entries. Furthermore, the

Linked List Manager 20-3 includes a Pointer Memory 20-7 and the Dual Port Reassembly Buffer Controller 20-4 includes a 128k by 32 Dual Port Reassembly Buffer 20-8.

For both the Segmenter and Reassembler, a variety of physical layers may be used, including SONET, Hewlett- Packard Company's GLINK, and AMD's TAXI. In presently preferred embodiments, the basic requirement for a given physical layer technology is that it can accept a byte-wide data path for both the transmit and receive directions and can operate at speeds of up to 20 MHz.

Figure 4 schematically depicts the control structures for virtual circuit reassembly, and Figure 5 schematically depicts the control structures for connectionless traffic reassembly. In presently preferred embodiments, the connectionless traffic reassembly comprises convergence sublevel protocol data unit (CS-PDU) reassembly. Briefly, AAL classes 3 and 4 share a common Convergence Sublayer (CS) . The CS-PDU comprises a payload with a header and a trailer. The CS-PDU header comprises an eight-bit Common Part Indicator (CPI) . A Beginning-End tag (BEtag) , an eight-bit field, is next. This field is duplicated in the CS-PDU trailer to ensure that the start and end SAR sublayer segments belong to the same CS-PDU. This is a mechanism to determine whether there is cell loss. Buffer Allocation Size (BAsize) is the final field. This is a 16-bit quantity used to indicate the maximum buffer size necessary to contain the CS-PDU.

The CS-PDU trailer begins with an eight-bit Alignment Field (AL) , which is used to align the CS-PDU trailer to a word boundary. The other field in the CS-PDU trailer is a 16-bit Length field that specifies the actual length of the CS-PDU payload.

Referring to Figure 4, in reassembling virtual circuit data, a VCI from the Virtual Circuit CAM 20-6a identifies the location in the Pointer Table 20-7 where the last node in the list, first node in the list, and number of cells in the list are identified. This data is then used to access the Pointer Table locations which point to the corresponding locations in the Dual Port Reassembly Buffer 20-8 where respective 48-byte cell bodies are stored. Further details of such virtual circuit reassembly are provided in application serial no. 708,775, now U.S. Patent No. 5,274,768.

Referring now to Figure 5, in reassembling CS-PDU Traffic, the Reassembler 20 employs a VCI, MID (Multiplex ID) , and a CS-PDU CAM 20-6b to identify data in the Pointer Table 20-7 indicating the last node in the list, first node in the list, number of cells in the list, and number of CS- PDU's in the list. This data identifies the next and successive items in the Pointer Table 20-7 which refer to corresponding nodes in the list and identify the node, the cell body length, the cell type, and the reassembly buffer pointer, the latter pointing into the Dual Port Reassembly Buffer 20-8 to the locations where the corresponding cell body is stored.

To provide support for connectionless traffic on the ATM network, preferred embodiments of the present invention provide hardware support for the Class 4 ATM adaptation layer (AAL4) . To provide a simple means for deciding what AAL processing to perform, a subset of the VCI space may be reserved for use with a particular AAL. The use of other adaptation layers is not prohibited by this extra support for the AAL4 , although the extra processing required to support additional adaptations layers may have to be borne by the host processor. The Segmenter 18 (depicted in Figure 2) reads data from the host's main memory (or other data source located on the MicroChannel Bus, such as, e.g., a video capture peripheral card) , segments this data into ATM cells, and then transmits it to the network at the OC-3c data rate of 155 Mbps. When data is to be transmitted, the host must first load several control registers with the source address, length, and ATM header control fields to be used, such as the VCI. If the VCI indicates that the data is to be transmitted using the AAL4, the MID must also be specified. Once this information is available, the Segmenter 18 initiates a streaming data transfer from the source of the data across the MicroChannel Bus to the Segmenter. As soon as sufficient data has been transferred into the Segmenter's data buffer 18-1, one cell's worth of data is extracted from the buffer by the Segmentation Controller 18-3 and is concatenated with an ATM header. An AAL4 header and AAL4 trailer are also added if appropriate.

Both the CRC-8 error code (for the ATM header) and the CRC- 10 error code (for the AAL4 trailer) are calculated at a rate of one byte per clock cycle as the cell header and body are passed to the SONET framer. This process is repeated until the entire block of data has been transmitted. The Reassembler 20 (depicted in Figure 4) receives data from the OC-3C network connection, reassembles it, and then delivers the reassembled data to the host's main memory or to another peripheral card on the MicroChannel Bus. To read data reassembled by the host interface, the host must specify the destination of the data, the internal list reference number of the connection/CS-PDU, and, when reading from a connection, the number of cell bodies to be transferred. The Reassembler 20 is composed of the five major functional units depicted in Figure 3. These units all work concurrently. The Cell Manager 20-1, CAM Lookup Controller 20-2, Linked List Manager 20-3, and Dual Port Reassembly Buffer Controller 20-4 form an ATM cell- processing pipeline. Only control information is passed through this pipeline in order to minimize the buffer space required for pipeline elements and to avoid repetitively copying the cell body data from state to stage. A separate data path allows cell bodies to be transferred from the Cell Manager's FIFO buffer to the Dual Port Reassembly Buffer 20-8.

The Cell Manager 20-1 verifies the integrity of the header and payload (if the cell is carrying AAL4 traffic) of the cells that are received by the SONET framer interface to the network by calculating the CRC-8 of the ATM header and the CRC-10 of the ATM cell body and comparing them with the values in the cell just received. If the values match, the cell is assumed to be intact. The Cell Manager 20-1 then extracts the VCI from the ATM header and extracts the MID, segment type, and length indicator from the AAL4 header and trailer. While these fields are being extracted and the CRCs are being verified, the cell body is placed in the FIFO buffer for later movement into the Dual Port Reassembly Buffer 20-4. Since the cell body will be placed into the FIFO buffer before its integrity can be verified, the Cell Manager is allowed to request that the body be flushed from the FIFO by the Dual Port Reassembly Buffer Controller 20-4. In one presently preferred embodiment of the invention, these operations take one cell time, or 2.7 μs at the OC-3c rate.

The CAM Lookup Controller 20-2 manages two 256- entry (48 bits per entry) content addressable memory devices. (For example, the CAMs may be AM99C10 256 by 48 content addressable memory devices from Advanced Micro Devices.) One CAM is reserved for virtual circuit traffic and the other is reserved for connectionless traffic. Thus, 256 virtual circuit connections and 256 CS-PDUs can be demultiplexed simultaneously. Virtual circuits are identified by their VCI and CS-PDUs are identified by their VCI and MID. It is also possible to employ direct lookup random access memory tables instead of CAMs. However, this option is believed to be inferior because, for CS-PDUs, the address space is 26 bits (16 bit VCI + 10 bit MID) . Larger CAMs may be employed if the 256 virtual circuit connection/CS-PDU limit proves to be confining.

When a VCI or VCI + MID is received from the Cell Manager 20-1, the CAM Lookup Controller 20-2 searches the appropriate CAM (recall that there are two CAMs in the presently preferred embodiment) for a matching entry. If none is found and an unused CAM location is available, the CAM Lookup Controller 20-2 assumes that the identifiers belong to a newly established connection or CS-PDU and writes the identifiers into the empty location. If no CAM location is available, the cell is dropped. If a match was found or a new entry was created, the CAM Lookup Controller 20-2 passes the location of the match or new entry to the Linked List Manager 20-3. This location is used as the internal reference number for the connection or CS-PDU.

The host is allowed to read the contents of each CAM entry to associate internal reference numbers with their corresponding VCI or VCI + MID. The host is also allowed to delete entries which are no longer active. A delete operation will remove the entry from the CAM. It also requests that the data structures associated with that internal reference at later stages in the pipeline be deallocated. In presently preferred embodiments, the CAM Lookup Controller 20-2 requires a maximum of eleven 50 ns cycles (550 ns) to perform the processing required for a cell.

The Linked List Manager 20-3 constructs and updates the linked list data structures responsible, for reassembly. These data structures are stored in a 32K by 16 static RAM Pointer Table. There are two reasons why linked lists are an excellent mechanism for performing reassembly: First, they allow dynamic allocation of memory. Extremely active connections can allocate more memory than their less active counterparts. Second, since each linked list node has a cell body sized portion of the Dual Port Reassembly Buffer 20-4 associated with it, all manipulations of the Dual Port Reassembly Buffer are controlled by the linked list data structures. Thus, the data stored for a connection or CS-PDU can appear contiguous without being physically contiguous in the Reassembly Buffer. By keeping a pointer to the beginning and end of each list, constant time insertion and removal can be assured.

The Linked List Manager 20-3 performs the following functions in connection with the linked lists: delete a list, append a node to the end of a list, and remove a node from the front of a list. Each of these operations also updates the list status information at the head of the affected list.

During configuration, the host is allowed to read and write into the RAM containing the data structures. This capability is necessary to initialize the data structures prior to the start of host interface operation. During operation, the host only needs to read the status blocks at the beginning of each linked list to remain aware of the network activity. The Linked List Manager 20-3 is responsible for all manipulation of the lists during operation. When the internal list reference number is passed to the Linked List Manager 20-3 from the CAM Lookup Controller 20-2, the Linked List Manager appends a new node at the end of the list specified. The pointer to the portion of the Dual Port Reassembly Buffer 20-8 location assigned to the node just appended to the list is passed to the Dual Port Reassembly Buffer Controller 20-4.

When the host reads data from the host interface, nodes are removed from the front of the affected list and the Reassembly Buffer pointers are passed to the Dual Port Reassembly Buffer Controller 20-4 so that the appropriate data can be moved from the host interface. In presently preferred embodiments, the Linked List Manager 20-3 requires a maximum of thirteen 50 ns cycles (650 ns) to perform an operation on a list.

The Dual Port Reassembly Buffer Controller 20-4 is the final stage of the ATM cell processing pipeline. It is responsible for moving data to and from the Dual Port Reassembly Buffer 20-8. This buffer comprises a single ported 128K by 32 RAM bank which is dual ported by the Dual Port Reassembly Buffer Controller. Dual port RAMs are commercially available but they are less dense and more expensive than the single port RAMs used in the preferred embodiment. The Dual Port Reassembly Buffer Controller is able to move a cell from the FIFO associated with the Cell Manager 20-1 into the Reassembly Buffer 20-8 in 2.4 μs (cell time is 2.7 μs) . A cell body can be extracted from the buffer for movement across the bus in 1.2 μs, the minimum time required to move the data across the bus.

Claims

We claim :

1. A reassembler for reassembling received data that has been segmented into a plurality of cells each of which comprises at least a virtual channel identifier (VCI) and a cell body, comprising:

(a) first means for separating each cell body from its corresponding VCI and determining respective linked list reference addresses for the VCIs;

(b) a reassembly buffer storing said cell bodies; and

(c) a linked list manager storing linked list data indicative of addresses at which said cell bodies are stored in said reassembly buffer.

2. A reassembler as recited in claim 1, wherein the reassembler is adapted for use in reassembling connectionless data.

3. A reassembler as recited in claim 2, wherein said connectionless data comprises data that has been segmented into a plurality of cells each of which comprises a VCI and datagram framing information.

4. A reassembler as recited in claim 1, wherein said linked list manager comprises a pointer table storing said linked list data.

5. A reassembler as recited in claim 1, wherein said reassembly buffer comprises:

(i) a reassembly memory for storing said cell bodies; and

(ii) a reassembly controller for writing/reading cell bodies to/from said reassembly memory.

6. A reassembler as recited in claim 5, wherein said reassembly memory comprises a dual port random access memory.

7. A reassembler as recited in claim 1, wherein said first means comprises:

(i) a cell manager for separating each cell body from its corresponding VCI and detecting whether said VCI has been corrupted;

(ii) a content addressable memory (CAM) storing said VCIs and providing pointers into said linked list data; and

(iii) a look-up controller for writing said VCIs to said CAM.

8. A reassembler as recited in claim 7, wherein the reassembler is adapted for use in reassembling connectionless data, said connectionless data comprising data that has been segmented into a plurality of cells each of which comprises a VCI and framing information; wherein said linked list manager comprises a pointer table storing said linked list data; wherein said reassembly buffer comprises a reassembly memory for storing said cell bodies and a reassembly controller for writing/reading cell bodies to/from said reassembly memory; and wherein said reassembly memory comprises a dual port random access memory.

9. A reassembler as recited in claim 1, wherein said first means, reassembly buffer, and linked list manager operate in parallel and form a cell processing pipeline.

10. A reassembler as recited in claim 8, wherein said first means, reassembly buffer, and linked list manager operate in parallel and form a cell processing pipeline.

11. A method for reassembling received data that has been segmented into a plurality of cells each of which comprises at least a virtual channel identifier (VCI) and a cell body, comprising the steps of: (a) separating each cell body from its corresponding VCI and determining respective linked list reference addresses for the VCIs;

(b) storing said cell bodies; and (c) storing linked list data indicative of addresses at which said cell bodies are stored.

12. A method as recited in claim 11, wherein the method is employed for use in reassembling connectionless data.

13. A method as recited in claim 12, wherein said connectionless data comprises data that has been segmented into a plurality of cells each of which comprises a VCI and datagram framing information.

14. A method as recited in claim 13, wherein said cells comprise at least one of the following group:

Class 4 ATM Adaptation Layer (AAL4) cells, and Class 5 ATM Adaptation Layer (AAL5) cells.

15. A method as recited in claim 13, wherein the step of storing linked list data indicative of addresses at which said cell bodies are stored comprises storing said linked list data in a pointer table.

16. A method as recited in claim 13, wherein said step of separating each cell body from its corresponding VCI and determining respective linked list reference addresses for the VCIs comprises:

(i) separating each cell body from its corresponding VCI and detecting whether said VCI has been corrupted; and

(ii) storing said VCIs in a content addressable memory (CAM) and providing pointers into said linked list data.

17. A method as recited in claim 13, wherein the method is employed for use in reassembling connectionless data comprising data that has been segmented into a plurality of cells each of which comprises a VCI and datagram framing information; wherein the step of storing linked list data indicative of addresses at which said cell bodies are stored comprises storing said linked list data in a pointer table; and wherein the step of separating each cell body from its corresponding VCI and determining respective linked list reference addresses for the VCIs comprises separating each cell body from its corresponding VCI and detecting whether said VCI has been corrupted, and storing said VCIs in a content addressable memory (CAM) and providing pointers into said linked list data.

18. A method as recited in claim 11, wherein steps (a) , (b) , and (c) are performed in parallel to provide a cell processing pipeline.

19. A method as recited in claim 17, wherein steps (a) , (b) , and (c) are performed in parallel to provide a cell processing pipeline.

20. A method, for use by a host interface between a network node and a host device, for receiving data that has been segmented into a plurality of cells each of which comprises at least a virtual channel identifier (VCI) and a cell body, comprising the steps of:

(a) storing each cell body in a first memory;

(b) generating and storing in a second memory a linked list comprising a plurality of pointers, wherein each pointer identifies where in said first memory a corresponding one of said cell bodies is stored; and

(c) storing in a third memory an identifier that indicates a location in said second memory at which said linked list is accessible.

21. A method as recited in claim 20, wherein said third memory is a content addressable memory (CAM) and each of said identifiers corresponds to a VCI, whereby said linked list is accessible by referring to its corresponding VCI.

22. A method as recited in claim 20, wherein said linked list is organized as a first item and a plurality of nodes, with each node identifying a storage location of a corresponding cell body, said first item identifying the last node in the linked list, the first node in the linked list, and the number of cells represented by the linked list.

23. A method as recited in claim 20, wherein steps (a) , (b) , and (c) are performed in parallel to provide a cell processing pipeline.