WO1994022173A1 - Solid state imaging device and process for production thereof - Google Patents
Solid state imaging device and process for production thereof Download PDFInfo
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- WO1994022173A1 WO1994022173A1 PCT/JP1994/000452 JP9400452W WO9422173A1 WO 1994022173 A1 WO1994022173 A1 WO 1994022173A1 JP 9400452 W JP9400452 W JP 9400452W WO 9422173 A1 WO9422173 A1 WO 9422173A1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/112—Devices sensitive to infrared, visible or ultraviolet radiation characterised by field-effect operation, e.g. junction field-effect phototransistor
- H01L31/113—Devices sensitive to infrared, visible or ultraviolet radiation characterised by field-effect operation, e.g. junction field-effect phototransistor being of the conductor-insulator-semiconductor type, e.g. metal-insulator-semiconductor field-effect transistor
- H01L31/1133—Devices sensitive to infrared, visible or ultraviolet radiation characterised by field-effect operation, e.g. junction field-effect phototransistor being of the conductor-insulator-semiconductor type, e.g. metal-insulator-semiconductor field-effect transistor the device being a conductor-insulator-semiconductor diode or a CCD device
Definitions
- the present invention relates to a solid-state imaging device and a method of manufacturing the solid-state imaging device.
- the present invention relates to a solid-state imaging device on a common substrate having a high light response speed and in the same process.
- Switching element for operation ⁇ A transistor that constitutes a shift register can be configured and a solid that can perform surface operation
- the present invention relates to an imaging device and a manufacturing method thereof.
- the non-contact type projects a manuscript through a reduced-lens system and projects it on a CCD using a single-crystal PN junction. It uses a silicon nozzle that is currently established.
- the LSI process can be used for IJ IJ, so it is characterized by high productivity and low cost.
- the close contact type and the complete contact type are more advantageous than the non-contact type in reducing the size and weight.
- the close-contact type is an expensive part such as a self-cleaning lens.
- ⁇ is used.
- a fully adherent type that does not require a cell lens has also been commercialized.
- the complete contact type uses thin glass, etc., but is costly IJI.
- the thin film type can be manufactured by a thin film process on an insulating substrate such as glass or ceramic, it is possible to increase the area and read a manuscript of the same length as the original width. This has the advantage that the chip can be easily obtained.
- a type of photoconductor type and a photodiode type are known.
- a type of photoconductor is made of a material whose resistance decreases when exposed to light, for example, a material such as amorphous silicon. In this method, a change in resistance according to light irradiation is read as a change in current value.
- the photoconductor type has a high noise-reducing characteristic because it can carry a large current.However, it has poor optical response. This is disadvantageous for demands for faster facsimile.
- the photo diode type reverses the carrier generated in the depletion layer of the PIN junction diode when light is applied to the diode. By sweeping the voltage imprinted in the noise direction, a current proportional to the light intensity is obtained as a signal.
- This photo diode type has the characteristic that the response to light is very fast. However, since the current flowing through the photodiode is small, there is a problem in that it is susceptible to noise.
- the photo diode type has a different manufacturing process for manufacturing the read drive circuit from the process for manufacturing the photo diode. A very large number of complex manufacturing processes are required, and the yield generally tends to be low. In addition, if the read drive circuit is externally provided as an IC, it is very difficult to reduce the cost because a large number of read chips are required.
- Japanese Patent Application Laid-Open No. 2-210877 discloses a solid-state imaging device using a baud rate transistor technique. Is difficult to make a PN junction Therefore, practical application is difficult.
- the conventional M0S structure which uses an amorphous silicon, has a low optical response speed on the order of several hundred thousand microseconds. It is unsuitable as an image sensor for a simiri and a switching element for operating the image sensor.
- the manufacturing process is complicated because the MOS transistor for the photoresist must be created in a separate process from the image sensor. However, the manufacturing cost is high and there are drawbacks.
- An object of the present invention is to provide a solid-state imaging device having a thin film MOS structure capable of performing a planar operation and a method of manufacturing the same.
- a feature of the present invention for achieving the above-mentioned object is that a substrate having an insulating surface and a non-single-crystal silicon layer to be placed thereon have a small number of features.
- An active layer having a common source region and a drain region, and an insulating layer may be interposed on a light receiving region between the source region and the drain region of the active layer.
- a gate electrode layer, and a source electrode layer and a drain electrode layer respectively provided above the source region and the drain region.
- the active layer is formed of a non-single-crystal silicon layer or a polycrystalline silicon layer.
- the non-single-crystal silicon layer is obtained by annealing the amorphous (amorphous) silicon layer, and the annealing method is laser. ⁇ two Lumpur or Ru Oh at 6 0 0 e C or more ⁇ knee Rugaka ability '.
- the imaging element and the MOS transistor are formed by a common non-single-crystal silicon film. You can configure both of the registers.
- One of the features of the present invention is that the imaging device is biased in a state where the source and the drain are electrically connected.
- Conventional photosensors have been used in a non-conductive state.
- FIG. 1 is a cross-sectional configuration diagram of a non-single-crystal TFT according to an embodiment of the present invention.
- FIG. 2 is a part of a diagram illustrating a manufacturing process of a non-single-crystal TFT according to one embodiment of the present invention.
- FIG. 3 is an explanatory view of a manufacturing process of the non-single-crystal TFT according to one embodiment of the present invention, which is an explanatory view of the next step of FIG.
- FIG. 4 is a characteristic diagram of the non-single-crystal TFT according to one embodiment of the present invention.
- FIG. 5 is a characteristic comparison diagram between the non-single-crystal TFT and the other TFT according to one embodiment of the present invention.
- FIG. 6 is a characteristic diagram of the non-single-crystal TFT according to one embodiment of the present invention.
- FIG. 7 is a diagram illustrating the principle of operation of the non-single-crystal TFT according to the present invention.
- FIG. 8 is a circuit diagram using a non-single-crystal TFT according to one embodiment of the present invention.
- FIG. 9 shows a manufacturing process of the example.
- FIG. 10 shows the manufacturing process of the example.
- FIG. 11 shows a manufacturing process of the example.
- FIG. 12 shows the fabrication process of the example.
- FIG. 1 One embodiment of the present invention will be described with reference to FIGS. 1 to 7.
- FIG. 1 One embodiment of the present invention will be described with reference to FIGS. 1 to 7.
- FIG. 1 is a sectional view showing the structure of a TFT according to an embodiment of the present invention.
- FIGS. 2 and 3 are views showing the fabrication of the TFT shown in FIG. Process description diagrams and Figs. 4 to 6 show the TF of one embodiment of the present invention.
- FIG. 7 is an explanatory view of the principle of operation of a non-single-crystal TFT which constitutes the solid-state imaging device of the present invention.
- 1 is glass la scan the substrate
- 3 is the active layer
- 4 'Gate insulating film 5' is gate electrode
- Reference numeral 6 'de notes a drain region
- 7 denotes an insulating film
- 8 denotes an electrode
- 10 denotes a TFT.
- the film forming conditions at this time are as follows.
- the amorphous silicon film 3 formed according to the above (2) is subjected to an annealing step.
- This annealing step is performed to crystallize the a-Si film 3 formed by the LPCVD method described above.
- the excimer laser is used.
- An anneal eg, KrF
- KrF is applied to obtain a crystallized non-single-crystal silicon film.
- Laser annealing melts the film at high temperature, so the interface of the crystal grains is bonded, and the level of the grain boundary is small.
- the conditions of the annealing process are as follows.
- a non-single-crystal Si film that has been subjected to the above annealing step is subjected to a notching process to form an iron 3 ( (See Fig. 2 (C)).
- TEOS is placed on the substrate 1 containing this land 3 '.
- a Si0 2 film 4 to be a gate insulating film is formed to a thickness of 150 A (see FIG. 2 (D)). ) ,.
- the conditions for forming the gate insulating film 4 are as follows.
- a gate-doped, gate-doped a-Si (amorphous silicon) layer 5 is formed by plasma CV.
- a film is formed to a thickness of 100 OA by the D method (see Fig. 2 (E)).
- the conditions for forming the a-Si layer 5 are as follows.
- the gate electrode layer and the gate insulating film are patterned by the etching, and the gate insulating film 4 'and the gate electrode are formed.
- a crystallized non-single-crystal Si layer; a source is formed by masking a gate insulating film 4 ′ and a gate electrode 5 ′ on an island 3 ′ made of ⁇ .
- the ring (P) is doped by the ion-doving method in the region 6 and the drain region 6 '(see Fig. 3 (A)).
- hydrogenation is performed by heating in a hydrogen atmosphere to reduce defect levels in the semiconductor layer.
- the conditions for hydrogenation are as follows.
- Hydrogenation is effective in lowering the trap density at the interface between the active layer 3 ′ and the gate insulating layer 4 and improving the film quality.
- Ri we realize Ri by the unique method ⁇ beauty hydrotreating SX lO / cm 2 or less DOO wrapping density in the active layer ⁇ beauty gate insulation ⁇ in the present invention.
- An SiO 2 film 7 serving as an interlayer insulating film is formed with a thickness of 400 A on the entire substrate by the TE OS method.
- Si0 deposition conditions of 2 film 7 is Ru Oh the Ri following through.
- an aluminum film for an electrode is formed and patterned, and as shown in FIG. 1, an aluminum electrode 8 is formed to form a TFT. Complete .
- boron (B) may be used instead of phosphorus (P).
- the input light irradiates the light-receiving region between the drain of the active layer 3 'and the source through the transparent substrate as shown in A of FIG. .
- a transparent IT0 indium tin oxide
- aluminum instead of aluminum to make the input. It is also possible to introduce the light into the active layer via the electrode 8 as shown in FIG. 1B.
- FIG. 4 shows the drain current ( ID ) -gate voltage (VG) characteristics of the TFT formed and manufactured in this manner.
- the solid line graph A shows the ID-Ve characteristic without light irradiation
- the dotted line graph B shows the ID-V ⁇ characteristic without light irradiation
- Graph C in the figure indicates the photocurrent (difference between ⁇ and ⁇ ).
- the TF ⁇ shows sensitivity to external light, as is clearer than ⁇ .
- the graph shows the value when there is no light irradiation
- the graph B shows the value without light irradiation. Therefore, the difference C is the light of the TFT.
- the gate Bok voltage V G is about 7.5 V or more, de Tray down current ID differences rather name on characteristics of grayed La full a and grayed La full B is ing constant.
- Fig. 7 shows an energy level diagram near the surface of an n-type non-single-crystal silicon having a MOS structure.
- Fig. 7 (A) shows the case where no light is irradiated from the outside.
- FIG. 7 (B) shows each energy level when light is irradiated from the outside.
- reference numeral 71 denotes a gate oxide film
- 72 denotes an n-type non-single-crystal silicon.
- FIG. 7 (A) when the light is not irradiated, there is a film level E f force s near the conduction band.
- FIG. 7 (B) the electrons move from the valence band to the conduction band when irradiated with external force, and as a result, the The mi level E f shifts toward the center, the trap density existing at the interface with the gate oxide film 71 increases, and strongly indicates the function of the receptor. Swell.
- the shift of the Fermi level E f causes the flat potential and the * nd potential of the MOS structure to be shifted in the negative direction.
- the threshold voltage (V tn ) of the drain current (ID) vs. gate voltage (VG) characteristic should be shifted to the negative side. become .
- the TFT Thin Film Transistor
- V th the shift of V th is expressed by the following equation.
- N t denotes Bok wrapping density of MOS structure
- capacitance of C ox is gate oxide film
- K is the coefficient .
- Nt is required to be sufficiently small
- a short pulse width laser such as an excimer laser / anneal is used.
- anneal a non-single-crystal silicon with a sufficiently small Nt has been realized.
- Nt is required to be at a level of 5 ⁇ 10 11 / cm 2 or less.
- the photosensitivity characteristics of the TFT having the M0S structure as in the present invention can be explained as follows.
- the light sensitivity of the TFT of the present invention is considered to be due to the photo-excited carrier generated by the light absorption in the active layer 3 of the TFT 10 shown in FIG.
- the photoexcited carrier generated by the light absorption is collected at the interface between the film 4 ′ and the active layer 3 ′, resulting in the displacement of the threshold voltage V th .
- ⁇ V th is generated.
- ⁇ V th can be expressed by the following equation.
- Nt 8 X 10 1 ′ cm 2 which means that if amorphous silicon is crystallized by an excimer laser anneal as in this example, if N t is that Ki 3.9 X 10 '' / cm 2 and a small value out and give Ru this.
- the value of Nt is further improved by hydrogenation.
- Nt depends on the grain boundary of the polycrystalline silicon.
- BS Levinson eta 1 J. Appl. Phys. Vol 52, pp. 1193-1202 (1982) BS
- Fig. 5 shows the solid phase growth.
- Non-simple after thermal crystallization Phase of activation energy with respect to gate voltage of crystalline Si TFT and non-single-crystal TFT crystallized by excimer laser annealing of this embodiment Indicates a function.
- graph A shows the change in the former activation energy
- graph B shows the change in the latter activation energy according to the present invention.
- the non-single-crystal Si TFT crystallized by the excimer laser annealing of this embodiment is a gate.
- the voltage (VG) is positive, there is a negative activation energy, which indicates that the effect of the grain boundary does not appear in almost this region.
- the TFT manufactured in this embodiment changes the total amount Q 0 of the photo-excited carrier of the equation (2) according to the intensity of the incident light, and as a result, ⁇ V th For example, moving to the negative side.
- this is an amplification effect by light, and has the function of a phototransistor.
- the horizontal axis shows trap density, and the vertical axis shows light sensitivity.
- FIG. 6 by Ri door wrapping density S x ltT '/ cm 2 or less of the value and of the Son and of the ing Shi Nozomi or les This is clearly the power.
- the present invention is not limited to this, and the trap density after annealing may be 5 ⁇ 10 1 ′ cm 2 or less. You should.
- a crystallized non-single-crystal silicon TFT having a trap density of 5 ⁇ 10 11 / cm 2 or less has a photoelectric conversion function. Therefore, as shown in Fig. 8, for example, as shown in Fig. 8, a sensor part for sensing light and a switch part have one circuit element, that is, light sensitivity. The use of a switch device has made it possible to simplify the imaging device.
- reference numeral 10 denotes a non-single-crystal silicon TFT having a photoelectric conversion function
- 11 denotes a power supply
- a power supply denotes an electric output
- a video line 13 indicates a gate line for applying a bias potential.
- FIG. 9 and 10 show a drive circuit portion shown two on the right side and a solid-state image pickup device portion shown one on the left side.
- the solid-state imaging device has a function of outputting incident light as an electric signal and outputs the same, and the driving circuit has a function of driving the solid-state imaging device.
- a silicon oxide is formed as an underlying insulating layer.
- a film 42 of a thickness of 300 nm is formed.
- a thermal oxidation method is used.
- the substrate may contain impurities, but in such a case, the silicon oxide film can be formed by LPCVD. Okay.
- This silicon oxide film 42 corresponds to the insulating layer 2 shown in FIG. 1, and is formed from the active silicon layer formed thereon. It functions to prevent the litter from flowing to the board side.
- an amorphous silicon film 43 is formed thereon to a thickness of 200 nm.
- the film is formed by a plasma CVD method, and the silicon film 43 is formed as an amorphous silicon film, and the film forming conditions at this time are shown below.
- a heat treatment is performed at a high temperature of 600 ° C. for 24 hours, whereby a silicon film 4 is formed. 3 is crystallized.
- This silicon film 43 constitutes a source / drain region and a silicon active layer. If the thickness of the silicon film 43 is too small, silicon diffuses into the aluminum at a contact portion with the aluminum wiring described later. And poor contact and disconnection are likely to occur. In particular, when the film thickness is set to less than 30 nm, the production yield and reliability are greatly reduced.
- the thickness of the silicon film 43 is more than 1 ⁇ m, it is difficult to control the stress in the film. This causes problems such as variations in the electrical characteristics of the device and a reduction in reliability. Furthermore, a thick film increases the film forming time, which leads to a decrease in productivity.
- the thickness of the silicon film 43 is appropriate to set the thickness of the silicon film 43 to 30 nm or more and 1 m or less.
- the crystalline silicon film 43 obtained in this manner is turned into an island shape, and the silicon film is turned into an island shape. Further, the silicon film is formed by LPCVD. The film 44 is formed to a thickness of 100 nra. This silicon oxide film 44 is removed except for the solid-state imaging device portion on the left side of the drawing. As shown in FIG. 9 (B), the remaining silicon oxide film 44 functions as a gate insulating film of the solid-state imaging device. Then, a silicon oxide film 45 constituting a gate insulating film of the read drive circuit is formed by a thermal oxidation method. At this time, the thickness of the silicon dioxide film is 100 nm. As a result of this step, the gate insulating film 44 ′ of the solid-state imaging element portion on the left side of the drawing is formed by the previously formed silicon oxide film 44 and the film formed in this step. And a thermally oxidized silicon film.
- the gate insulating film is formed as described above so that the solid-state imaging device portion and the reading drive circuit portion can obtain optimal electric characteristics respectively. It is.
- the upper limit of the thickness is about 300 nm. This is because a sufficient amplification effect cannot be obtained when the thickness of the gate insulating film is 300 nm or more.
- the lower limit of the thickness is 20 nm. This is because the driving voltage of the solid-state imaging device (in this case, the photoelectric conversion device on the left side of the drawing) is 5 to 20 V, and there are variations in film quality and long-term reliability. Considering that, when a silicon oxide film is used as a gate insulating film, its thickness force must be s 20 nm or more. .
- the gate insulating films in the solid-state image element portion and the reading drive circuit portion were made different according to their characteristics.
- the gate insulating film of the drive circuit portion is entirely provided, the gate insulating film of the solid-state imaging device portion is partially provided, and the thermally oxidized silicon is used. It is composed of a membrane. The use of the thermally oxidized silicon film is to obtain electrical characteristics and long-term reliability.
- the electrical characteristics of the MIS transistor differ greatly between when the thermal oxidation method is used and when it is not. And have been found. In other words, it was found that the threshold voltage was lower and the 0N ⁇ 0FF ratio was higher when the thermally oxidized silicon film was used. It has also been found that when a thermally oxidized silicon film is used as a gate insulating film, its electrical characteristics can be maintained for a long period of time.
- the N + polycrystalline silicon 46 serving as the gate electrode is formed to a thickness of 300 nm by LPCVD.
- a film is formed on the substrate.
- the rinsing is 1 ⁇ 10 2 . Doves about 2 atoms / era or more. (Fig. 9 (D))
- the polycrystalline silicon film 46 is patterned by the draining method, and the silicon oxide that forms the gate insulating film is continuously formed.
- the upper part of the membranes 44 'and 45 is also removed by etching.
- the remaining polycrystalline silicon films 47 to 49 which are the polycrystalline silicon films, have been formed as gate electrodes.
- ion injection is performed according to the ion doping method.
- phosphorus which is an impurity imparting N-type conductivity, is implanted at an acceleration voltage of 70 kV and at a dose of 1 ⁇ 10 15 atoms / cra 2 . (Fig. 9 (E))
- the portion that does not need to be doped with an impurity for imparting a P-type is covered with a register 50, and boron is accelerated at a speed of 40 kV by 5 ⁇ 10 Inject at a dose of 15 atoras / cm 2 .
- FIG. 9 (F) shows an example in which only two elements on the right are implanted with polon.
- a silicon oxide film to be an interlayer insulating film 51 is formed to a thickness of 800 nm by a normal pressure CVD method. (Fig. 10 (A))
- a PSG film may be used as the inter-layer insulating film. Drill a contact hole. (Fig. 10 (B))
- an aluminum film 52 is formed by a sputtering method, and the aluminum wiring is formed by performing patterning. (Fig. 10 (C), (D))
- the element part and the read drive circuit part are completed at the same time.
- the solid-state imaging device thus obtained has a gate electrode 47, source drain electrodes 53 and 55, and an active layer region (channel forming region) 54. Yes.
- the two elements in the read drive circuit have the same configuration. That is, one element has a gate electrode 48, a source / drain area 56/58, and an active layer area 57, and the other element has a gate electrode.
- a contact electrode 49, a source / drain region 59-61, and an active layer region 60 are provided.
- a solid-state imaging device is formed on a single-crystal silicon substrate, and the single-crystal silicon of the substrate is used as it is to read and drive on the same substrate.
- This section shows how to construct a circuit.
- Fig. 11 and Fig. 12 show the fabrication process of this example.
- two MOS type transistors are formed by the LSI process conventionally used.
- One of the two MOS type transistors is of the N-channel type and the other is of the P-channel type.
- These MOS transistors are for driving a solid-state imaging device, and may have a CMOS structure if necessary.
- a solid-state imaging device using a thin-film semiconductor is formed on the left side of the figure.
- an N-type single crystal silicon substrate is used as the substrate 501.
- a silicon oxide film 502 is formed on an N-type single-crystal silicon substrate 501 by a thermal oxidation method or the like for the purpose of buffering stress.
- the channel stopper 50 Doping for 3 is performed, and a silicon nitride film 504 for selective oxidation is selectively provided.
- the register covers the area where the N-channel M0S transistor is to be formed, and is indicated by reference numeral 506 according to the ion implantation method.
- an amorphous silicon is formed by a plasma CVD method, and a heat treatment is performed in the same manner as in the above-described embodiment.
- a crystalline silicon film having a crystalline property is formed by a turning process.
- an island-like crystalline silicon layer 507 is formed. You The crystalline silicon layer formed in an island shape is used as an active layer of a solid-state imaging device. (Fig. 11 (C)).
- the heat treatment for forming the crystalline silicon layer 507 can be performed at a high temperature of 800 or more, and extremely high Good properties can be obtained. This is because, since the substrate is made of single-crystal silicon, shrinkage or deformation of the substrate during heat treatment does not pose a problem.
- a thermally oxidized silicon film is formed as a new gate insulating film 500, and ⁇ + poly-si is further formed as a gate electrode.
- ⁇ + poly-si is further formed as a gate electrode.
- reference numeral 508 denotes a gate electrode of a photoelectric conversion element constituting the solid-state imaging device
- 509 and 51 0 is the gate electrode of the M0S type transistor in the drive circuit.
- a thickness of 800 nm is formed as an inter-layer insulating film 512 by an atmospheric pressure method using a pressure of 0 nm, and a contact hole for wiring is opened. (Fig. 12 (C))
- the solid-state imaging device 513 is formed on an insulating film 505, and has a N-type source node. It has a drain area 515/517 and a channel forming area (active layer) 516.
- the drive circuit for driving the solid-state imaging device is an N-channel having an N-type source / drain region 518Z5200 and a channel formation region 519.
- one solid-state imaging device and two MOS transistors for driving the solid-state imaging device are formed on the same silicon substrate.
- the number of solid-state imaging devices and M0S-type transistors may be selected as needed.
- the active layer can be obtained by laser annealing or high-temperature annealing of the amorphous silicon layer.
- the thickness of the active layer is 30 nm to 100 nm, and the thickness of the gate insulating film of the photosensor is 20 ⁇ ! 3300 nm. Since the manufacturing process of the photosensor according to the present invention is the same as the manufacturing process of the MOS transistor, the process required for the operation of the photosensor is performed. It is possible to manufacture a transistor for the evening by using a thin film technology at the same time as the photo sensor. it can .
- the photosensor according to the present invention has an optical response time of the order of several hundred microseconds, is fast, and has a planar motion by arranging the elements in a plane. It can be used for facsimile image readers as well as various image readers that require high-speed reading. .
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/343,492 US5574293A (en) | 1993-03-23 | 1994-03-22 | Solid state imaging device using disilane |
EP94910053A EP0642179B1 (en) | 1993-03-23 | 1994-03-22 | Solid state imaging device and process for production thereof |
DE69416363T DE69416363T2 (de) | 1993-03-23 | 1994-03-22 | Abbildendes festkörperbauteil und herstellungsverfahren dafür |
US08/477,104 US5591988A (en) | 1993-03-23 | 1995-06-07 | Solid state imaging device with low trap density |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP06378993A JP3267375B2 (ja) | 1993-03-23 | 1993-03-23 | 固体撮像装置 |
JP5/63789 | 1993-03-23 | ||
JP5314135A JPH07142694A (ja) | 1993-11-19 | 1993-11-19 | 半導体装置およびその動作方法 |
JP5/314135 | 1993-11-19 |
Publications (1)
Publication Number | Publication Date |
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WO1994022173A1 true WO1994022173A1 (en) | 1994-09-29 |
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ID=26404914
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP1994/000452 WO1994022173A1 (en) | 1993-03-23 | 1994-03-22 | Solid state imaging device and process for production thereof |
Country Status (4)
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---|---|
US (2) | US5574293A (ja) |
EP (1) | EP0642179B1 (ja) |
DE (1) | DE69416363T2 (ja) |
WO (1) | WO1994022173A1 (ja) |
Cited By (1)
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DE19929733B4 (de) * | 1998-06-29 | 2013-07-25 | Intellectual Ventures Ll Llc, ( N. D. Ges. D. Staates Delaware) | Bildsensor und Einheitspixel eines CMOS-Bildsensors mit selbstjustierender Silizidschicht |
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KR100643038B1 (ko) * | 2000-08-31 | 2006-11-10 | 엘지.필립스 엘시디 주식회사 | 박막트랜지스터형 광센서 어레이 기판 |
JP2005005509A (ja) * | 2003-06-12 | 2005-01-06 | Canon Inc | 薄膜トランジスタ及びその製造方法 |
TWI260093B (en) * | 2005-01-25 | 2006-08-11 | Au Optronics Corp | Thin film transistor with microlens structure, forming method thereof and TFT display panel comprising thereof |
EP1727120B1 (en) | 2005-05-23 | 2008-07-09 | Semiconductor Energy Laboratory Co., Ltd. | Photoelectric conversion device and manufacturing method thereof |
KR101299604B1 (ko) * | 2005-10-18 | 2013-08-26 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 및 그 제조 방법 |
US8514165B2 (en) * | 2006-12-28 | 2013-08-20 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
US7972943B2 (en) * | 2007-03-02 | 2011-07-05 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of semiconductor device |
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Also Published As
Publication number | Publication date |
---|---|
EP0642179A4 (en) | 1995-08-30 |
EP0642179B1 (en) | 1999-02-03 |
US5574293A (en) | 1996-11-12 |
DE69416363D1 (de) | 1999-03-18 |
US5591988A (en) | 1997-01-07 |
DE69416363T2 (de) | 1999-09-23 |
EP0642179A1 (en) | 1995-03-08 |
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