WO1994017553A1 - Three dimensional integrated circuit and method of fabricating same - Google Patents
Three dimensional integrated circuit and method of fabricating same Download PDFInfo
- Publication number
- WO1994017553A1 WO1994017553A1 PCT/US1994/000363 US9400363W WO9417553A1 WO 1994017553 A1 WO1994017553 A1 WO 1994017553A1 US 9400363 W US9400363 W US 9400363W WO 9417553 A1 WO9417553 A1 WO 9417553A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- substrate
- interconnection means
- forming
- circuit assembly
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
- H01L2225/06586—Housing with external bump or bump-like connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06596—Structural arrangements for testing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/928—Front and rear surface processing
Definitions
- This invention relates generally to integrated circuit manufacturing technology and, in particular, to-a method for fabricating a multi-layered, three-dimensional integrated circuit.
- a supporting substrate is employed to support a Si layer when a Si crystal is removed by a preferential polishing method.
- the supporting substrate is later removed.
- a perceived disadvantage to this approach is that the bulk silicon crystal is required to mechanically thinned down, using a LOCOS-buried SiO as a polish stop. This process may be difficult to control in order not to remove the LOCOS-buried Si0 2 , and cannot be readily applied to technologies other than LOCOS-isolated CMOS. This process also appears to require that the LOCOS-buried Si0 2 extend further into the Si than the active devices in the Si. This may present a serious limitation for many applications.
- SOI Silicon-on- Insulator
- a further object of this invention is to provide a fabrication technology that results in a 3d circuit that supports metal oxide semiconductor (MOS) , bipolar, or combination technologies; and that achieves a high circuit density through the use of thin silicon films with small vertical feedthroughs.
- MOS metal oxide semiconductor
- the method includes the steps of providing a first and a second Silicon-on- Insulator (SOI) wafer, wherein each SOI wafer includes a thin silicon layer separated from a bulk silicon substrate by a thin layer of dielectric material, typically Si02.
- a next step processes the thin silicon layers to form at least one electrical feedthrough in each of the thin silicon layers and to also form desired active and passive devices in each of the thin silicon layers.
- a next step forms interconnects that overlie the thin silicon layer and that are electrically coupled to the at least one feedthrough.
- One of the wafers is then attached to a temporary substrate such that the interconnects are interposed between the thin silicon layer and the temporary substrate.
- the bulk silicon substrate of the wafer having the temporary substrate is then removed by a step of etching the bulk silicon substrate so as to expose the dielectric layer.
- Further interconnects are then formed through the exposed dielectric layer for electrically contacting the at least one feedthrough. This results in the formation of a first circuit assembly that includes the processed silicon layer, the interconnects formed over a first major surface (topside surface) of the processed silicon layer, and the further interconnects that are formed over a second major surface (bottomside surface) of the processed silicon layer.
- a next step then couples the further interconnects of the circuit assembly to the interconnects of a supporting substrate, such as a second SOI wafer having a bulk substrate, a dielectric layer overlying a surface of the substrate, and a layer of processed silicon overlying the dielectric layer.
- a supporting substrate such as a second SOI wafer having a bulk substrate, a dielectric layer overlying a surface of the substrate, and a layer of processed silicon overlying the dielectric layer.
- the temporary substrate is then removed. Additional circuit assemblies may then be stacked and interconnected to form a 3d integrated circuit of a desired complexity.
- the completed 3d wafer stack may be used in wafer form, or it may be sawed into 3d dice after stacking. Alternatively, individual dice may be cut from a circuit assembly, processed as described above, and stacked to form a 3d structure.
- Figs. 1 through 7 are cross-sectional views that illustrate steps of a fabrication method of the invention
- Fig. 8 illustrates an embodiment of a 3d integrated circuit assembly that is connected to a larger diameter carrier wafer
- Figs. 9 and 10 are cross-sectional views that illustrate an embodiment of the invention wherein a thin Si film has active device structures that extend through a total thickness of the film.
- a first fabrication step provides an SOI wafer 1 that includes of a silicon film 12 separated from a bulk silicon wafer 10 by an SiO layer 11.
- the presence of the Si02 layer 11 facilitates the performance 5 of the etching step described below.
- the thickness of the silicon film 12 is typically within a range of approximately 0.2 micrometers to approximately 10 micrometers.
- the thickness of the Si0 2 layer 11 is not critical, and is typically in the range of approximately 0.1 micrometers to approximately 1.5 micrometers.
- the thickness of the substrate 10 is approximately 600 micrometers.
- the overall diameter of the wafer 1 is typically in the range of approximately 100 mm to approximately 200 mm.
- a presently preferred method for forming the Si film 12 is by bonding two silicon wafers together with a fused oxide layer, and then thinning one of the wafers to form the thin film Si layer 12.
- This technique allows optimum control in the thickness and composition of the buried insulator 11, and provides a high quality Si film. It is noted that both wafers need not be crystalline Si.
- one of the wafers may be polycrystalline Si and the other crystalline Si, with the crystalline Si being thinned to provide the Si film 12 within which active devices are fabricated.
- SIMOX Separation by Implanted Oxygen
- ZMR Zero Melt and Recrystallization
- SOI wafer 1 can also be purchased commercially.
- the Si film 12 can be characterized as being either a "thick" film, having a thickness greater than approximately one micrometer, or a "thin” film having a thickness less than approximately one micrometer.
- trenches are formed to provide vertical feedthroughs.
- the vertical feedthroughs can be readily formed within gaps made between transistor mesas.
- Figs. 2-6 illustrate the thick film case
- Figs. 9 and 10 illustrate the thin film case.
- a conventional LOCOS process has been employed t form regions of isoplanar Si0 2 13 on the surface of the s layer 12.
- Transistors can be formed within active areas that is, areas not covered by the isoplanar oxide 13.
- Fig. 3 illustrates the SOI wafer 1 after trenches 14 hav been etched by an anisotrophic plasma etch process Trenches are typically formed both in the active region (trench 14a) and in the isoplanar field regions (trenc 14b) so as to provide optimum vertical interconnec placement flexibility.
- th feedthroughs 16 are formed by etching the trenches 14a an
- the trench walls, and the upper surface of th silicon film 12, are oxidized using a conventional therma oxidation process to form a dielectric SiO layer 15 havin a thickness of approximately 0.1 micron.
- the remainin opening within each trench is then filled with a electrically conductive material 16a.
- Heavily dope pol crystalline silicon (polysilicon) is a preferre electrically conductive material, although othe electrically conductive materials, such as tungsten, ma also be employed.
- Phosphorus or Arsenic are the preferre dopants at concentrations sufficient to provide ' th required conductivity, which may vary depending upon th application.
- the feedthroughs result whe the Si film 12 is etched to form islands where th transistors will be made. The space-between these island is then available for use by feedthroughs.
- the diffusions e.g. source and drain diffusions for MO transistors
- each feedthrough 16 includes an electrically conductive member 16a surrounded by an electrically insulating Si02 region (15) .
- CMOS complementary metal-oxide-semiconductor
- CMOS complementary metal-oxide-semiconductor
- N-type and p-type regions are formed where desired within the silicon film 12. These regions are delineated through a photolithographic process and are formed through a diffusion or an ion implantation step.
- the sacrificial Si0 2 layer 15 is then removed and a further Si0 2 layer 17 is formed to serve as the gate oxide, the Si0 2 layer 17 being formed by oxidizing the silicon film 12.
- One or more polysilicon gate electrodes 18 are also deposited, as required, upon the Si02 layer 17.
- P+ and n+ regions 19a and 19b, respectively, are then photolithographically defined and diffused or implanted to serve as the source and drain regions of p and n-channel transistors, respectively.
- a layer 20 of Si0 2 is then deposited over the polysilicon gate electrodes 18. Openings are defined and etched within the Si0 2 layer 20, and metalization 21 is deposited so as to contact the conductive feedthroughs 16, the polysilicon electrodes 18, and the p+ and n+ regions 19a and 19b within the silicon film 12. As can be seen, a number of active devices (FETs) are thus formed, as may also be polysilicon resistors and other conventional devices. Additional layers of metal interconnects may also be added (as described below) , followed by an insulating overglass layer 22 that is deposited in a conventional manner. Finally, openings are defined and etched into the overglass layer 22, and "topside" indium bumps 23 are formed to contact the metalization 21 within the openings.
- FETs active devices
- the indium bumps 23 are located where desired for eventual interconnection to another wafer that is processed as thus far described, and are not required to be located directly over the vertical feedthroughs 16. That is, routing metalization can be applied before the deposition of the overglass layer 22 in order to locate the indium bumps 23 at desired locations.
- Other suitable materials for the second substrate 26 include quartz and crystalline
- a consideration in the choice of material for the second substrate 26 is the coefficient of thermal expansion of the material, if the additional processing steps described below are performed at elevated temperatures. That is, the selected material for the second substrate 26 should have a coefficient of thermal expansion that is similar to that of Si to avoid undue deformation of the Si film 12 when the assembly is heated.
- the temporary attachment of the substrate 26 is made with a bonding layer 24 comprised of a wax or a similar material which can be readily removed later.
- the second substrate 26 provides mechanical support for the silicon layer 12 during the ensuing steps of the method, and has a suitable thickness for providing the required mechanical support.
- the first silicon substrate 10 is removed. This is accomplished, in accordance with an aspect of this invention, through the use of an etching process, or a lapping process, to remove a portion of the substrate 10, followed by an etching process.
- the etchant is chosen so that it stops at the Si0 2 layer 11 which separates the silicon substrate 10 from the thin silicon film 12 containing the active and passive circuitry.
- Suitable etching processes include the use of a hot KOH solution (60'C to 80'C) or a plasma etch that is highly selective for Si. As a result, a well controlled and complete removal of the silicon substrate 10 is achieved.
- a protective layer such as a thin layer of epoxy, can be provided around the periphery of the wafer to protect the Si layer 12 during the etching process.
- the temporary substrate 26 may be provided with a larger diameter than the wafer 1 to facilitate providing the protective layer at the periphery of the wafer 1. For example, if the wafer 1 has a diameter of 100 mm, a suitable diameter for the temporary substrate 26 is 125 mm.
- bonding pads 28 typically comprised of aluminum, an overglass layer 29, and "bottomside" indium bumps 30.
- This further processing results in the formation of an intermediate Structure or circuit assembly having active and passive electrical components located within the silicon layer 12, and topside and bottomside interconnects for coupling to other Structures.
- one of the bottomside indium bumps 30 will be associated with one of the vertical feedthroughs 16.
- a bottomside indium bump 30 need not be located so as to directly overlie a feedthrough. That is, bottomside metalization can be applied before the application of the overglass layer 29 so as to provide signal routing from the contacts 28 to any desired location on the bottomside surface, thereby enabling the indium bumps 30 to be located at the periphery of the wafer or at any desired location.
- One such indium bump is shown generally as 30a.
- the bump 30a is connected to its respective feedthrough 28 through an intervening strip of signal routing metalization 31.
- Figs. 9 and 10 are cross-sectional views that correspond to Figs.
- the Si layer has a thickness of less than one micrometer, and preferably less than approximately 0.5 micrometers.
- the reference numerals that correspond to the reference numerals in Figs. 5 and 6 are designated with primes.
- the Si layer 12' has been selectively removed down to the SiO_ layer 11'.
- the remaining Si material forms islands or mesas within which active and passive devices are formed by selective doping. Due to the thinness of the Si layer 12• , the doped regions extend completely through the Si layer 12*.
- a feedthrough 16' is partially formed by depositing a doped polysilicon pad 18' onto the dielectric layer 11' within an area between mesas, and contacting the doped polysilicon pad 18' with metalization 21'.
- Fig. 10 the bulk substrate 10' has been removed and the temporary substrate 26' attached. Furthermore, apertures have been opened in the dielectric layer 11' and bottomside metalization 28' applied, after which the bottomside indium bumps 30' are formed.
- the transistor device generally designated as "A” is electrically contacted from both the topside and the bottomside of the structure.
- the transistor device generally designated as “B” is not contacted from either the topside or bottomside, although metalization could be provided from either the topside or bottomside surfaces, or from both surfaces as in the case of transistor device A.
- the feedthrough 16' is formed by opening an aperture within the dielectric layer 11* and contacting the polysilicon pad 18' with metalization 21' and 28' and indium bumps 23• and 30 » .
- the steps illustrated in Figs. 1-6, or Figs. 9 and 10, are also performed with any number of other wafers 1. These other wafers are fabricated to have feedthroughs and/or indium bumps located in common positions so that they can be stacked, and the circuitry may be different on each wafer.
- Fig. 7 shows a multiplicity of Structures or wafers after stacking and interconnection to form a 3d integrated circuit assembly 40.
- Structure 1 at the bottom, provides rigid mechanical support for the overlying stack.
- Structure 1 may be identical to that shown in Figs. 5 or 9, with the original silicon substrate 10 left in place to provide the mechanical support.
- Structure 1 may be any suitable-Si or SOI wafer containing passive and/or active circuitry and interconnecting bumps on the top surface.
- Structures 2 and 3 are identical to that shown in Figs. 6 or 10, with the original silicon substrate 10 and also the temporary silicon substrate 26 removed.
- Structure 4 is similar to that shown in Figs. 6 or 10, with the exception of aluminum bonding pads 32 that have been fabricated on the topside surface instead of the indium bumps 23.
- a presently preferred method for forming the 3d integrated circuit 40 is as follows. Using an infrared microscope, two processed wafers are aligned to each other such that the indium bumps 30 on the bottom of Structure 2 are lined up with the indium bumps 23 on the top surface of Structure 1. The indium bumps are then brought into contact and fused together. A conventional cold weld process can be used for interconnecting the indium bumps. Everywhere outside the fused indium bumps there will be an air gap approximately 5 to 15 micrometers thick, depending on the height of the bumps and the degree of compression that occurs during bump fusing. This gap is then filled with a suitable material 34, such as an epoxy adhesive, to provide mechanical 12 support. The temporary substrate 26 is then removed from the top wafer (Structure 2) , exposing the indium bumps 23 on the topside surface.
- a suitable material 34 such as an epoxy adhesive
- Additional processed Structures are then incrementally stacked on top of the underlying Structures until a desired number of structures are incorporated into the 3d integrated circuit 40.
- Each additional Structure added to the stack requires that its bottomside indium bumps 30 be fused to the topside indium bumps 23 of the Structure below it, and then the temporary silicon substrate 26 removed from its top surface. These processes are repeated as often as required to build up the desired number of active layers.
- the entire 3d integrated circuit 40 can be bumped to a larger diameter wafer 42 through the topside indium bumps 23 of Structure 4 and corresponding indium bumps 44 on the larger diameter wafer 42.
- the larger diameter wafer 42 is provided with bonding pads 46 that are located outside of the area or footprint of the 3d integrated circuit 40, and interconnecting metalization 48. Connection to external circuitry is then made through the bonding pads 46, as opposed to the bonding pads 32 of Fig. 7. Conventional wirebonds can be employed for interfacing to the 3d integrated circuit 40.
- Wafer testing can b accomplished before applying the topside overglass an bumps.
- the bump formation is typically a high yiel process, the subsequent processing to add the overglass an bumps does, not adversely affect the wafer yield to significant degree.
- each of the resulting 3 circuits includes a number of vertically stacked thi silicon layers each of which contains desired circuitry an interconnects between layers.
- each Structure of the 3d integrate circuit 40 can contain circuitry that differs from th circuitry of the other • Structures.
- th circuitry can be analog circuitry, such as amplifiers an mixers, or may be digital circuitry, such as memories an microprocessors.
- several of the Structures ma contain analog circuitry while several others of th Structures may contain digital circuitry.
- a mixture o analog and digital circuitry within a single Structure is also possible. This enables the provision of a highl integrated, low volume device having mixed analog an digital functions.
- a given feedthrough 16 within one of the wafers is not required to be electrically coupled to any of the active or passive components that are fabricated within the Si layer 12 of that wafer. That is, a plurality of the feedthroughs 16 may pass through a number of wafers for vertically interconnecting circuitry within two non-adjacent wafers.
- topside and bottomside are provided for reference purposes only, and are not intended to indicate in an absolute sense a final orientation of a particular one of the wafers or assemblage of wafers.
- teaching of the invention is not limited for use only with silicon-based wafers. That is, the layer 12 within which the circuitry is formed may be comprised of a semiconductor material other than silicon, such as GaAs, the dielectric layer 11 may be other than Si0 2 , and the bulk substrate 10 may be other than silicon. In this case the etching process is suitably adjusted so as to select an etchant that is effective for removing the bulk substrate material.
- interconnection means between individual active circuit layers are not required to be indium bumps.
- solder bumps may be employed instead, and the process for joining individual ones of the Structures together adjusted accordingly.
Abstract
A method includes the steps of providing a first and a second Silicon-on-Insulator (SOI) wafer, wherein each SOI water includes a thin silicon layer (12) separated from a bulk silicon (10) substrate by a thin layer of dielectric material, typically SiO2 (11). A next step processes the thin silicon layers to form at least one electrical feedthrough (16) in each of the thin silicon layers (12) and to also form desired active and passive devices (17, 18, 19a, 19b) in each of the thin silicon layers. A next step forms interconnects (21) that overlie the thin silicon layer (12) and that are electrically coupled to the at least one feedthrough (16). One of the wafers is then attached to a temporary substrate such that the interconnects are interposed between the thin silicon layer and the temporary substrate. The bulk silicon substrate of the wafer having the temporary substrate is then removed by a step of etching the bulk silicon substrate so as to expose the dielectric layer. Further interconnects are then formed through the exposed dielectric layer for electrically contacting the at least one feedthrough. This results in the formation of a first circuit assembly. A next step then couples the further interconnects of the circuit assembly to the interconnects of the second SOI wafer, the second SOI wafer having a bulk substrate, a dielectric layer overlying a surface of the substrate, and a layer of processed silicon overlying the dielectric layer. The temporary substrate is then removed. Additional circuit assemblies may then be stacked and interconnected to form a 3d integrated circuit of a desired complexity.
Description
THREE DIMENSIONAL INTEGRATED CIRCUIT AND METHOD OF FABRICATING SAME
FIELD OF THE INVENTION;
This invention relates generally to integrated circuit manufacturing technology and, in particular, to-a method for fabricating a multi-layered, three-dimensional integrated circuit.
BACKGROUND OF THE INVENTION:
The fabrication of three-dimensional (3d) integrated circuits has been previously accomplished by several techniques. One approach employs a fabrication technology wherein active silicon films are grown in successive layers with intervening insulating layers. However, this approach must overcome difficult materials problems, and also generally precludes the testing of individual layers of the device. Furthermore, the total fabrication time is proportional to the number of layers, and becomes lengthy for a structure having more than three or four layers of active circuitry.
Another known approach involves the thinning and stacking of conventional integrated circuit dice into cubes, with additional processing to bring metal interconnects out to the edge of the cube. The cubes are then attached and electrically connected to a substrate by the use of solder bumps. However, this approach requires considerable handling of the small dice and therefore incurs high processing costs. Furthermore, all interconnects between the vertically stacked dice must be made at the edges. This tends to limit the operating speed by requiring additional lengths of conductors to bring the signals to and from the edges.
A third approach is described by Hayashi et al. , "Fabrication of Three-Dimensional IC Using 'Cumulatively Bonded IC (CUBIC) Technology", 1990 Symposium on VLSI Technology, which employs a method of thinning and stacking integrated circuit functional blocks and incorporating vertical interconnects between adjacent functional blocks. A supporting substrate is employed to support a Si layer when a Si crystal is removed by a preferential polishing method. The supporting substrate is later removed. A perceived disadvantage to this approach is that the bulk silicon crystal is required to mechanically thinned down, using a LOCOS-buried SiO as a polish stop. This process may be difficult to control in order not to remove the LOCOS-buried Si02, and cannot be readily applied to technologies other than LOCOS-isolated CMOS. This process also appears to require that the LOCOS-buried Si02 extend further into the Si than the active devices in the Si. This may present a serious limitation for many applications.
It is thus an object of this invention to overcome these and other problems of the prior art.
It is another object of this invention to provide a novel semiconductor fabrication technology to construct 3d integrated circuits of small volume by stacking Silicon-on- Insulator (SOI) integrated circuit wafers, wherein a silicon substrate is chemically etched away using the buried oxide as an etch stop.
A further object of this invention is to provide a fabrication technology that results in a 3d circuit that supports metal oxide semiconductor (MOS) , bipolar, or combination technologies; and that achieves a high circuit density through the use of thin silicon films with small vertical feedthroughs.
SUMMARY OF THE INVENTION
The foregoing and other problems are overcome and the objects of the invention are realized by a novel method for fabricating three dimensional integrated circuits. In a presently preferred embodiment the method includes the steps of providing a first and a second Silicon-on- Insulator (SOI) wafer, wherein each SOI wafer includes a thin silicon layer separated from a bulk silicon substrate by a thin layer of dielectric material, typically Si02. A next step processes the thin silicon layers to form at least one electrical feedthrough in each of the thin silicon layers and to also form desired active and passive devices in each of the thin silicon layers. A next step forms interconnects that overlie the thin silicon layer and that are electrically coupled to the at least one feedthrough. One of the wafers is then attached to a temporary substrate such that the interconnects are interposed between the thin silicon layer and the temporary substrate. The bulk silicon substrate of the wafer having the temporary substrate is then removed by a step of etching the bulk silicon substrate so as to expose the dielectric layer. Further interconnects are then formed through the exposed dielectric layer for electrically contacting the at least one feedthrough. This results in the formation of a first circuit assembly that includes the processed silicon layer, the interconnects formed over a first major surface (topside surface) of the processed silicon layer, and the further interconnects that are formed over a second major surface (bottomside surface) of the processed silicon layer. A next step then couples the further interconnects of the circuit assembly to the interconnects of a supporting substrate, such as a second SOI wafer having a bulk substrate, a dielectric layer overlying a surface of the substrate, and a layer of processed silicon overlying the dielectric layer. The temporary substrate is then removed. Additional circuit
assemblies may then be stacked and interconnected to form a 3d integrated circuit of a desired complexity.
The completed 3d wafer stack may be used in wafer form, or it may be sawed into 3d dice after stacking. Alternatively, individual dice may be cut from a circuit assembly, processed as described above, and stacked to form a 3d structure.
Methods for forming feedthroughs within a Si layer of an SOI wafer are also disclosed.
BRIEF DESCRIPTION OF THE DRAWING
The above set forth and other features of the invention are made more apparent in the ensuing Detailed Description of the Invention, when read in conjunction with the attached Drawing, wherein:
Figs. 1 through 7, not drawn to scale, are cross-sectional views that illustrate steps of a fabrication method of the invention;
Fig. 8, not drawn to scale, illustrates an embodiment of a 3d integrated circuit assembly that is connected to a larger diameter carrier wafer; and
Figs. 9 and 10, not drawn to scale, are cross-sectional views that illustrate an embodiment of the invention wherein a thin Si film has active device structures that extend through a total thickness of the film.
DETAILED DESCRIPTION OF THE INVENTION
Referring to Fig. 1, a first fabrication step provides an SOI wafer 1 that includes of a silicon film 12 separated from a bulk silicon wafer 10 by an SiO layer 11. The presence of the Si02 layer 11 facilitates the performance
5 of the etching step described below. The thickness of the silicon film 12 is typically within a range of approximately 0.2 micrometers to approximately 10 micrometers. The thickness of the Si02 layer 11 is not critical, and is typically in the range of approximately 0.1 micrometers to approximately 1.5 micrometers. The thickness of the substrate 10 is approximately 600 micrometers. The overall diameter of the wafer 1 is typically in the range of approximately 100 mm to approximately 200 mm.
A presently preferred method for forming the Si film 12 is by bonding two silicon wafers together with a fused oxide layer, and then thinning one of the wafers to form the thin film Si layer 12. This technique allows optimum control in the thickness and composition of the buried insulator 11, and provides a high quality Si film. It is noted that both wafers need not be crystalline Si. By example, one of the wafers may be polycrystalline Si and the other crystalline Si, with the crystalline Si being thinned to provide the Si film 12 within which active devices are fabricated. Alternatively, SIMOX (Separation by Implanted Oxygen) or ZMR (Zone Melt and Recrystallization) wafers could be used.
It is noted that the SOI wafer 1 can also be purchased commercially.
By whatever method the SOI wafer 1 is obtained, the next steps of the process depend upon the thickness of the Si film 12. In general, the Si film 12 can be characterized as being either a "thick" film, having a thickness greater than approximately one micrometer, or a "thin" film having a thickness less than approximately one micrometer. In the thick film case, trenches are formed to provide vertical feedthroughs. In the thin film case, the vertical feedthroughs can be readily formed within gaps made between transistor mesas. Figs. 2-6 illustrate the thick film case,
while Figs. 9 and 10 illustrate the thin film case.
In Fig. 2 a conventional LOCOS process has been employed t form regions of isoplanar Si02 13 on the surface of the s layer 12. Transistors can be formed within active areas that is, areas not covered by the isoplanar oxide 13.
Fig. 3 illustrates the SOI wafer 1 after trenches 14 hav been etched by an anisotrophic plasma etch process Trenches are typically formed both in the active region (trench 14a) and in the isoplanar field regions (trenc 14b) so as to provide optimum vertical interconnec placement flexibility.
In greater detail, and referring also to Fig. 4, th feedthroughs 16 are formed by etching the trenches 14a an
14b through the silicon layer 12 to the underlying SiO layer 11, with the SiO_ layer 11 functioning as an etc
; stop. The trench walls, and the upper surface of th silicon film 12, are oxidized using a conventional therma oxidation process to form a dielectric SiO layer 15 havin a thickness of approximately 0.1 micron. The remainin opening within each trench is then filled with a electrically conductive material 16a. Heavily dope pol crystalline silicon (polysilicon) is a preferre electrically conductive material, although othe electrically conductive materials, such as tungsten, ma also be employed. Phosphorus or Arsenic are the preferre dopants at concentrations sufficient to provide ' th required conductivity, which may vary depending upon th application.
Alternatively, for the thin film case described below wit reference to Figs. 9 and 10, the feedthroughs result whe the Si film 12 is etched to form islands where th transistors will be made. The space-between these island is then available for use by feedthroughs. Furthermore, the diffusions (e.g. source and drain diffusions for MO
transistors) will generally extend completely through the Si layer 12 and may be used as feedthroughs.
In the thick film case each feedthrough 16 includes an electrically conductive member 16a surrounded by an electrically insulating Si02 region (15) .
In Fig. 5 the structure formed thus far is processed to form an integrated circuit. A CMOS process is described, but any other process, such as bipolar or bipolar/CMOS, may also be employed. N-type and p-type regions are formed where desired within the silicon film 12. These regions are delineated through a photolithographic process and are formed through a diffusion or an ion implantation step. The sacrificial Si02 layer 15 is then removed and a further Si02 layer 17 is formed to serve as the gate oxide, the Si02 layer 17 being formed by oxidizing the silicon film 12. One or more polysilicon gate electrodes 18 are also deposited, as required, upon the Si02 layer 17. P+ and n+ regions 19a and 19b, respectively, are then photolithographically defined and diffused or implanted to serve as the source and drain regions of p and n-channel transistors, respectively.
A layer 20 of Si02 is then deposited over the polysilicon gate electrodes 18. Openings are defined and etched within the Si02 layer 20, and metalization 21 is deposited so as to contact the conductive feedthroughs 16, the polysilicon electrodes 18, and the p+ and n+ regions 19a and 19b within the silicon film 12. As can be seen, a number of active devices (FETs) are thus formed, as may also be polysilicon resistors and other conventional devices. Additional layers of metal interconnects may also be added (as described below) , followed by an insulating overglass layer 22 that is deposited in a conventional manner. Finally, openings are defined and etched into the overglass layer 22, and "topside" indium bumps 23 are formed to contact the metalization 21 within the openings.
It is noted that the indium bumps 23 are located where desired for eventual interconnection to another wafer that is processed as thus far described, and are not required to be located directly over the vertical feedthroughs 16. That is, routing metalization can be applied before the deposition of the overglass layer 22 in order to locate the indium bumps 23 at desired locations.
In Fig. 6 a second, temporary substrate 26, typically comprised of Si, is attached to the upper surface of the completed wafer shown in Fig. 5. Other suitable materials for the second substrate 26 include quartz and crystalline
A1203 (sapphire) . A consideration in the choice of material for the second substrate 26 is the coefficient of thermal expansion of the material, if the additional processing steps described below are performed at elevated temperatures. That is, the selected material for the second substrate 26 should have a coefficient of thermal expansion that is similar to that of Si to avoid undue deformation of the Si film 12 when the assembly is heated.
The temporary attachment of the substrate 26 is made with a bonding layer 24 comprised of a wax or a similar material which can be readily removed later. The second substrate 26 provides mechanical support for the silicon layer 12 during the ensuing steps of the method, and has a suitable thickness for providing the required mechanical support.
Next, the first silicon substrate 10 is removed. This is accomplished, in accordance with an aspect of this invention, through the use of an etching process, or a lapping process, to remove a portion of the substrate 10, followed by an etching process. The etchant is chosen so that it stops at the Si02 layer 11 which separates the silicon substrate 10 from the thin silicon film 12 containing the active and passive circuitry. Suitable etching processes include the use of a hot KOH solution (60'C to 80'C) or a plasma etch that is highly selective
for Si. As a result, a well controlled and complete removal of the silicon substrate 10 is achieved. If needed, a protective layer, such as a thin layer of epoxy, can be provided around the periphery of the wafer to protect the Si layer 12 during the etching process.
In this regard, the temporary substrate 26 may be provided with a larger diameter than the wafer 1 to facilitate providing the protective layer at the periphery of the wafer 1. For example, if the wafer 1 has a diameter of 100 mm, a suitable diameter for the temporary substrate 26 is 125 mm.
The structure formed thus far is then processed with conventional processing steps to define and etch contact openings in the now exposed dielectric layer 11, followed by the formation of bonding pads 28, typically comprised of aluminum, an overglass layer 29, and "bottomside" indium bumps 30.
This further processing results in the formation of an intermediate Structure or circuit assembly having active and passive electrical components located within the silicon layer 12, and topside and bottomside interconnects for coupling to other Structures.
In general, one of the bottomside indium bumps 30 will be associated with one of the vertical feedthroughs 16. However, a bottomside indium bump 30 need not be located so as to directly overlie a feedthrough. That is, bottomside metalization can be applied before the application of the overglass layer 29 so as to provide signal routing from the contacts 28 to any desired location on the bottomside surface, thereby enabling the indium bumps 30 to be located at the periphery of the wafer or at any desired location. One such indium bump is shown generally as 30a. The bump 30a is connected to its respective feedthrough 28 through an intervening strip of signal routing metalization 31.
Figs. 9 and 10 are cross-sectional views that correspond to Figs. 5 and 6, respectively, for the thin film case wherein the Si layer has a thickness of less than one micrometer, and preferably less than approximately 0.5 micrometers. In Figs. 9 and 10 the reference numerals that correspond to the reference numerals in Figs. 5 and 6 are designated with primes.
As can be seen in Fig. 9, the Si layer 12' has been selectively removed down to the SiO_ layer 11'. The remaining Si material forms islands or mesas within which active and passive devices are formed by selective doping. Due to the thinness of the Si layer 12• , the doped regions extend completely through the Si layer 12*. A feedthrough 16' is partially formed by depositing a doped polysilicon pad 18' onto the dielectric layer 11' within an area between mesas, and contacting the doped polysilicon pad 18' with metalization 21'.
In Fig. 10 the bulk substrate 10' has been removed and the temporary substrate 26' attached. Furthermore, apertures have been opened in the dielectric layer 11' and bottomside metalization 28' applied, after which the bottomside indium bumps 30' are formed.
As can be seen, in this embodiment of the invention the transistor device generally designated as "A" is electrically contacted from both the topside and the bottomside of the structure. The transistor device generally designated as "B" is not contacted from either the topside or bottomside, although metalization could be provided from either the topside or bottomside surfaces, or from both surfaces as in the case of transistor device A. The feedthrough 16' is formed by opening an aperture within the dielectric layer 11* and contacting the polysilicon pad 18' with metalization 21' and 28' and indium bumps 23• and 30» .
The steps illustrated in Figs. 1-6, or Figs. 9 and 10, are also performed with any number of other wafers 1. These other wafers are fabricated to have feedthroughs and/or indium bumps located in common positions so that they can be stacked, and the circuitry may be different on each wafer.
Fig. 7 shows a multiplicity of Structures or wafers after stacking and interconnection to form a 3d integrated circuit assembly 40. Structure 1, at the bottom, provides rigid mechanical support for the overlying stack. Structure 1 may be identical to that shown in Figs. 5 or 9, with the original silicon substrate 10 left in place to provide the mechanical support.
Alternatively, Structure 1 may be any suitable-Si or SOI wafer containing passive and/or active circuitry and interconnecting bumps on the top surface. Structures 2 and 3 are identical to that shown in Figs. 6 or 10, with the original silicon substrate 10 and also the temporary silicon substrate 26 removed. Structure 4 is similar to that shown in Figs. 6 or 10, with the exception of aluminum bonding pads 32 that have been fabricated on the topside surface instead of the indium bumps 23.
A presently preferred method for forming the 3d integrated circuit 40 is as follows. Using an infrared microscope, two processed wafers are aligned to each other such that the indium bumps 30 on the bottom of Structure 2 are lined up with the indium bumps 23 on the top surface of Structure 1. The indium bumps are then brought into contact and fused together. A conventional cold weld process can be used for interconnecting the indium bumps. Everywhere outside the fused indium bumps there will be an air gap approximately 5 to 15 micrometers thick, depending on the height of the bumps and the degree of compression that occurs during bump fusing. This gap is then filled with a suitable material 34, such as an epoxy adhesive, to provide mechanical
12 support. The temporary substrate 26 is then removed from the top wafer (Structure 2) , exposing the indium bumps 23 on the topside surface.
Additional processed Structures are then incrementally stacked on top of the underlying Structures until a desired number of structures are incorporated into the 3d integrated circuit 40. Each additional Structure added to the stack requires that its bottomside indium bumps 30 be fused to the topside indium bumps 23 of the Structure below it, and then the temporary silicon substrate 26 removed from its top surface. These processes are repeated as often as required to build up the desired number of active layers.
In the embodiment shown in Fig. 7, no indium bumps are required on the top surface of the top Structure. Rather, conventional technology is used to route the metal out to the bonding pads 32.
Alternatively, and as is shown in Fig. 8, the entire 3d integrated circuit 40 can be bumped to a larger diameter wafer 42 through the topside indium bumps 23 of Structure 4 and corresponding indium bumps 44 on the larger diameter wafer 42. The larger diameter wafer 42 is provided with bonding pads 46 that are located outside of the area or footprint of the 3d integrated circuit 40, and interconnecting metalization 48. Connection to external circuitry is then made through the bonding pads 46, as opposed to the bonding pads 32 of Fig. 7. Conventional wirebonds can be employed for interfacing to the 3d integrated circuit 40.
A consideration when stacking the Structures is the overall yield of the individual dice or circuit areas upon each wafer. As such, the provision of redundant circuitry and interconnections may be advantageous in order to enable the elimination of defective circuits and the replacement of
same with operational, circuits. Wafer testing can b accomplished before applying the topside overglass an bumps. In that the bump formation is typically a high yiel process, the subsequent processing to add the overglass an bumps does, not adversely affect the wafer yield to significant degree.
Referring again to Figs. 6 and 10, it is within the scop of the invention to saw the processed Si film and temporar substrate 26 into individual dice, and then stack an interconnect the dice as described above for the case o the wafer-sized Structures. It is also within the scope o the invention to fabricate the 3d integrated circuit 40 o Fig. 7, and to then subsequently saw the circuit int individual dice. In either case, each of the resulting 3 circuits includes a number of vertically stacked thi silicon layers each of which contains desired circuitry an interconnects between layers.
As can be realized, each Structure of the 3d integrate circuit 40 can contain circuitry that differs from th circuitry of the other • Structures. Furthermore, th circuitry can be analog circuitry, such as amplifiers an mixers, or may be digital circuitry, such as memories an microprocessors. Also, several of the Structures ma contain analog circuitry while several others of th Structures may contain digital circuitry. A mixture o analog and digital circuitry within a single Structure is also possible. This enables the provision of a highl integrated, low volume device having mixed analog an digital functions.
It should also be realized that a given feedthrough 16 within one of the wafers is not required to be electrically coupled to any of the active or passive components that are fabricated within the Si layer 12 of that wafer. That is, a plurality of the feedthroughs 16 may pass through a number of wafers for vertically interconnecting circuitry
within two non-adjacent wafers.
It should further be realized that the terms "topside" and "bottomside" are provided for reference purposes only, and are not intended to indicate in an absolute sense a final orientation of a particular one of the wafers or assemblage of wafers. Furthermore, the teaching of the invention is not limited for use only with silicon-based wafers. That is, the layer 12 within which the circuitry is formed may be comprised of a semiconductor material other than silicon, such as GaAs, the dielectric layer 11 may be other than Si02, and the bulk substrate 10 may be other than silicon. In this case the etching process is suitably adjusted so as to select an etchant that is effective for removing the bulk substrate material.
It is also pointed out that the interconnection means between individual active circuit layers are not required to be indium bumps. For example, solder bumps may be employed instead, and the process for joining individual ones of the Structures together adjusted accordingly.
Thus, while the invention has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the scope and spirit bf the invention.
SUBSTITUTESHEET
Claims
1. A method of fabricating a circuit assembly, comprising the steps of:
providing a multilayered wafer having a first substrate, a dielectric layer overlying a surface of the first substrate, and a layer of semiconductor material overlying the dielectric layer;
processing the semiconductor material layer to form at least one electrically conductive feedthrough and to form circuitry within the semiconductor material layer;
forming interconnection means that overlie the semiconductor material layer and that are electrically coupled to the at least one feedthrough;
attaching a temporary substrate such that the interconnection means are interposed between the semiconductor material layer and the temporary substrate;
removing the first substrate, the step of removing including a step of etching the first substrate so as to expose the dielectric layer; and
forming further interconnection means through the dielectric layer for electrically coupling at least to the at least one feedthrough.
2. The method of claim 1 wherein the step of attaching includes a step of providing a protective material at a periphery of the multilayered wafer, the protective material being selected to resist a selected etchant to protect edges of the layer of semiconductor material.
3. The method of claim 1 wherein the first substrate is comprised of silicon, and wherein the step of etching employs a KOH solution.
4. The method of claim 1 wherein the step of etching employs plasma etching.
5. The method of claim 1 wherein the step of forming interconnection means includes an initial step of depositing an electrically insulating overglass layer on the semiconductor material layer.
6. The method of claim 1 wherein the step of removing the first substrate comprises the steps of first lapping and then etching the first substrate.
7. The method of claim 1 wherein steps of forming interconnection means and further interconnection means each include a step of forming an indium bump in registration with said at least one feedthrough, the indium bump being electrically coupled to said at least one feedthrough.
8. The method of claim 1 wherein steps of forming interconnection means and further interconnection means each include a step of forming an indium bump at a selected location, the indium bump being electrically coupled to said at least one feedthrough.
9. The method of claim 1 wherein steps of forming interconnection means and further interconnection means each include a step of forming a solder bump at a selected location, the solder bump being electrically coupled to said at least one feedthrough.
10. The method of claim 1 and further comprising a step of sawing the circuit assembly into a plurality of smaller circuit assemblies.
11. The method of claim 10 and further comprising the steps of:
removing a portion of the temporary substrate from a first smaller circuit assembly;
stacking a second smaller circuit assembly upon the first smaller circuit assembly;
electrically interconnecting the further interconnection means of the second smaller circuit assembly to the interconnection means of the first smaller circuit assembly; and
removing a portion of the temporary substrate from the second smaller circuit assembly.
12. The method of claim 1 and further comprising the steps of:
removing the temporary substrate from a first circuit assembly;
stacking a second circuit assembly upon the first circuit assembly;
electrically interconnecting the further interconnection means of the second circuit assembly to the interconnection means of the first circuit assembly; and
removing the temporary substrate from the second circuit assembly. 18
13. The method of claim 12 and further comprising the step of sawing the electrically interconnected first and second circuit assemblies into a plurality of smaller, electrically interconnected circuit assemblies.
14. A method of fabricating a three-dimensional integrated circuit assembly, comprising the steps of:
providing a first multilayered wafer having a first substrate, a dielectric layer overlying a surface of the first substrate, and a layer of semiconductor material overlying the dielectric layer;
processing the semiconductor material layer to form at least one electrically conductive feedthrough and to form circuitry as required within the semiconductor material layer;
forming interconnection means that overlies the semiconductor material layer and that is electrically coupled to the at least one feedthrough;
attaching the first wafer to a temporary substrate such that the interconnection means is interposed between the semiconductor material layer and the temporary substrate;
removing the first substrate, the step of removing including a step of etching the first substrate so as to expose the dielectric layer;
forming further interconnection means through the dielectric layer for electrically contacting at least the at least one feedthrough, the step of forming further interconnection means resulting in a first circuit assembly that includes the processed semiconductor material layer, the interconnection means formed over a first major surface of the 19 processed semiconductor material layer, and the further interconnection means formed over a second major surface of the processed semiconductor layer;
coupling the further interconnection means to interconnection means of a second wafer, the second multilayered wafer including a supporting substrate; and
removing the temporary substrate.
15. The method of claim 14 wherein the first substrate is comprised of silicon, and wherein the step of etching employs a KOH solution.
16. The method of claim 14 wherein the step of etching includes a step of plasma etching.
17. The method of claim 14 and further comprising the steps of:
coupling the further interconnection means of a second circuit assembly to the interconnection means of the first circuit assembly, thereby forming a stack of circuit assemblies; and
removing a temporary substrate from the second circuit assembly.
18. The method of claim 17 and, after a last circuit assembly is coupled to the stack of circuit assemblies, further comprising a step of coupling the interconnection means of the last circuit assembly to interconnection means of a further substrate, the further substrate having a surface area that is greater than a surface area of the stack of circuit assemblies, the further substrate being provided with electrical contact means for coupling the stack of circuit assemblies to other circuitry.
19. The method of claim 17 wherein a last circuit assembly that is coupled to the stack of circuit assemblies includes electrical contact means for coupling the stack of circuit assemblies to other circuitry.
20. The method of claim 14 wherein the step of forming interconnection means includes an initial step of depositing an electrically insulating overglass layer on the semiconductor material layer.
21. The method of claim 14 wherein the step of removing the first substrate comprises the steps of first lapping and then etching the first substrate.
22. The method of claim 14 wherein steps of forming interconnection means and further interconnection means each include a step of forming an indium bump that is electrically coupled to the at least one feedthrough.
23. The method of claim 14 wherein steps of forming interconnection means and further interconnection means each include a step of forming a solder bump that is electrically coupled to the at least one feedthrough.
24. The method of claim 17 and, after a last circuit assembly is coupled to the stack of circuit assemblies, further comprising a step of sawing the stack of circuit assemblies into a plurality of stacks of circuit assemblies.
25. A three-dimensional integrated circuit assembly comprising:
a supporting substrate; and
a stack comprised of a plurality of semiconductor material film layers disposed upon the supporting substrate, each film layer having a dielectric layer 21 disposed upon a first surface thereof, each film layer including passive and active devices formed therein and vertical interconnect means formed at least through said dielectric layer, at least some of the devices and vertical interconnect means associated with each of said film layers being electrically coupled together by interconnecting means formed between the film layers, the interconnecting means of a given film layer being provided above a second surface that is opposite the first surface and also at the first surface by way of apertures that are formed through the dielectric layer.
26. The assembly of claim 25 wherein said film layers are provided by etching away a bulk substrate to which each was originally attached, the bulk substrate being etched away so as to expose the dielectric layer so as to enable the formation of the apertures and interconnecting means.
27. The assembly of claim 25 and further comprising an additional substrate having a surface area that is larger than a surface area of the first surface of the film layers, the additional substrate having bonding pads disposed thereon and connected to said interconnecting means for enabling the assembly to be electrically coupled to external circuitry.
28. The assembly of claim 25 wherein * the interconnecting means are comprised of bumps of electrically conducting material.
29. The assembly of claim 25 and further comprising a layer of epoxy adhesive that is interposed between each of said film layers.
30. A method of forming an electrically conductive feedthrough through a Si layer of an SOI wafer, comprising the steps of :
etching a trench through the Si layer, the trench extending completely though the Si layer and terminating at a layer of dielectric material within the SOI wafer;
oxidizing walls of the trench to form a layer of dielectric material upon the walls; and
filling the trench with an electrically conductive material.
31. A method as set forth in claim 30, and further including the steps of:
forming a first contact pad that is electrically coupled to a first portion end of the electrically conductive material;
removing a supporting substrate of the SOI wafer to expose a surface of the dielectric layer of the SOI wafer;
opening an aperture within the dielectric layer;
forming a second contact pad through the aperture, the second contact pad being electrically coupled to a second end portion of the electrically conductive material; and
applying first and second bumps comprised of electrically conductive material, the first and second bumps being electrically coupled to the first and second contact pads, respectively.
32. A method of forming an electrically conductive feedthrough in an SOI wafer, comprising the steps of: selectively removing a portion of a Si layer of the SOI wafer to expose a portion of a first surface of an underlying dielectric layer;
forming an electrically conductive pad upon an exposed portion of the first surface of the dielectric layer;
forming a first electrically conductive member that contacts a first surface of the pad;
removing a supporting substrate of the SOI wafer to expose a second surface of the dielectric layer;
opening an aperture through the second surface of the dielectric layer; and
forming a second electrically conductive member through the aperture to contact a second surface of the pad.
33. A method as set forth in Claim 32 and further including a step of applying first and second bumps of electrically conductive material, each of the bumps being electrically coupled to one of the electrically conductive members.
34. An intermediate circuit structure for use in constructing a three dimensional integrated circuit, the structure comprising:
an active layer region that includes semiconductor material having circuitry formed therein, said active layer region having a first major surface and a second major surface;
first electrical interconnect means disposed over said first major surface for electrically coupling to at least some of said circuitry; a layer of dielectric material disposed upon the second major surface;
second electrical interconnect means disposed over said second major surface for electrically coupling to at least some of said circuitry, said second electrical interconnect means passing through an aperture within said layer of dielectric material; and
a supporting substrate disposed over said first major surface and removably coupled thereto by an intervening layer of material.
35. An intermediate circuit structure as set forth in claim 34 and further comprising at least one electrical feedthrough means that passes between said first and second major surfaces and through an aperture within said layer of dielectric material.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6517067A JPH07506936A (en) | 1993-01-21 | 1994-01-10 | Three-dimensional integrated circuit and its manufacturing method |
EP94906589A EP0631692A1 (en) | 1993-01-21 | 1994-01-10 | Three dimensional integrated circuit and method of fabricating same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/006,601 US5426072A (en) | 1993-01-21 | 1993-01-21 | Process of manufacturing a three dimensional integrated circuit from stacked SOI wafers using a temporary silicon substrate |
US006,601 | 1993-01-21 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1994017553A1 true WO1994017553A1 (en) | 1994-08-04 |
Family
ID=21721669
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1994/000363 WO1994017553A1 (en) | 1993-01-21 | 1994-01-10 | Three dimensional integrated circuit and method of fabricating same |
Country Status (4)
Country | Link |
---|---|
US (1) | US5426072A (en) |
EP (1) | EP0631692A1 (en) |
JP (1) | JPH07506936A (en) |
WO (1) | WO1994017553A1 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2775387A1 (en) * | 1998-02-26 | 1999-08-27 | Mitsubishi Electric Corp | SEMICONDUCTOR DEVICE HAVING SELF STRUCTURE AND MANUFACTURING METHOD |
EP0942466A1 (en) * | 1997-04-11 | 1999-09-15 | Kabushiki Kaisha Toshiba | Process for manufacturing semiconductor device and semiconductor component |
WO2000031796A1 (en) * | 1998-11-20 | 2000-06-02 | Giesecke & Devrient Gmbh | Method for producing an integrated circuit processed on both sides |
WO2007131867A1 (en) * | 2006-05-16 | 2007-11-22 | International Business Machines Corporation | Dual wired integrated circuit chips |
EP2186128A1 (en) * | 2007-08-10 | 2010-05-19 | Agency For Science, Technology And Research (A*star) | Nano-interconnects for atomic and molecular scale circuits |
Families Citing this family (165)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5354695A (en) * | 1992-04-08 | 1994-10-11 | Leedy Glenn J | Membrane dielectric isolation IC fabrication |
US6714625B1 (en) * | 1992-04-08 | 2004-03-30 | Elm Technology Corporation | Lithography device for semiconductor circuit pattern generation |
US5985693A (en) * | 1994-09-30 | 1999-11-16 | Elm Technology Corporation | High density three-dimensional IC interconnection |
US6008126A (en) * | 1992-04-08 | 1999-12-28 | Elm Technology Corporation | Membrane dielectric isolation IC fabrication |
US5737192A (en) * | 1993-04-30 | 1998-04-07 | The United States Of America As Represented By The Secretary Of The Air Force | Density improvement in integration modules |
US5382759A (en) * | 1993-09-28 | 1995-01-17 | Trw Inc. | Massive parallel interconnection attachment using flexible circuit |
DE69428181T2 (en) * | 1993-12-13 | 2002-06-13 | Matsushita Electric Ind Co Ltd | Device with chip housing and method for its manufacture |
DE59503218D1 (en) * | 1994-02-07 | 1998-09-24 | Siemens Ag | Method for producing a cubic integrated circuit arrangement |
DE707741T1 (en) * | 1994-05-05 | 1996-11-28 | Siliconix Inc | SURFACE MOUNTING AND FLIP-CHIP TECHNOLOGY |
US5753529A (en) * | 1994-05-05 | 1998-05-19 | Siliconix Incorporated | Surface mount and flip chip technology for total integrated circuit isolation |
US5902118A (en) * | 1994-07-05 | 1999-05-11 | Siemens Aktiengesellschaft | Method for production of a three-dimensional circuit arrangement |
US5880010A (en) * | 1994-07-12 | 1999-03-09 | Sun Microsystems, Inc. | Ultrathin electronics |
MY114888A (en) * | 1994-08-22 | 2003-02-28 | Ibm | Method for forming a monolithic electronic module by stacking planar arrays of integrated circuit chips |
US5567654A (en) * | 1994-09-28 | 1996-10-22 | International Business Machines Corporation | Method and workpiece for connecting a thin layer to a monolithic electronic module's surface and associated module packaging |
US5767578A (en) * | 1994-10-12 | 1998-06-16 | Siliconix Incorporated | Surface mount and flip chip technology with diamond film passivation for total integated circuit isolation |
US5841197A (en) * | 1994-11-18 | 1998-11-24 | Adamic, Jr.; Fred W. | Inverted dielectric isolation process |
US6124179A (en) * | 1996-09-05 | 2000-09-26 | Adamic, Jr.; Fred W. | Inverted dielectric isolation process |
WO1996020497A1 (en) * | 1994-12-23 | 1996-07-04 | Philips Electronics N.V. | Method of manufacturing semiconductor devices with semiconductor elements formed in a layer of semiconductor material glued on a support wafer |
DE19509231C2 (en) * | 1995-03-17 | 2000-02-17 | Ibm | Method of applying a metallization to an insulator and opening through holes in it |
US6020257A (en) * | 1995-06-07 | 2000-02-01 | Elm Technology Corporation | Membrane dielectric isolation IC fabrication |
US5674785A (en) * | 1995-11-27 | 1997-10-07 | Micron Technology, Inc. | Method of producing a single piece package for semiconductor die |
US6013948A (en) | 1995-11-27 | 2000-01-11 | Micron Technology, Inc. | Stackable chip scale semiconductor package with mating contacts on opposed surfaces |
US6861290B1 (en) * | 1995-12-19 | 2005-03-01 | Micron Technology, Inc. | Flip-chip adaptor package for bare die |
US5904546A (en) * | 1996-02-12 | 1999-05-18 | Micron Technology, Inc. | Method and apparatus for dicing semiconductor wafers |
US5952725A (en) * | 1996-02-20 | 1999-09-14 | Micron Technology, Inc. | Stacked semiconductor devices |
US5789271A (en) * | 1996-03-18 | 1998-08-04 | Micron Technology, Inc. | Method for fabricating microbump interconnect for bare semiconductor dice |
US6784023B2 (en) * | 1996-05-20 | 2004-08-31 | Micron Technology, Inc. | Method of fabrication of stacked semiconductor devices |
US5817530A (en) * | 1996-05-20 | 1998-10-06 | Micron Technology, Inc. | Use of conductive lines on the back side of wafers and dice for semiconductor interconnects |
US5949144A (en) * | 1996-05-20 | 1999-09-07 | Harris Corporation | Pre-bond cavity air bridge |
US5953626A (en) * | 1996-06-05 | 1999-09-14 | Advanced Micro Devices, Inc. | Dissolvable dielectric method |
US6376330B1 (en) | 1996-06-05 | 2002-04-23 | Advanced Micro Devices, Inc. | Dielectric having an air gap formed between closely spaced interconnect lines |
US5814555A (en) | 1996-06-05 | 1998-09-29 | Advanced Micro Devices, Inc. | Interlevel dielectric with air gaps to lessen capacitive coupling |
US6809421B1 (en) | 1996-12-02 | 2004-10-26 | Kabushiki Kaisha Toshiba | Multichip semiconductor device, chip therefor and method of formation thereof |
JP3695893B2 (en) * | 1996-12-03 | 2005-09-14 | 沖電気工業株式会社 | Semiconductor device, manufacturing method and mounting method thereof |
KR100251859B1 (en) * | 1997-01-28 | 2000-04-15 | 마이클 디. 오브라이언 | Singulation method of ball grid array semiconductor package manufacturing by using flexible circuit board strip |
US5923067A (en) * | 1997-04-04 | 1999-07-13 | International Business Machines Corporation | 3-D CMOS-on-SOI ESD structure and method |
US5915167A (en) | 1997-04-04 | 1999-06-22 | Elm Technology Corporation | Three dimensional structure memory |
US6551857B2 (en) | 1997-04-04 | 2003-04-22 | Elm Technology Corporation | Three dimensional structure integrated circuits |
US5904495A (en) * | 1997-06-11 | 1999-05-18 | Massachusetts Institute Of Technology | Interconnection technique for hybrid integrated devices |
FR2765398B1 (en) * | 1997-06-25 | 1999-07-30 | Commissariat Energie Atomique | STRUCTURE WITH MICROELECTRONIC COMPONENT IN SEMICONDUCTOR MATERIAL DIFFICULT OF ENGRAVING AND WITH METAL HOLES |
US6097096A (en) * | 1997-07-11 | 2000-08-01 | Advanced Micro Devices | Metal attachment method and structure for attaching substrates at low temperatures |
US6069398A (en) * | 1997-08-01 | 2000-05-30 | Advanced Micro Devices, Inc. | Thin film resistor and fabrication method thereof |
US5888853A (en) * | 1997-08-01 | 1999-03-30 | Advanced Micro Devices, Inc. | Integrated circuit including a graded grain structure for enhanced transistor formation and fabrication method thereof |
US5949092A (en) * | 1997-08-01 | 1999-09-07 | Advanced Micro Devices, Inc. | Ultra-high-density pass gate using dual stacked transistors having a gate structure with planarized upper surface in relation to interlayer insulator |
US5898189A (en) * | 1997-08-04 | 1999-04-27 | Advanced Micro Devices, Inc. | Integrated circuit including an oxide-isolated localized substrate and a standard silicon substrate and fabrication method |
US5892287A (en) * | 1997-08-18 | 1999-04-06 | Texas Instruments | Semiconductor device including stacked chips having metal patterned on circuit surface and on edge side of chip |
US6294455B1 (en) | 1997-08-20 | 2001-09-25 | Micron Technology, Inc. | Conductive lines, coaxial lines, integrated circuitry, and methods of forming conductive lines, coaxial lines, and integrated circuitry |
US6143616A (en) | 1997-08-22 | 2000-11-07 | Micron Technology, Inc. | Methods of forming coaxial integrated circuitry interconnect lines |
US6187677B1 (en) | 1997-08-22 | 2001-02-13 | Micron Technology, Inc. | Integrated circuitry and methods of forming integrated circuitry |
US6096576A (en) | 1997-09-02 | 2000-08-01 | Silicon Light Machines | Method of producing an electrical interface to an integrated circuit device having high density I/O count |
US5843806A (en) * | 1997-11-24 | 1998-12-01 | Compeq Manufacturing Company Limited | Methods for packaging tab-BGA integrated circuits |
US5869379A (en) * | 1997-12-08 | 1999-02-09 | Advanced Micro Devices, Inc. | Method of forming air gap spacer for high performance MOSFETS' |
US5973391A (en) * | 1997-12-11 | 1999-10-26 | Read-Rite Corporation | Interposer with embedded circuitry and method for using the same to package microelectronic units |
US6833613B1 (en) | 1997-12-18 | 2004-12-21 | Micron Technology, Inc. | Stacked semiconductor package having laser machined contacts |
US6620731B1 (en) * | 1997-12-18 | 2003-09-16 | Micron Technology, Inc. | Method for fabricating semiconductor components and interconnects with contacts on opposing sides |
US6114240A (en) | 1997-12-18 | 2000-09-05 | Micron Technology, Inc. | Method for fabricating semiconductor components using focused laser beam |
US6107109A (en) * | 1997-12-18 | 2000-08-22 | Micron Technology, Inc. | Method for fabricating a semiconductor interconnect with laser machined electrical paths through substrate |
US6160316A (en) * | 1998-03-04 | 2000-12-12 | Advanced Micro Devices, Inc. | Integrated circuit utilizing an air gap to reduce capacitance between adjacent metal linewidths |
USRE43112E1 (en) | 1998-05-04 | 2012-01-17 | Round Rock Research, Llc | Stackable ball grid array package |
US6137173A (en) * | 1998-06-30 | 2000-10-24 | Intel Corporation | Preventing backside analysis of an integrated circuit |
US6107119A (en) * | 1998-07-06 | 2000-08-22 | Micron Technology, Inc. | Method for fabricating semiconductor components |
US6303986B1 (en) | 1998-07-29 | 2001-10-16 | Silicon Light Machines | Method of and apparatus for sealing an hermetic lid to a semiconductor die |
TW442873B (en) * | 1999-01-14 | 2001-06-23 | United Microelectronics Corp | Three-dimension stack-type chip structure and its manufacturing method |
US6352923B1 (en) * | 1999-03-01 | 2002-03-05 | United Microelectronics Corp. | Method of fabricating direct contact through hole type |
DE19918671B4 (en) * | 1999-04-23 | 2006-03-02 | Giesecke & Devrient Gmbh | Vertically integrable circuit and method for its manufacture |
US6429509B1 (en) * | 1999-05-03 | 2002-08-06 | United Microelectronics Corporation | Integrated circuit with improved interconnect structure and process for making same |
WO2000074134A1 (en) * | 1999-05-27 | 2000-12-07 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Method for the vertical integration of electric components by |
US6249136B1 (en) * | 1999-06-28 | 2001-06-19 | Advanced Micro Devices, Inc. | Bottom side C4 bumps for integrated circuits |
US6703286B1 (en) * | 1999-07-29 | 2004-03-09 | Taiwan Semiconductor Manufacturing Company | Metal bond pad for low-k inter metal dielectric |
US6281041B1 (en) * | 1999-11-30 | 2001-08-28 | Aptos Corporation | Process to make a tall solder ball by placing a eutectic solder ball on top of a high lead solder ball |
US6414396B1 (en) | 2000-01-24 | 2002-07-02 | Amkor Technology, Inc. | Package for stacked integrated circuits |
US6444921B1 (en) | 2000-02-03 | 2002-09-03 | Fujitsu Limited | Reduced stress and zero stress interposers for integrated-circuit chips, multichip substrates, and the like |
JP2001223323A (en) * | 2000-02-10 | 2001-08-17 | Mitsubishi Electric Corp | Semiconductor device |
US6544837B1 (en) | 2000-03-17 | 2003-04-08 | International Business Machines Corporation | SOI stacked DRAM logic |
JP3631956B2 (en) | 2000-05-12 | 2005-03-23 | 富士通株式会社 | Semiconductor chip mounting method |
AU2001273424A1 (en) * | 2000-07-18 | 2002-01-30 | Intel Corporation | Flip-chip mounted integrated optic receivers and transmitters |
US6627998B1 (en) * | 2000-07-27 | 2003-09-30 | International Business Machines Corporation | Wafer scale thin film package |
US6600173B2 (en) | 2000-08-30 | 2003-07-29 | Cornell Research Foundation, Inc. | Low temperature semiconductor layering and three-dimensional electronic circuits using the layering |
US6355501B1 (en) | 2000-09-21 | 2002-03-12 | International Business Machines Corporation | Three-dimensional chip stacking assembly |
JP3822043B2 (en) * | 2000-09-25 | 2006-09-13 | 太陽誘電株式会社 | Chip part assembly manufacturing method |
US6498073B2 (en) * | 2001-01-02 | 2002-12-24 | Honeywell International Inc. | Back illuminated imager with enhanced UV to near IR sensitivity |
US6707591B2 (en) | 2001-04-10 | 2004-03-16 | Silicon Light Machines | Angled illumination for a single order light modulator based projection system |
US6748994B2 (en) * | 2001-04-11 | 2004-06-15 | Avery Dennison Corporation | Label applicator, method and label therefor |
US6747781B2 (en) | 2001-06-25 | 2004-06-08 | Silicon Light Machines, Inc. | Method, apparatus, and diffuser for reducing laser speckle |
US6782205B2 (en) | 2001-06-25 | 2004-08-24 | Silicon Light Machines | Method and apparatus for dynamic equalization in wavelength division multiplexing |
US6829092B2 (en) | 2001-08-15 | 2004-12-07 | Silicon Light Machines, Inc. | Blazed grating light valve |
US7109571B1 (en) | 2001-12-03 | 2006-09-19 | National Semiconductor Corporation | Method of forming a hermetic seal for silicon die with metal feed through structure |
US6677235B1 (en) * | 2001-12-03 | 2004-01-13 | National Semiconductor Corporation | Silicon die with metal feed through structure |
US6599778B2 (en) * | 2001-12-19 | 2003-07-29 | International Business Machines Corporation | Chip and wafer integration process using vertical connections |
US6800238B1 (en) | 2002-01-15 | 2004-10-05 | Silicon Light Machines, Inc. | Method for domain patterning in low coercive field ferroelectrics |
EP2560199B1 (en) * | 2002-04-05 | 2016-08-03 | STMicroelectronics S.r.l. | Process for manufacturing a through insulated interconnection in a body of semiconductor material |
US6642081B1 (en) * | 2002-04-11 | 2003-11-04 | Robert Patti | Interlocking conductor method for bonding wafers to produce stacked integrated circuits |
US6759309B2 (en) * | 2002-05-28 | 2004-07-06 | Applied Materials, Inc. | Micromachined structures including glass vias with internal conductive layers anodically bonded to silicon-containing substrates |
US6728023B1 (en) | 2002-05-28 | 2004-04-27 | Silicon Light Machines | Optical device arrays with optimized image resolution |
US6767751B2 (en) | 2002-05-28 | 2004-07-27 | Silicon Light Machines, Inc. | Integrated driver process flow |
US6822797B1 (en) | 2002-05-31 | 2004-11-23 | Silicon Light Machines, Inc. | Light modulator structure for producing high-contrast operation using zero-order light |
US6829258B1 (en) | 2002-06-26 | 2004-12-07 | Silicon Light Machines, Inc. | Rapidly tunable external cavity laser |
US6813059B2 (en) | 2002-06-28 | 2004-11-02 | Silicon Light Machines, Inc. | Reduced formation of asperities in contact micro-structures |
US6716737B2 (en) * | 2002-07-29 | 2004-04-06 | Hewlett-Packard Development Company, L.P. | Method of forming a through-substrate interconnect |
WO2004015764A2 (en) | 2002-08-08 | 2004-02-19 | Leedy Glenn J | Vertical system integration |
US6801354B1 (en) | 2002-08-20 | 2004-10-05 | Silicon Light Machines, Inc. | 2-D diffraction grating for substantially eliminating polarization dependent losses |
US6712480B1 (en) | 2002-09-27 | 2004-03-30 | Silicon Light Machines | Controlled curvature of stressed micro-structures |
JP3828473B2 (en) * | 2002-09-30 | 2006-10-04 | 株式会社東芝 | Multilayer semiconductor device and manufacturing method thereof |
US20040104454A1 (en) * | 2002-10-10 | 2004-06-03 | Rohm Co., Ltd. | Semiconductor device and method of producing the same |
JP3908146B2 (en) * | 2002-10-28 | 2007-04-25 | シャープ株式会社 | Semiconductor device and stacked semiconductor device |
FR2848724B1 (en) * | 2002-12-13 | 2005-04-15 | St Microelectronics Sa | BONDED CONNECTIONS IN AN INTEGRATED CIRCUIT SUBSTRATE |
DE60235267D1 (en) * | 2002-12-20 | 2010-03-18 | Ibm | METHOD OF MANUFACTURING A THREE-DIMENSIONAL DEVICE |
US6806997B1 (en) | 2003-02-28 | 2004-10-19 | Silicon Light Machines, Inc. | Patterned diffractive light modulator ribbon for PDL reduction |
US6829077B1 (en) | 2003-02-28 | 2004-12-07 | Silicon Light Machines, Inc. | Diffractive light modulator with dynamically rotatable diffraction plane |
JP2004327910A (en) * | 2003-04-28 | 2004-11-18 | Sharp Corp | Semiconductor device and its manufacturing method |
JP4016340B2 (en) * | 2003-06-13 | 2007-12-05 | ソニー株式会社 | Semiconductor device, mounting structure thereof, and manufacturing method thereof |
US6838332B1 (en) * | 2003-08-15 | 2005-01-04 | Freescale Semiconductor, Inc. | Method for forming a semiconductor device having electrical contact from opposite sides |
US7183654B2 (en) * | 2003-09-30 | 2007-02-27 | Intel Corporation | Providing a via with an increased via contact area |
US7005388B1 (en) | 2003-12-04 | 2006-02-28 | National Semiconductor Corporation | Method of forming through-the-wafer metal interconnect structures |
DE102004016145A1 (en) * | 2004-04-01 | 2005-10-20 | Infineon Technologies Ag | Semiconductor chip, has connection contacts electrically connected with its surfaces at back side or top side of redistribution layer utilizing press contacts, where layer is located on main side |
US7091604B2 (en) * | 2004-06-04 | 2006-08-15 | Cabot Microelectronics Corporation | Three dimensional integrated circuits |
JP4773697B2 (en) * | 2004-06-30 | 2011-09-14 | ルネサスエレクトロニクス株式会社 | SOI substrate, method of manufacturing the same, and semiconductor device |
US7109068B2 (en) * | 2004-08-31 | 2006-09-19 | Micron Technology, Inc. | Through-substrate interconnect fabrication methods |
US7326629B2 (en) * | 2004-09-10 | 2008-02-05 | Agency For Science, Technology And Research | Method of stacking thin substrates by transfer bonding |
JP4153932B2 (en) * | 2004-09-24 | 2008-09-24 | 株式会社東芝 | Semiconductor device and manufacturing method of semiconductor device |
JP2006114732A (en) * | 2004-10-15 | 2006-04-27 | Renesas Technology Corp | Semiconductor device, manufacturing method thereof, and semiconductor module |
US20060171556A1 (en) * | 2004-12-17 | 2006-08-03 | Galaxy Audio, Inc. | Cooling structure for loudspeaker driver |
FR2880189B1 (en) * | 2004-12-24 | 2007-03-30 | Tracit Technologies Sa | METHOD FOR DEFERRING A CIRCUIT ON A MASS PLAN |
US7714451B2 (en) * | 2005-02-18 | 2010-05-11 | Stats Chippac Ltd. | Semiconductor package system with thermal die bonding |
US7547917B2 (en) * | 2005-04-06 | 2009-06-16 | International Business Machines Corporation | Inverted multilayer semiconductor device assembly |
US7622313B2 (en) * | 2005-07-29 | 2009-11-24 | Freescale Semiconductor, Inc. | Fabrication of three dimensional integrated circuit employing multiple die panels |
US7429529B2 (en) * | 2005-08-05 | 2008-09-30 | Farnworth Warren M | Methods of forming through-wafer interconnects and structures resulting therefrom |
US7517798B2 (en) | 2005-09-01 | 2009-04-14 | Micron Technology, Inc. | Methods for forming through-wafer interconnects and structures resulting therefrom |
US20070090156A1 (en) * | 2005-10-25 | 2007-04-26 | Ramanathan Lakshmi N | Method for forming solder contacts on mounted substrates |
US7684224B2 (en) * | 2006-03-31 | 2010-03-23 | International Business Machines Corporation | Structure comprising 3-dimensional integrated circuit architecture, circuit structure, and instructions for fabrication thereof |
US7408798B2 (en) * | 2006-03-31 | 2008-08-05 | International Business Machines Corporation | 3-dimensional integrated circuit architecture, structure and method for fabrication thereof |
US7462509B2 (en) * | 2006-05-16 | 2008-12-09 | International Business Machines Corporation | Dual-sided chip attached modules |
US20070279885A1 (en) * | 2006-05-31 | 2007-12-06 | Basavanhally Nagesh R | Backages with buried electrical feedthroughs |
US7723224B2 (en) * | 2006-06-14 | 2010-05-25 | Freescale Semiconductor, Inc. | Microelectronic assembly with back side metallization and method for forming the same |
US7829438B2 (en) * | 2006-10-10 | 2010-11-09 | Tessera, Inc. | Edge connect wafer level stacking |
US8513789B2 (en) | 2006-10-10 | 2013-08-20 | Tessera, Inc. | Edge connect wafer level stacking with leads extending along edges |
US7901989B2 (en) * | 2006-10-10 | 2011-03-08 | Tessera, Inc. | Reconstituted wafer level stacking |
US7952195B2 (en) * | 2006-12-28 | 2011-05-31 | Tessera, Inc. | Stacked packages with bridging traces |
FR2910704A1 (en) * | 2007-04-05 | 2008-06-27 | Commissariat Energie Atomique | Interconnected integrated circuit device e.g. dynamic D flip-flop, forming method for electronic component, involves forming set of interconnection layers connected to semiconductor device and another set of layers, on active layer surface |
DE102007034306B3 (en) * | 2007-07-24 | 2009-04-02 | Austriamicrosystems Ag | Semiconductor substrate with via and method for producing a semiconductor substrate with via |
KR101458538B1 (en) | 2007-07-27 | 2014-11-07 | 테세라, 인코포레이티드 | A stacked microelectronic unit, and method of fabrication thereof |
CN101861646B (en) | 2007-08-03 | 2015-03-18 | 泰塞拉公司 | Stack packages using reconstituted wafers |
US8043895B2 (en) | 2007-08-09 | 2011-10-25 | Tessera, Inc. | Method of fabricating stacked assembly including plurality of stacked microelectronic elements |
US20090070550A1 (en) * | 2007-09-12 | 2009-03-12 | Solomon Research Llc | Operational dynamics of three dimensional intelligent system on a chip |
US8136071B2 (en) * | 2007-09-12 | 2012-03-13 | Neal Solomon | Three dimensional integrated circuits and methods of fabrication |
KR101477690B1 (en) * | 2008-04-03 | 2014-12-30 | 삼성전자주식회사 | Non-volatile memory device, method of fabricating the same |
US8680662B2 (en) * | 2008-06-16 | 2014-03-25 | Tessera, Inc. | Wafer level edge stacking |
DE102008033395B3 (en) | 2008-07-16 | 2010-02-04 | Austriamicrosystems Ag | Method for producing a semiconductor component and semiconductor component |
US8129256B2 (en) * | 2008-08-19 | 2012-03-06 | International Business Machines Corporation | 3D integrated circuit device fabrication with precisely controllable substrate removal |
US8399336B2 (en) | 2008-08-19 | 2013-03-19 | International Business Machines Corporation | Method for fabricating a 3D integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layer |
US8298914B2 (en) | 2008-08-19 | 2012-10-30 | International Business Machines Corporation | 3D integrated circuit device fabrication using interface wafer as permanent carrier |
US8513119B2 (en) | 2008-12-10 | 2013-08-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming bump structure having tapered sidewalls for stacked dies |
US20100171197A1 (en) * | 2009-01-05 | 2010-07-08 | Hung-Pin Chang | Isolation Structure for Stacked Dies |
US8198172B2 (en) * | 2009-02-25 | 2012-06-12 | Micron Technology, Inc. | Methods of forming integrated circuits using donor and acceptor substrates |
EP2406821A2 (en) * | 2009-03-13 | 2012-01-18 | Tessera, Inc. | Stacked microelectronic assemblies having vias extending through bond pads |
US8791549B2 (en) * | 2009-09-22 | 2014-07-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer backside interconnect structure connected to TSVs |
US8114707B2 (en) * | 2010-03-25 | 2012-02-14 | International Business Machines Corporation | Method of forming a multi-chip stacked structure including a thin interposer chip having a face-to-back bonding with another chip |
US8466059B2 (en) | 2010-03-30 | 2013-06-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-layer interconnect structure for stacked dies |
US9831164B2 (en) * | 2010-06-28 | 2017-11-28 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
US8970043B2 (en) | 2011-02-01 | 2015-03-03 | Maxim Integrated Products, Inc. | Bonded stacked wafers and methods of electroplating bonded stacked wafers |
US8536701B2 (en) * | 2011-05-03 | 2013-09-17 | Industrial Technology Research Institute | Electronic device packaging structure |
US8900994B2 (en) | 2011-06-09 | 2014-12-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for producing a protective structure |
US9947688B2 (en) * | 2011-06-22 | 2018-04-17 | Psemi Corporation | Integrated circuits with components on both sides of a selected substrate and methods of fabrication |
US9196671B2 (en) | 2012-11-02 | 2015-11-24 | International Business Machines Corporation | Integrated decoupling capacitor utilizing through-silicon via |
US20170186731A1 (en) * | 2015-12-23 | 2017-06-29 | Sandisk Technologies Llc | Solid state drive optimized for wafers |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0168815A2 (en) * | 1984-07-20 | 1986-01-22 | Nec Corporation | Process for fabricating three-dimensional semiconductor device |
EP0238089A2 (en) * | 1986-03-20 | 1987-09-23 | Fujitsu Limited | Three-dimensional integrated circuit and manufacturing method therefor |
JPH04280456A (en) * | 1991-03-08 | 1992-10-06 | Fujitsu Ltd | Semiconductor device and its manufacture |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL158024B (en) * | 1967-05-13 | 1978-09-15 | Philips Nv | PROCESS FOR THE MANUFACTURE OF A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE OBTAINED BY APPLYING THE PROCEDURE. |
US3623219A (en) * | 1969-10-22 | 1971-11-30 | Rca Corp | Method for isolating semiconductor devices from a wafer of semiconducting material |
US4022927A (en) * | 1975-06-30 | 1977-05-10 | International Business Machines Corporation | Methods for forming thick self-supporting masks |
US4423435A (en) * | 1980-10-27 | 1983-12-27 | Texas Instruments Incorporated | Assembly of an electronic device on an insulative substrate |
JPS62214624A (en) * | 1986-03-17 | 1987-09-21 | Fujitsu Ltd | Manufacture of semiconductor device |
JPS63308386A (en) * | 1987-01-30 | 1988-12-15 | Sony Corp | Semiconductor device and manufacture thereof |
US5279991A (en) * | 1992-05-15 | 1994-01-18 | Irvine Sensors Corporation | Method for fabricating stacks of IC chips by segmenting a larger stack |
US5244817A (en) * | 1992-08-03 | 1993-09-14 | Eastman Kodak Company | Method of making backside illuminated image sensors |
-
1993
- 1993-01-21 US US08/006,601 patent/US5426072A/en not_active Expired - Lifetime
-
1994
- 1994-01-10 JP JP6517067A patent/JPH07506936A/en active Pending
- 1994-01-10 WO PCT/US1994/000363 patent/WO1994017553A1/en not_active Application Discontinuation
- 1994-01-10 EP EP94906589A patent/EP0631692A1/en not_active Withdrawn
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0168815A2 (en) * | 1984-07-20 | 1986-01-22 | Nec Corporation | Process for fabricating three-dimensional semiconductor device |
EP0238089A2 (en) * | 1986-03-20 | 1987-09-23 | Fujitsu Limited | Three-dimensional integrated circuit and manufacturing method therefor |
JPH04280456A (en) * | 1991-03-08 | 1992-10-06 | Fujitsu Ltd | Semiconductor device and its manufacture |
Non-Patent Citations (2)
Title |
---|
HAYASHI ET AL: "Fabrication of three-dimensional IC using "Cumulatively Bonded IC" (CUBIC) technology", 1990 SYMPOSIUM ON VLSI TECHNOLOGY, 4 June 1990 (1990-06-04), HONOLULU,USA, pages 95 - 96, XP000164428 * |
PATENT ABSTRACTS OF JAPAN vol. 17, no. 85 (E - 1322) 19 February 1992 (1992-02-19) * |
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0942466A4 (en) * | 1997-04-11 | 2003-01-02 | Toshiba Kk | Process for manufacturing semiconductor device and semiconductor component |
EP0942466A1 (en) * | 1997-04-11 | 1999-09-15 | Kabushiki Kaisha Toshiba | Process for manufacturing semiconductor device and semiconductor component |
DE19842441B4 (en) * | 1998-02-26 | 2004-07-29 | Mitsubishi Denki K.K. | Semiconductor component and method for its production |
US6459125B2 (en) | 1998-02-26 | 2002-10-01 | Mitsubishi Denki Kabushiki Kaisha | SOI based transistor inside an insulation layer with conductive bump on the insulation layer |
FR2775387A1 (en) * | 1998-02-26 | 1999-08-27 | Mitsubishi Electric Corp | SEMICONDUCTOR DEVICE HAVING SELF STRUCTURE AND MANUFACTURING METHOD |
WO2000031796A1 (en) * | 1998-11-20 | 2000-06-02 | Giesecke & Devrient Gmbh | Method for producing an integrated circuit processed on both sides |
US6583030B1 (en) | 1998-11-20 | 2003-06-24 | Giesecke & Devrient Gmbh | Method for producing an integrated circuit processed on both sides |
WO2007131867A1 (en) * | 2006-05-16 | 2007-11-22 | International Business Machines Corporation | Dual wired integrated circuit chips |
US7381627B2 (en) | 2006-05-16 | 2008-06-03 | International Business Machines Corporation | Dual wired integrated circuit chips |
US7939914B2 (en) | 2006-05-16 | 2011-05-10 | International Business Machines Corporation | Dual wired integrated circuit chips |
US7960245B2 (en) | 2006-05-16 | 2011-06-14 | International Business Machines Corporation | Dual wired integrated circuit chips |
EP2186128A1 (en) * | 2007-08-10 | 2010-05-19 | Agency For Science, Technology And Research (A*star) | Nano-interconnects for atomic and molecular scale circuits |
EP2186128A4 (en) * | 2007-08-10 | 2012-01-04 | Agency Science Tech & Res | Nano-interconnects for atomic and molecular scale circuits |
US8420530B2 (en) | 2007-08-10 | 2013-04-16 | Agency For Science, Technology And Research | Nano-interconnects for atomic and molecular scale circuits |
Also Published As
Publication number | Publication date |
---|---|
US5426072A (en) | 1995-06-20 |
JPH07506936A (en) | 1995-07-27 |
EP0631692A1 (en) | 1995-01-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5426072A (en) | Process of manufacturing a three dimensional integrated circuit from stacked SOI wafers using a temporary silicon substrate | |
US11710729B2 (en) | Wafer bonding in fabrication of 3-dimensional NOR memory circuits | |
JP2654332B2 (en) | SOI integrated circuit and method of forming the same | |
JP2974211B2 (en) | SOI semiconductor device | |
US5087585A (en) | Method of stacking semiconductor substrates for fabrication of three-dimensional integrated circuit | |
US6291858B1 (en) | Multistack 3-dimensional high density semiconductor device and method for fabrication | |
EP0182032B1 (en) | SoI semiconductor device and method for producing it | |
KR100915534B1 (en) | Three Dimensional CMOS Integrated Circuits Having Device Layers Built On Diffrent Crystal Oriented Wafers | |
EP0168815B1 (en) | Process for fabricating three-dimensional semiconductor device | |
US4870475A (en) | Semiconductor device and method of manufacturing the same | |
US20050029592A1 (en) | Method and structure for buried circuits and devices | |
JPH07508614A (en) | Membrane insulation layer separation IC manufacturing | |
US6096621A (en) | Polysilicon filled trench isolation structure for soi integrated circuits | |
JPH077144A (en) | Soi transistor and forming method therefor | |
US4851366A (en) | Method for providing dielectrically isolated circuit | |
US5633190A (en) | Semiconductor device and method for making the same | |
JPH07506937A (en) | Thermally matched readout/detector structure and its fabrication method | |
US5844294A (en) | Semiconductor substrate with SOI structure | |
US5907783A (en) | Method of fabricating silicon-on-insulator substrate | |
US5589419A (en) | Process for fabricating semiconductor device having a multilevel interconnection | |
EP0469583A2 (en) | Semiconductor substrate with complete dielectric isolation structure and method of making the same | |
JPH0817177B2 (en) | Semiconductor device | |
US20060255389A1 (en) | Semiconductor device with decoupling capacitor and method of fabricating the same | |
JP2839088B2 (en) | Semiconductor device | |
EP0525256A1 (en) | Method of fabricating isolated device regions |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): JP |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): AT BE CH DE DK ES FR GB GR IE IT LU MC NL PT SE |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1994906589 Country of ref document: EP |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWP | Wipo information: published in national office |
Ref document number: 1994906589 Country of ref document: EP |
|
WWW | Wipo information: withdrawn in national office |
Ref document number: 1994906589 Country of ref document: EP |