WO1994010794A1

WO1994010794A1 - Control system for projection displays

Info

Publication number: WO1994010794A1
Application number: PCT/US1993/010701
Authority: WO
Inventors: Matthew Zavracky
Original assignee: Kopin Corporation
Priority date: 1992-11-04
Filing date: 1993-11-04
Publication date: 1994-05-11

Abstract

A control apparatus for an active matrix liquid crystal display device is fabricated with the active matrix as a single integrated SOI circuit. The control apparatus and the active matrix are lifted from a silicon substrate and transferred to a glass substrate as a single piece. The control apparatus comprises a video interface, a column driver, and dual select line drivers. The video interface operates the active matrix as a multiple-frequency scanning display device. The column driver comprises dual shift register arrays, one array coupled to the even columns and the other array coupled to the odd columns. The even and odd columns operate at opposite polarities. The respective polarities are reversed on every frame by a polarity switch. The control apparatus further comprises sensors for generating a gray-scale feedback signal to adjust the amplifier gain. The sensors comprise a temperature sensor within the active matrix and a light sensor measuring light transmission through the liquid crystal material.

Description

CONTROL SYSTEM FOR PROJECTION DISPLAYS

Background of the Invention

Flat-panel displays are being developed which utilize liquid crystals or electroluminescent materials to produce high quality images. These displays are expected to supplant cathode ray tube (CRT) technology and provide a more highly defined television picture or computer monitor image. The most promising route to large scale high quality liquid crystal displays

(LCDs) , for example, is the active-matrix approach in which thin-film transistors (TFTs) are co-located with LCD pixels. The primary advantage of the active matrix approach using TFTs is the elimination of cross-talk between pixels, and the excellent grey scale that can be attained with TFT-compatible LCDs.

Flat panel displays employing LCDs generally include five different layers: a white light source, a first polarizing filter that is mounted on one side of a circuit panel on which the TFTs are arrayed to form pixels, a filter plate containing at least three primary colors arranged into pixels, and finally a second polarizing filter. A volume between the circuit panel and the filter plate is filled with a liquid crystal material. This material will rotate the polarization of light when an electric field is applied across the material between the circuit panel and a ground affixed to the filter plate. Thus, when a particular pixel of the display is turned on, the liquid crystal material rotates polarized light being transmitted through the material so that the light will pass through the second polarizing filter. The primary approach to TFT formation over the large areas required for flat panel displays has involved the use of amorphous silicon, which has previously been developed for large-area photovoltaic devices. Although the TFT approach has proven to be feasible, the use of amorphous silicon compromises certain aspects of the panel performance. For example, amorphous silicon TFTs lack the frequency response needed for large area displays due to the low electron mobility inherent in amorphous material. Thus the use of amorphous silicon limits display speed, and is also unsuitable for the fast logic needed to drive the display.

Owing to the limitations of amorphous silicon, other alternative materials include polycrystalline silicon, or laser recrystallized silicon. These materials are limited as they use silicon that is already on glass, which generally restricts further circuit processing to low temperatures. A continuing need exists for systems and methods of controlling pixel of panel displays having the desired speed and providing for ease, and reduced cost, of fabrication.

Summary of the Invention A preferred embodiment of the present invention relates to projection display devices (i.e. monitors and image projectors) including methods of fabricating such devices using thin films of single crystal silicon in which a light valve matrix (or matrices) is formed for controlling images produced by these devices. In accordance with the present invention, projection display devices employing high density single crystal silicon light valve matrices provide high resolution images compatible with 35 mm optics.

In one preferred embodiment, an optically transmissive substrate is positioned to receive light from a back-light source and a light valve matrix is secured to the substrate. In accordance with the present invention, the light valve matrix includes an array of transistors and an array of electrodes. The light valve matrix also includes an adjacent light transmitting material, through which light from the back-light source is selectively transmitted. Preferred embodiments are directed to light valves employing a transmissive light transmitting material such as liquid crystal or a ferroelectric material, although other transmissive materials may be used. Each light valve includes a transistor, an electrode and a portion of the adjacent light transmitting material. Each transistor, by application of an electric field or signal, serves to control the optical transmission of light through the adjacent light transmitting material for a single light valve.

A driver circuit is electrically connected to the light valve matrix to selectively actuate the light valves. The drive circuitry may be formed in the same thin-film material in which the transistors and electrodes have been formed. The drive circuitry is capable of being fully interconnected to the light valve matrix using thin-film metallization techniques without the need for wires and wirebonding. An optical system is also provided for projecting light transmitted through the actuated light valves onto a large viewing surface. The present devices and related methods for fabricating projectors satisfy the requirements of large screen television or monitor displays for producing highly defined color images. To that end, a projection display device can have multiple light valves each adapted to selectively transmit light of a single primary color. Further, a dichroic prism may be provided for combining the single color light transmitted by each light valve producing a multi-color light image which is projected onto a large viewing surface.

Other preferred embodiments of the present invention relate to an active matrix slide adapted for use in a conventional 35 mm slide projector for providing monochrome or multi-color images. The active matrix is mounted within a slide frame, which is fabricated to have equivalent physical dimensions as a standard 35 mm photographic slide having an image that can be projected by a slide projector. In accordance with the present invention, an active matrix slide assembly, being packaged to be size equivalent with a standard 35 mm slide, is insertible into a slide projector for generating the projected images. An electronics unit is connected to the active matrix and controls image generation by the active matrix. In preferred embodiments, the active matrix is capable of generating monochrome or multi-color images.

In one preferred embodiment of the invention, an active matrix display unit is adapted for use with a slide projector having a projector body, a light source, an optical system, and a projection chamber in which a 35 mm slide can be placed for projection of a fixed photographic image onto an external viewing surface. The display unit includes a housing and an active matrix slide assembly movably mounted to the housing. As such, the slide assembly has a storage position and an operating position. The housing is positioned on the slide projector body such that the slide assembly, being moved into the operating position, can be securely disposed in the projection chamber for selectively transmitting light from the light source to provide images for projection by the slide projector optics.

The housing preferably contains a shielded electronics assembly which is electrically connected to the active matrix for controlling image generation. The electronics assembly receives image data from an image generation device which can be a computer or any video source. Image data provided by the image generation device is processed by the electronics and sent to the active matrix. Responsive to the received data, the individual active matrix light valves are actuated such that illuminating light from the light source is selectively transmitted through the active matrix to form monochrome or multi-color images.

In another preferred embodiment, the active matrix display unit includes an active matrix slide assembly and a remote electronics housing. The active matrix slide assembly is dimensioned to be securely positioned in the projection chamber of the slide projector and is electrically connected to electronics in the remote housing by a cable. In yet another preferred embodiment, the active matrix display unit includes an active matrix that is not physically connected to the electronics housing. Instead, the active matrix and the electronics in the housing communicate with each other via antenna elements such as RF antennas or infrared transmitter/detector elements.

As with aforementioned embodiments, an active matrix has an array of pixels or light valves that are individually actuated by a drive circuit. The drive circuit components can be positioned adjacent to the array and electrically connected to the light valves. As such, the individual light valves are actuated by the drive circuit so illuminating light is selectively transmitted through the slide to form an image.

A preferred control apparatus is fabricated with the active matrix as a monolithic SOI structure. After the SOI structure is fabricated in a thin film layer of single crystal or substantially single crystal silicon on a silicon substrate, the structure is removed from the silicon substrate using a lift-off process and transferred to a glass substrate as a single substrate. The single structure provides improved processing speeds and the fabrication process reduces the difficulty and cost of manufacturing display panels. In a particular preferred embodiment, the display panel is adapted for use in a standard 35mm slide projector. In a preferred embodiment, a control apparatus for a liquid crystal display device comprises a video interface, a left select scanner, a right select scanner, a video polarity network, a data scanner, and a transmission gate. The video interface converts video signals from a video source into active matrix control signals. In response to the active matrix control signals, the left and right select scanners simultaneously drive opposite sides of the matrix select lines. The video polarity network inverts the polarity of the video signals on each successive video frame. A preferred embodiment employs either column inversion or frame inversion techniques. In particular, a column inversion technique is used where the polarity of the even columns is opposite to the polarity of the odd columns on any given video frame. In response to the active matrix control signals, the data scanner triggers the transmission gate to drive the active matrix columns with the even and the odd column signals.

The data scanner comprises an odd-column shift register array and an even-column shift register array. The odd column array triggering an odd column array of the transmission gate and the even column array triggering an even column array of the transmission gate. The odd and even column arrays of the transmission gate drive respective columns of the active matrix.

An encoder may be coupled between the video source and the video polarity network. The encoder generating a superposed analog video signal from a video source Red-Green-Blue (RGB) data- signal. The RGB data signal can be mapped to a superposed color analog signal. The RGB data signal can also be mapped to a gray-scale analog signal. Preferably, the encoder can map to either of the color or gray-scale signal in response to a control signal.

In a preferred embodiment, the control apparatus adjusts the gray-scale video signal level to compensate for changes in the transmittance of the liquid crystal material. At least one sensor is fabricated within the SOI structure. A temperature sensor can be used to generate a data signal in response to the temperature of the active matrix. A light sensor can be used to generate a data signal in response to the light transmittance of the liquid crystal material. The sensor can include at least one real-time light sensor at least one real-time temperature sensor, or a combination of light sensors and temperature sensors. The sensor data is processed by a light meter or temperature measurer, which generates a feedback signal in response to the sensor data. An amplifier gain is adjusted by the feedback signal, the amplifier amplifying the video signal by the gain. The gain may be linear or nonlinear.

If light sensors are used, a light transmittance curve for the liquid crystal material must be established. A light sensor is provided that generates a signal representing light transmittance through a black pixel. Another light sensor is provided that generates a signal representing light transmittance through a white pixel. The black and white pixel signals can be generated by permanently connecting one pixel light sensor to a DC voltage and the other pixel light sensor to ground. The black and white pixel light sensors define the end points of the active matrix transmittance curve. In a preferred embodiment, the video source generates a video signal having variable synchronization frequencies. The active matrix display has a fixed pixel resolution. The video interface generates a dot clock signal from the variable synchronization frequencies for driving the display at the fixed resolution. The video interface allows the display panel to function as a multiple-frequency scanning display device. The video interface comprises a control processor and dot clock regenerator. The control processor is responsive to video mode changes on the video signal as reflected by changes in the synchronization signals. In response to mode changes, the control processor signals the dot clock regenerator. The dot clock regenerator is responsive to the control processor signal. The dot clock regenerator comprises a digitally programmable phase-locked loop that tracks changes on the synchronization frequencies such that the dot clock signal is centered over the correct pixel and does not drift. The video interface providing compatibility with Video Graphics Array (VGA) adapter and Apple™ video signals.

Brief Description of the Drawings

The above and other features of the invention, including various novel details of construction and combination of parts, will now be more particularly described with reference to the accompanying drawings and pointed out in the claims. It will be understood that the particular control system for slide projector mountable display panels embodying the invention is shown by way of illustration only and not as a limitation of the invention. The principles and features of this invention may be employed in varied and numerous embodiments without departing from the scope of the invention.

FIGS. 1A-D illustrate a preferred embodiment of the light valve housing with the light valve display panel assembly retracted. FIGS. 2A-B illustrate a preferred embodiment of the light valve housing with the light valve display panel assembly extended.

FIG. 3 is an exploded view of a preferred embodiment of a display unit.

FIGS. 4A-B are sectional views of a preferred light valve display unit mounted on a standard slide projector.

FIGS. 5A-C are perspective views of the light valve slide frame 210 of FIG. 3.

FIG. 5D is a partial schematic cross sectional view of a mounted display panel 250 taken along lines I-I of FIGS. 5A-C.

FIG. 6A is an exploded view of remote control units.

FIG. 6B is a view of the underside of the button insert 320 of FIG. 5A.

FIG. 7 illustrates a preferred embodiment of the housing with an attached remote control unit. FIG. 8 is a schematic block diagram of a preferred embodiment of a control system.

FIGs. 9A-9D illustrate preferred video signal connections to a computer video source.

FIGs. 10A-10C are schematic block diagrams of a preferred video interface 110 of FIG. 1.

FIG. 11 is a schematic block diagram of a preferred video polarity network 150 of FIG. 8.

FIG. 12 is a view of a display panel showing a preferred temperature sensor arrangement. FIGs. 13A-13C are views of a display panel showing a preferred light sensor arrangement. FIGs. 14A-14H illustrate a preferred processed flow sequence illustrating the fabrication of a transmissive active matrix display with a sensor.

FIG. 15 is a partial cross-sectional view of a preferred active matrix display panel.

FIG. 16 is a partial cross-sectional view of a preferred active matrix display panel illustrating a preferred shielding approach.

FIG. 17 is a flowchart of the processing steps of the control processor of FIG. 10A.

FIGs. 18A-18B are timing diagrams for driving the active matrix 90.

FIGs. 19A-19B are timing diagrams for a particular preferred embodiment of the invention.

Detailed Description of a Preferred Embodiment of the Invention

FIGS. 1A-D illustrate external feature of a slide projector mountable light valve display housing 100 according to a preferred embodiment of the invention. The housing 100 is adapted to be mounted to a commercially available slide projector. Commercially available slide projectors are available from Vivatar, Kodak, Agfa, and other manufacturers. A particular preferred embodiment of the invention will be described in relation to a Kodak carousel slide projector. It being understood that other slide projectors can be used with minor structural changes to the housing 100.

FIG. IA is a right-side perspective view of a preferred embodiment of a slide projector mountable light valve slide housing 100. Illustrated is the housing body 110, a top control panel 112, a base 141, and a manual release access door 150. An infrared receiving element 114 is visible on the housing body 110. The control panel 112 contains a plurality of raised buttons 181 and a power indicator 183, such as an LED. The housing base 141 contains a frame tab channel 146 and a mounting lip 148. The housing 100 is ergonomically designed for an average human hand. FIG. IB illustrates a bottom plan view of the housing 100. A spindle mount 145 registers to the center hub of a slide projector. After the spindle mount 145 is mounted on the center hub, the housing 100 is rotated into position on the slide projector. A spindle tab cutout 147 and clip 146 are adjacent to the spindle mount 145 and registers to a spindle tab on the projector spindle. Once the housing 100 has been rotated into position, the mounting lip 148 registers to the slide projector housing. The mounting lip 148 also contains a mounting slot 149, which registers to a remote control unit (discussed below) . Also shown is an opening to a slide channel 143 through which a light valve slide extends and retracts. The clip secures the housing to the center hub, once the housing 100 has been rotated into position. A remote control release 170 registers to the remote control unit. The clip 146 acts as a spring acting against the remote control release 170.

FIG. IC is a rear view of the housing 100. Registered to the housing body 110 is an external interface plate 160 and the remote control release 170. The external interface plate 160 contains a power connector cutout 162 and a video signal connector cutout 164. FIG. ID is a top plan view of the housing 100. Shown are the elevated control buttons 181 and the power indicator 183. The control buttons allow the user to control brightness 181a, 181b, contrast 18lc, 181d, and tuning 181e, 181f (i.e., pixel centering). A graphics/text button 181g allows the user to switch between graphics and text displays on an MS-DOS computer. Frame buttons 18lj, ... ,181m allow the user to shift the display up, left, right and down, respectively, by whole pixel increments. A save button 18lh saves the current setting for the current video mode. A reset button 181i returns the settings to factory default settings. Details of the control button function are discussed below. Each control panel button 181 is formed from a rubberized button insert (not shown) , which is registered to a control panel contact pad insert (not shown) .

FIG. 2A is a front plan view of the housing 100 with a light valve slide assembly 200 in the extended position. Located behind the access door 150 is a handle slot 105 (shown in phantom) . A slide handle 220 (shown in phantom) extends through the handle slot 105 and moves relative to the handle slot 105 as the light valve slide assembly 200 is moved within the housing 100.

FIG. 2B is a right-side plan view of the housing 100 with the light valve slide assembly 200 in the extended position. FIG. 3 is an exploded view of a preferred display unit. A housing base 140 contains much of the structural elements of the housing 100. In particular, a front superstructure 142 a slide channel 143 for the light valve slide assembly 200 and provides structural support for the front of the housing 100. In addition, a rear superstructure 144 is mounted to the topside of the spindle mount 145 to provide structural support for the rear of the housing 100. The light valve slide assembly 200 moves freely through the slide channel 143. A latch holder 120 registers to the slide channel 143. The latch holder 120 includes a latch mechanism 125. The latch mechanism 125 meets with a latch tab 225 of a light valve slide frame 210. When the light valve slide assembly 200 is fully retracted into the housing 100, the latch mechanism 125 secures the latch tab 225 so the light valve slide assembly 200 is fixed to the housing in the retracted position. The latch mechanism 125 is of a type that releases the latch tab 225 when an upward pressure is placed on the light valve slide assembly 200. After being released, the light valve slide assembly 200 descends through the slide channel 143. Preferably, the light valve slide assembly 200 is gravity fed.

During operation, it is possible that the light valve slide assembly 200 may jam while extended into the projection chamber 16. For that reason, the slide handle 220 can be accessed through the manual release access door 150, which is mounted to the housing body 110 by hinges 152a, 152b. ^' By using the slide handle 220, a user can manually raise or lower the light valve slide assembly 200. A light valve display panel 250 is coupled to video control circuitry 132, 134. As illustrated in FIG. 3, the video control circuitry is provided by a digital circuit board 132 and analog circuit board 134. In particular, the analog circuit board 134 is a daughter board connected to the digital circuit board 132. These circuit boards 132, 134 are adapted to fit within the housing 100. The analog circuit board 134 receives power from an external power source and analog video signals from an external video source through power cutout 162 and video connector cutout 16 , respectively. Preferably, the video source is a computer that generates video images. The video source can generate a composite video signal. The analog circuit board 134 also receives user control signals from the control panel 12 and the remote control unit 300. The digital circuit board 132 performs digital processing of the video signal. The drive signals for the light valves are provided by the analog circuit board 134 over a ribbon cable 135.

FIG. 4A illustrates the housing 100 properly aligned in the locked position with the light valve slide assembly 200 aligned directly above the projection chamber 716 of the projector 710. Once positioned and locked, the light valve slide assembly 200 is ready to be lowered into the projection chamber 716. By advancing the slide projector, the ejector arm 712 is raised such that the slide bumper 715 contacts the light valve slide 200. The upward motion of the ejector arm 712 urges the light valve slide assembly 200 vertically upward causing the latch mechanism 125 to disengage the latch tab 225. After being released from the latch mechanism 125, the light valve slide assembly 200 is supported by the slide bumper 713. The ejector arm 712 then continues to cycle downward to lower the light valve slide assembly 200 into the projection chamber 716. The light valve slide assembly 200 is secured by spring clips 717 in the projection chamber 716. Because of friction between the light valve slide assembly 200 and the slide channel 143, the light valve slide assembly may drop into the projection chamber 716 after the ejector arm 712 has finished the ejection cycle. On the next ejection cycle, the light valve slide assembly 200 will be forced upward by the ejector arm 712 to be secured by the latch mechanism 125. FIG. 4B illustrates the light valve slide assembly 200 positioned and retained in the projection chamber 716 of a slide projector 710, such that light 1101 from a light source (not shown) passes through the light valve 250 and is projected onto a viewing surface by a projection lens 711. While the light valve slide assembly 200 is positioned in the projection chamber 716, the light valve and associated circuitry are exposed to heat from the projector light source. Adequate ventilation must be provided to reduce the exposure of the light valve to excessive heat.

Ventilation is preferably provided through the underside of the housing 100. Cool air 700 is drawn into the projection chamber 716 by a circulating fan (not shown) of the slide projector. The cool air 700 is drawn through a ventilation channel 259 of the light valve slide assembly 200. Warm exhaust air 750 exits the ventilation channel 259 and is expelled by the projector circulating fan. The physical character¬ istics of the ventilation channel 259 will be discussed in more detail below.

Critical features of the construction of the light valve slide assembly 200 are illustrated in FIGS. 5A-5C, which are perspective views of the light valve slide frame 210 of FIG. 3. The slide frame 210 comprises two main structural features. The main structural element is the display holder 210a shown in FIGS. 5A-5B. The second main structural element is the display cover 210b, which is illustrated in FIG. 5C. As will be described in detail below, the display holder 210a and the display cover 210b are sandwiched together with a light valve display panel 250 disposed between the two elements. FIG. 5A is a perspective view of the light-source side of the display holder 210a. Illustrated are a front rail 212 and a rear rail 214. The rails 212, 214 register to corresponding rail slots in the slide channel 143. The rails 212, 214 and the rail slots cooperate to allow and facilitate movement of the light valve slide assembly 200 into and out of the housing 100 while inhibiting twisting or lateral motion of the light valve slide assembly 200. The handle 220 is fastened to the front rail 212. Also illustrated are a front stop 216 and a rear stop 218. These stops work in conjunction with the rails 212, 214. A polarizer area 251 is defined between the stops 216, 218. The polarizer area 251 is registered to the display aperture 255a. The polarizer area 251 is spatially displaced from the viewing aperture 255a such that a ventilation channel is formed between the polarizer area 251 and the viewing aperture 255a. A polarizer 252 is supported by ledges 217, 218 of the stops 216, 218. Further support for the polarizer 252 can be provided by spacer support 215. There may be fewer or more spacer supports 215 than illustrated in FIG. 5A. Finally, a plurality of recessed fastening apertures 291 are shown for receiving a fastener, such as a bolt. FIG. 5B is a perspective view of the backside of the display holder 210a of FIG. 5A. In particular, note the signal cable feed through ports 201, 203. The signal cable from the analog circuit board 134 is fed through the upper feed through port 201 and through the lower feed through port 203 to connect to a light valve display. Note that each fastening hole has a fastening support 293.

FIG. 5C is a perspective view of a display cover 210b. Again, note the upper feed through port 201 and the lower feed through port 203. The display cover 210b has formed therein a display panel area 253. The liquid crystal display panel 250 registers to the display panel area 253 such that when the display cover is fastened to the display holder 210a, the light valve display panel is fixedly aligned with the view aperture 255. Fastening nuts 295 are intrically formed in the display cover 210b.

In a preferred embodiment of the invention, both the display holder 210a and the display cover 210b are fabricated from zinc. Zinc is chosen because of suitability to casting. Other materials may be substituted instead of zinc. However, the materials of the light valve slide frame 210 should be compatible with the materials used to form the slide channel 143 of the display housing 100. In particular, the coefficient of friction between the two materials should be low enough so that the light valve slide 200 can freely descend and ascend through the slide channel 143. In a preferred embodiment of the invention, the slide channel 143, as well as the housing 100, is fabricated from injection molded plastic.

FIG. 5D is a cross-sectional view of a mounted display panel 250 taken along section lines I-I of FIGS. 5A-5C. The display panel 250 is sandwiched between the display holder 210a and the display cover 210b. In a preferred embodiment, the display panel 250 is an active matrix liquid crystal display. It is understood that the display panel 250 could be a passive matrix liquid crystal display, or another suitable light transmissive light valve display. Note the ventilation channel 259 formed between the polarizer 252 and the active matrix 250.

FIG. 6A is an exploded perspective view of a remote control device 300 for use in controlling the displayed image.

Typically, the remote control unit 300 is defined by an upper shell 310 and a lower shell 340. The upper shell 310 contains a plurality of voids 312, 314, 316 through which control buttons 322, cursor control button 324, and mouse select buttons 326 are accessed, respectively. The buttons 322, 324, 326 are preferably rubberized buttons molded onto a rubberized button insert 320. The buttons 322, 324, 326 are registered to contact pads 332, 334, 336 on a circuit board 330. In response to user inputs through the control buttons 322, 324, 326, an infrared signal is generated by LED 339. The infrared signal transmits the user's selections to housing 100.

The remote 300 is preferably powered by batteries 350 installed within a battery chamber in the lower segment 340 and secured therein by a battery door 345. The batteries preferably provide three-volts to the circuit board 330. It being understood that alternate battery configuration can be utilized instead, such as a nine-volt battery.

FIG. 6B is a view of the underside of the rubberized button insert 320. Each button 322, 324, 326 has at least one button contact protrusion for depressing an associated contact pad 332, 334, 336. Each control button 322 has a single button contact protrusion 333. Each mouse select button 326 has three redundant button contact protrusions 327. The mouse select buttons 326 preferably emulates standard Microsoft or Apple mouse select buttons. The functions of the select buttons 326 can be programmed to differ from standard mouse select buttons. For example, the right select button 326b can function as a drag-lock. The cursor control button 324 provides for eight-way cursor movement. There are, however, only four cursor control contact pads 334 to provide the eight-way cursor movement.

In a preferred embodiment, the cursor control button 324 has eight button contact protrusions 325. The cursor control contact protrusions 325 are paired with respective contact pads 334 such that a user selection of left, right, up or down results in a redundant depression of the respective contact pad 334. Each pair of cursor control contact protrusions are further positioned such that a diagonal user selection results in the depression of the two contact pads 334 adjacent to the diagonal direction. A processing unit interprets the depression of adjacent contact pads 334 as a diagonal cursor movement.

In another preferred embodiment, the cursor control button 324 is a plastic cap (such as a rigid disk or ring) , which is registered to four directional buttons. Each directional button is registered to a respective cursor control contact pad 334. As pressure is placed on an area of the plastic cap, at least one directional button is depressed to contact a cursor control contact pad 334. If the depressed area of the plastic cap is about midway between two adjacent directional buttons, then both adjacent directional buttons are depressed. Processing similar to that discussed above, interprets this as a diagonal cursor movement.

In other preferred embodiments, cursor control is provided through a trackball or joystick dimensioned for use with the remote control 300 of course discrete cursor control keys can also be used with the remote control 300.

The remote control buttons 322 perform the same functions as the control panel buttons 181.

FIG. 7 is a right side view of the housing 100 with an attached remote control unit 300. The remote control device 300 registers to the base 141 of the housing 100, such that the remote control device 300 attaches to and stores underneath the housing 100 when the light valve slide 200 is in the upward position. In particular, a mounting tab 318 registers to the mounting slot 149 of the housing 100. The remote control device 300 is disengaged from the housing 100 by depressing the remote control release 170 on the housing 100.

A preferred embodiment of a control system is shown in FIG. 8. A video signal source (not shown) provides video signals to an active matrix display device (shown in phantom) . The video signal source can be any analog or digital video signal source including a Video Graphics Array (VGA) adaptor, the Apple™ Macintosh™ family of computers, a National Television Systems Committee (NTSC) composite video source, a high-resolution professional display adapter, a Charge- Coupled-Device (CCD) , or other similar sources. In a particular preferred embodiment, the active matrix display device is adapted as a computer-controlled light valve that substitutes for a positive photographic slide in a standard 35mm slide projector.

Horizontal and vertical synchronization signals from the video signal source are provided to a video interface 410 on data lines 13 and 14, respectively. Red-Green-Blue (RGB) video signal components, if supplied by the video signal source, are provided to an encoder 440 on respective data lines 1, 2, 3. If discrete color (e.g., RGB) signals are not supplied by the video source, then a single encoded video signal 41 (e.g., NTSC composite video signal) must be supplied by the video source. The appropriate video signal is supplied to a video polarity network 450 on data line 441, the operation of which is described in greater detail below.

An active matrix display 90 (shown in phantom) operates as a multi-frequency display device. Typically, video signals from the video signal source will not be synchronized to a fixed frequency. A change in the video mode can change the resolution of the data, measured in pixels. For example, a VGA adaptor generates synchronization signals that vary depending on the particular video mode in which the adaptor is operating. A standard VGA adaptor can generate a vertical synchronization frequency between about 56 and 70 Hz and a horizontal synchronization frequency between about 15 and 35 Khz. For professional display purposes (e.g., CAD/CAM) the vertical and horizontal synchronization frequency can be higher than described. To handle current high resolution display applications, the display device can preferably adapt to vertical synchronization frequencies up to about 100 Hz and horizontal synchronization frequencies up to about 66 Khz. In addition, a change in the video mode can also invert the polarities of the synchronization signals. Consequently, a preferred embodiment of the invention adapts to changes in the synchronization signals caused by changes in the video mode.

The video interface 410 is used to interface the active matrix display device with the horizontal and vertical synchronization signals from the video signal source. In a preferred embodiment, the video interface 410 interfaces with a standard VGA display adapter to display the video image at a horizontal resolution of 640 pixels and a vertical resolution of 480 pixels (64OH x 480V) . In another preferred embodiment, the display resolution is 1024H x 768V. In yet another preferred embodiment, the display resolution is 2048H x 2048V. The video interface 410 adjusts to changes in the input synchronization frequencies by detecting polarity, frequency, or phase changes in the input signals.

A preferred embodiment of the invention for use with video signals for a VGA adaptor supports 720H x 400V text mode, 640H x 480V graphics mode, 640H x 400V graphics mode and 640H x 350V graphics mode. Table I summarizes video rates and resolutions associated with these supported VGA modes. It will be understood that other video modes having different video rates and resolutions can be supported as well, with minor modifications.

TABLE I TYPICAL VGA RATES AND RESOLUTIONS

Connection to a VGA adapter is through a traditional 15-pin, 3 row connector. The pin connections for the VGA receptacle are illustrated in FIG. 9A. Table II defines the pinouts for a typical VGA adapter. Table III lists the pinouts for the receptacle in FIG. 9A. Video signals are carried on pins 1, 2, 3, 5, 6, 7, 8, 10, 13 and 14. These pins are identical between the VGA connection and the control system connection. Pin 9 is used by a preferred embodiment of the invention as an EIA mouse out signal line. Pin 9 together with the equipment ground (pin 5) are provided to a mouse port on the receiving computer through an appropriate connector. In addition, pin 15 is used to receive a Mac detect signal to help detect Apple machines. FIG. 9B is a schematic diagram illustrating a VGA to video control system cable. Note that the computer end has two connections: a 15-pin, 3-row plug for the video information, and an appropriate plug for the mouse connector. To connect to a standard COM port, a 9-pin DSUB plug connector is used as the mouse connector.

TABLE II VGA PINOUTS

TABLE III CONTROL SYSTEM PINOUTS

A preferred embodiment of the invention for use with Apple™ MAC-II computers, including the Powerbook™ series, supports 64OH x 480V resolution. In particular, the computer is informed that the active matrix display 90 is a 13-inch, 640H x 480V Apple™ monitor. This does not imply that the same video timing is used on all Apple™ computers. If the correct timing cannot be determined, differences may manifest as centering offsets, which can be adjusted to zero. Table IV summarizes video rates and resolutions associated with an Apple™ MAC-II computer.

TABLE IV TYPICAL MAC-II RATES AND RESOLUTIONS

Connection to an Apple MAC-II computer is through a 15-pin, 2 row connector. The Macintosh video connector is illustrated in FIG. 9C. The Macintosh video pinout definitions are provided in Table V. The video control system pin definitions are the same as defined in Table III. FIG. 9D is a schematic diagram illustrating a Macintosh computer to video control system cable.

Table V MAC PINOUTS

Preferably, a preferred embodiment of the invention also supports the Apple™ MAC-LC video family. The MAC-LC computer can generate signals to drive either a 13-inch 640H x 480V Apple™ monitor or a VGA monitor, using a special monitor adaptor available from Apple Computer, Inc. When connected directly to the MAC-LC computer, the video control system functions as a 13-inch 64OH x 480V Apple™ monitor. When the monitor adaptor is installed, the video control system receives quasi-VGA signals. The video control system detects the actual video mode sent by the computer. Unfortunately, the timing of the Apple™ quasi-VGA signal is not identical to the VGA specification. This timing difference results in the horizontal centering being four pixels off, which can be adjusted using centering controls. Table VII summarizes video rates and resolutions associated with an Apple™ MAC-LC product.

TABLE VI

TYPICAL MAC-LC RATES AND RESOLUTIONS

Video signal from the appropriate video connector are fed to the video control system. FIGs. 10A-₁0C are block diagrams of a preferred video interface 110 for VGA signals.

Referring to FIG. 10A, horizontal and vertical synchronization signals are provided at TTL levels on respective incoming data lines 13, 14 from a VGA adapter or similar video source. A control processor 412 examines the incoming video stream and tracks mode changes, which provide for variable frequency multi- scanning capability. Upon detecting a mode change, the control processor 412 signals the mode change to a dot clock regenerator 414 over data line 416. Optionally, the control processor 412 interprets input signals from a remote control device over a remote signal line 31 and either controls hardware or provides remote mouse functionality over a mouse signal line 9 to the computer, as required. Preferably, a non-volatile Editable Erasable Programmable Read-Only Memory (EEPROM) is used to store setup and adjustment parameters. The program for the processor is contained within a Erasable Programmable Read-Only Memory (EPROM) which simplifies upgrading the functionality of the program. Most digital logic is contained within Field Programmable Gate Arrays (FPGAs) , which are also programmed from the same EPROM. Upgrading the EPROM allows functionality to be changed, added or repaired, all with little manufacturing cost. The dot clock regenerator 414 provides a pixel data signal on line 411, a pixel clock signal on line 413, a frame switch signal on line 415, a select clock signal on line 417, and a select data signal on line 419.

As illustrated in FIG. 10B, the dot clock regenerator 114 recreates the pixel dot clock used by a computer to output pixels. The regeneration must be accurately controlled because it is very important to provide a clock that is centered over each pixel and does not drift. Thus, a clock must be recreated that can be used to sample a pixel and move to the next pixel. The dot clock regenerator 414 includes a phase locked loop (PLL) network 414a and Voltage Controlled Oscillator (VCO) 414b. The PLL 414a and VCO 414b are responsive to the mode change signal over data line 416. There is no standard for the frequency of the incoming video signal, which can range from 20 Mhz to over 30 Mhz, depending on the source.

An analog RGB signal is not quantizied because CRTs do not require the analog signal to have a notion of screen position. Unlike CRTs, flat panel displays have quantizied pixels. Hence, the analog RGB signal must be quantizied to each pixel. For the quantization to be accurate, each scan line of the analog RGB signal must be divided into discrete values. That task is performed by the dot clock regenerator 414. As summarized in Table I, the VGA 640H x 480V modes include 800 pixels per horizontal scan. Unfortunately, only one timing signal (i^'.e. , the horizontal sync) is received per scan line. Thus, the PLL 414a must operate with a divider multiplication ratio of 800:1. Typical phase-lock loop circuits become unstable at divider multiplication ratios over about 8:1. PixelVision, Inc. of Acton, Massachusetts manufactures and sells video processing circuitry containing a preferred dot clock regenerator 414, under Part Nos. PV-CIFK-xxxx. Other suitable dot clock regenerators

414 may be available from other sources. The dot clock regenerator 414 preferably permits a user to fine tune the position of the reconstructed dot clock, through the control processor 412.

Although the active matrix 90 is an analog device, video signals must be "massaged" before being presented to the active matrix 90. In general, the video signal is to be presented to the active matrix 90 through two inputs, each a mirror of the other. Both signals are to be biased on a nine-volt reference, with the video having a six volt, peak-to-peak swing. At least 50 Mhz 0 bandwidth must be maintained, into a 100 pf load. The voltages and currents required in this particular embodiment are detailed in Table VII.

TABLE VII

FIG. 10C is a schematic block diagram of the logic drive 460 for the active matrix 90. Overall, the logic drive 460 receives common logic level inputs, preferably CMOS or TTL and translates them to the drive levels required by the active matrix 90.

A tracking regulator 466 provides a DC voltage approximately two volts higher than the panel voltage supply to the active matrix 90. The panel voltage itself is adjustable, to allow operation with different 0 liquid crystal types. The tracking regulator 466 is a small linear regulator, with an emitter follower output to supply the needed current.

A horizontal logic drive 463 provides the synchronizing pulse (i.e., pixel data 411) and clock (i.e., pixel clock 413) for the horizontal axis of the active matrix 90. This is the fast axis, where the video data is clocked into the display. A MOSFET driver is used, to provide the needed fifteen-volt logic swing into the 30 pF load at speeds commensurate with a maximum pixel rate (e.g., 31.5 Mhz). The clock is half the pixel rate, with each edge being used to enter pixels. Another reason for the output voltages to quickly reach near the panel voltage, or ground, is to limit power dissipation in the active matrix circuitry. This is especially important for the clock, because the edge rate is high. Another reason for fast edge rates is sampling jitter; slow edges lead to timing uncertainty. To increase the positive-going edge rate, the voltage from the tracking regulator 166 is used to provide some overdrive. In the negative- going direction there is already overdrive, because the negative panel supply is a nominal three volts.

With the overdrive from the driver, there would be some danger of overloading the input clamp to the active matrix 90. This is prevented by, first, including a small current limiting resistor 467a, 467b in series with each output. There is also a diode clamp 468a, 468b to the panel voltage. The current limiting resistor 467 together with the diode clamp 468 prevents the input clamp to the active matrix 90 from being overly stressed.

A vertical logic drive 462 provides the synchronizing pulse (i.e., select data 419) and clock(s) (i.e., select clock 417) for the vertical axis of the active matrix 90. This is the slow axis, where a clocking edge occurs every scanline. A MOSFET driver is used here, as with the horizontal axis, except without overdrive.

Returning to FIG. 8, the video interface 410 converts the synchronization signals from the video signal source into pixel timing information for the pixel columns and select line timing information for the pixel rows of the active matrix. The video interface 410 provides control registers to adjust and delay the pixel clock 413, pixel data 411, select clock 417, and select data 419 so the image generated by the video source (e.g. VGA) can be precisely mapped to the active matrix 90 pixel resolution (e.g., 640H x 480V). The video interface 410 provides a pixel data signal and a pixel clock signal to a data scanner 420 on respective data lines 411,413. The video interface 410 also provides a select line data signal and a select line clock signal to select scanners 432,436 on respective data lines 417,419. Preferred embodiments of the invention supply one or four clocks on each clock signal line 413,417. By supplying four clock signals on each clock signal line 413,417, the circuitry of the scanners 420,430 can be simplified. This is especially important if the scanners 420,430 are fabricated on the SOI structure with the active matrix 90 and the video interface 410 is a discrete component. Finally, the video interface 410 provides a frame switch signal to the video polarity network 450 on data line 415.

Encoder 440 may be a gray-scale encoder or a color encoder. The RGB signal is provided from the pinout connectors on signal lines 1,2,3. The encoder converts the RGB signal into a mapped analog signal. A gray-scale encoder employs a colored mapper to convert the RGB signal into a gray-scale equivalent. In a preferred embodiment, each color from the RGB signal is weighted and then summed together to form a gray-scale signal. The gray-scale mapper uses the equation

V₀ = w_RV_R + w_GV_G + w_BV_B , ( 1 )

where V₀ is the gray-scale output signal; w_R, w_G, and w_B are the respective weighting for the red, green and blue signals; and V_R, V_G, and V_B are the respective signal strengths for the red, green and blue signals. In a preferred embodiment of the invention, w_R=0.3, w_G=0.59 and w_B=0.ll to result in a weighting function approximately equal to the human eye's relative response. However, other weighting values can be obtained by changing resistor values in the circuit. If the video source supplies a monochrome signal, that signal is preferably applied at the green input 2. In addition, other mapping techniques may be employed without affecting the scope of the invention (e.g., digital mapping) . A color encoder employs a multiplexer to multiplex the RGB signal into a mixed color equivalent. In a preferred embodiment, the encoder 440 provides either one of gray-scale or color encoding, as required. The encoded analog signal from either the gray-scale mapper or color encoder is provided to the video polarity network 450 via an encoder line 441. In a further embodiment, the video source can provide an NTSC composite video signal on signal line 423. In an NTSC composite video signal, the RGB signals and the synchronization signals are superposed as a single analog video signal. Because the RGB signals are already encoded in a NTSC composite video signal, no separate encoding is necessary. Instead, the superposed RGB data is extracted from the NTSC composite video signal. The superposed RGB data from an NTSC composite video source is provided to the video polarity network 450 on line 441.

The video polarity network 450 generates odd and even video driven signals 459 from the frame switch data on line 415 and the analog video signal on line 441. The video drive signal 459 is adjusted by a contrast control signal 51, a back porch clamp signal 53, a brightness control signal 55, the liquid crystal reference voltage 461, and feedback signals 473, 483 from a temperature measurer 470 or light meter 480. As shown in FIG. 11, the video polarity network 450 incorporates a video amplifier 452, bias network 454, a video switch 456, drive amplifiers 458 and a DC level control servo 455.

The analog video signal from line 441 is provided to the video amplifier 452. The video input 441 is amplified by an amount determined by the contrast (gain) control voltage 51 generated by a digital-to-analog (D/A) converter 50. Because the video input is AC coupled, the DC restore function is done by a back porch clamp (not shown) . The Brightness (level) control 55 is the reference voltage for the clamp which is obtained from the D/A converter.50. The feedback for the clamp is taken from the main video outputs, which closes the loop around the full video path. In a preferred embodiment, this block is implemented by a National Semiconductor LM1201 amplifier, although other suitable amplifiers can be used.

One important feature is that there are two complementary outputs from the video amplifier 452. The normal output 453b is positive-white from a (clamped) level a few volts above ground. The inverted output 453a is negative-white from a few volts below the positive supply voltage (12V) . These two outputs 453a, 453b are inherently in phase, and have the same gain because they are preferably taken from the same output transistor. Alternatively, the amplifier gain can be nonlinear (e.g., gamma functions). The normal and inverted amplifier signals 453a, 453b are fed to a bias network 454.

The bias network 454 is an RC network that biases the two outputs of the video amplified 452 toward each other. Those outputs can never reach the same voltage, due to the nature of the output stage. But the inputs to the drive amplifiers 458 should be capable of crossing over in some cases, to allow a full range of contrast and brightness adjustment. The output signals from the bias network 454 are fed to the video polarity switch 456.

To provide the AC component of the required active matrix drive signal, video switches select either the normal or the inverted video signals. These video signals are supplied alternately to an odd drive amplifier 458a, with an even drive amplifier 458b receiving the opposite signal. Preferably, the switches change every video field (every vertical sync) . The switch could occur more or less often, as might be desirable for crosstalk or other purposes; a preferred switching rate allows switching every scanline. The switches used are FET-based "T" switches, which provide good isolation and fairly low "on" resistance. A switch is also used to select between the outputs, to always provide a "normal" feedback signal for clamping comparison. The video polarity switch 456 is synchronized to the frame rate provided over the frame switch line 415.

In a preferred embodiment, a column inversion technique is used to reduce crosstalk between select lines to reduce or avoid the production of a DC offset voltage. The video switch 456 provides an alternating opposite polarity for the column pixels. The even column pixels are operated at the opposite polarity of the odd column pixels. The polarities of the column pixels are switched on each sequential frame. For example, on one frame even column pixels operate at a positive polarity and odd column pixels operate at a negative polarity. On the next sequential frame, the switch 456 switches the polarities of the odd and even columns. As a result, the even column pixels operate at a negative polarity and the odd column pixels operate at a positive polarity. The odd column polarity is provided to the active matrix on line 459b and the even column polarity is provided to the active matrix on line 459a.

Another preferred embodiment of the invention uses a frame inversion technique instead of column inversion. Using frame inversion, each column during any one frame has the same polarity. On alternating frames, as clocked by the frame switch 415, the polarity of each column is reversed. In that way, the polarity of the entire active matrix 90 is inverted on each successive frame. Note that this frame inversion embodiment would not require the use of distinct odd and even data registers 422.

The video drive to the active matrix 90 is preferably implemented with current feedback operational amplifiers 458. These amplifiers 458 can drive the high load capacitance while remaining stable and retaining adequate frequency response. Two amplifiers 458a,458b are provided, for the odd and even pixel inputs of the active matrix 90. Both inputs receive the full video signal, with correct pixel data selected by the clock inputs discussed above. The operational amplifiers 458 are used in a non-inverting configuration, with the feedback networks referenced to the output of the DC-level control servo 455. There is a small output resistor, to limit peaking and overshoot. Alternatively, an RC snubber can be coupled to ground. The nominal gain of this stage is preferably 2.3.

The DC level control^'servo 455 adjusts the operating level of the drive amplifiers 458 so there is a minimal overall DC voltage applied across the liquid crystal material. A significant DC voltage could damage the liquid crystal material. A regulated LCD voltage 461 is supplied to the servo 455 as a center reference voltage of the liquid crystal material. The servo 455 filters the two video outputs 459, to establish their average level. The difference between this average and the reference voltage is integrated, with the result providing a feedback voltage for the drive amplifiers 458. Thus, the loop is closed, and drives to "zero" error. The integrator output stage has a discrete emitter follower to handle the current required by the drive amplifiers 458. With fixed 1% resistors, the residual error should be less than 100 V. With a potentiometer as well, as used in a preferred embodiment, the DC level error can be further adjusted as needed.

Returning to FIG. 8, the data scanner 420 provides for double storage of pixel data. The data scanner 420 interfaces with the pixel data signal on line 411 and the pixel clock signal on line 413 via interface component 425. The data scanner 420 uses an odd shift register array 422a and an even shift register array 422b to store data for each scan. The odd shift register array 422a stores data to odd column pixels and the even shift register array 422b stores data to even column pixels. To facilitate fabrication testing, an odd test pad 424a is fabricated on the odd shift register array 422a and an even test pad 424b is fabricated on the even shift register array 422b.

A transmission gate 428 transmits pixel actuation signals to the active matrix 90. The transmission gate 428 is partitioned into odd column gate 428a and even column gate 428b, which are registered to respective columns of the data scanner shift registers 422a,422b. A serial data stream of a video drive signal is provided to the odd and even column pixels on respective signal lines 459a,459b. An appropriate signal level is transmitted by the transmission gate 428 to the correct pixel as triggered by the output from the shift registers 422.

To reduce signal loss across the active matrix, the select lines are driven from both sides by select scanners 430. As viewed in FIG. 8, left select scanner 430a and right select scanner 430b are connected to the select data line 419 and the select clock line 417. The left select scanner 430a provides a select line signal at the end of the select line nearest the lowest-valued pixel column (C,) and right select scanner 430b provides a select line signal at the end of the select line nearest the highest-valued pixel column (C_N) . Thus, an identical select line signal is supplied at both ends of the select line. To facilitate fabrication testing, a left scanner test pad 434a is fabricated on the left select scanner 430a and a right scanner test pad 434b is fabricated on the right select scanner 430b. The shift registers of the data scanner 420 and the select scanners 430 are dynamic shift registers. The dynamic shift registers rely on capacitor storage without leakage. However, dynamic shift registers are susceptible to leakage, especially when they are exposed to light. Hence, light shields are needed to protect the scanners 420,430 from exposure to light. In a further preferred embodiment, at least one sensor 92, 94 is integrated into the active matrix 90 for gray-scale adjustments. The sensor may be a temperature diode, a photo transistor or diode, or combinations thereof. A preferred embodiment employs at least one temperature sensor 92 and at least one light sensor 94. The signals from the sensors provide feedback signals, to the video polarity network 450. In response to the feedback signal, the video amplifier 452 adjusts the gray-scale signal strength. In a preferred embodiment, the sensors 92,94 are uniformly distributed throughout the active matrix. For example, each pixel element, or a selected group of pixel elements can have an associated sensor 92,94. The sensor to pixel ratio need not be one-to-one however. In another material embodiment, the sensors 92,94 are distributed around the perimeter of the active matrix.

FIG. 12 shows a preferred temperature sensor arrangement. The active matrix 90 comprises a plurality of pixels 1000 arranged in columns and rows. Ideally, heat will be absorbed substantially uniformly throughout the liquid crystal material. Thus, only one temperature sensor 92 is necessary to measure the temperature of the active matrix 90. However, there will be local temperature variations due to the nature of the image being displayed. In addition, a plurality of temperature sensors can be used to provide redundancy. In the figure, temperature sensors 92 are distributed throughout the active matrix region 90. As shown, temperature sensors 92 are distributed around the perimeter of the active matrix 90. In particular, the temperature sensors 92 are located at corner pixels 1000 of the active matrix 90. In addition, a temperature sensor 92 is disposed near the center of the active matrix 90. Of course, more or less temperature sensors 90 may be used.

FIG. 13A shows a preferred light sensor arrangement. Light sensors are used to construct a transmittance curve for the liquid crystal material. The light sensors 94 are distributed around the active matrix region 90. In addition, there are sensors 941 to indicate a permanently dark pixel reading. There are also sensors 942 that represent permanently white pixel readings. The permanent readings are provided by either connecting the sensors 94 to either a DC supply voltage or to ground. The permanent-valued sensors 941,942 map the end points of the liquid crystal material's transmittance curve. The light sensor 94 measures the transmission of light through the liquid crystal material in real time. The transmittance of the liquid crystal material varies with the temperature of the material.

FIG. 13B-13C are partial cross-sectional views of the display area having a light sensor 94. Because all light between the polarizes 252a,252b is polarized, a light sensor 94 located within the active matrix 90 cannot measure changes in the transmission of light through the liquid crystal material. To measure changes in the intensity of light, the light transmitted through the liquid crystal material 1081 must be measured after exiting the second polarizer 252b. Although a light sensor may be mounted outside the second polarizer 252b, a preferred embodiment of the invention fabricates the light sensor 94 as part of the SOI circuit 1058. In both figures, the light sensor 94 is located outside of the active matrix region 90.

A preferred embodiment is shown in FIG. 13B. A reflector 1210 is mounted on a mechanical frame 1200. The reflector 1210 is inclined such that light that has passed through the liquid crystal material 1081 is reflected toward the light sensor 94. Light sensor 94 only measures relative change in light transmission. Therefore, only a minute quantity of light, such as collateral light, needs to be reflected toward the sensor 94.

An alternative embodiment is shown in FIG. 13C, where an aperture 1290 is provided through the mechanical frame 1200. The incident light 1101 enters the structure through the aperture 1290 and passes through the liquid crystal material 1081. After passing through the liquid crystal material 1081, the light 1101 is reflected by a reflector 1220 mounted on the mechanical frame 1200. The reflected light is thus reflected back to the light sensor 94, where the light intensity is measured. Although the light does not pass through the active matrix region 90, the transmittance can be calculated because the temperature of the liquid crystal material is essentially constant throughout. Therefore, the measurement by light sensor 94 is sufficiently accurate to determine the liquid crystal's relative position on the transmittance curve. FIGs. 14A-14H illustrates a preferred fabrication process for fabricating the sensors 92,94 into the active matrix. Referring to FIG. 14A, an SOI structure includes a silicon substrate 1041 and an insulating oxide layer 1043 (such as, for example, one micron of Si0₂) that is grown or deposited on the substrate 1041. A thin (i.e. 0.3 micron) single crystal layer 1045 of silicon is formed over the oxide 1043. The oxide is thus buried beneath the silicon surface layer, such that higher speed devices can be fabricated. However, it is noted that any number of techniques can be employed to provide a thin film of single crystal silicon. As shown in FIG. 14B, the film 1045 is patterned into islands to define each pixel elements 1047. As explained below, the pixel elements are then processed to form a transistor, an electrode, and sensors 92,94. To that end, the pixel elements are masked (not shown) and subjected to deep and shallow implants to form an n-well region 1049 (FIG. 14C) . Another masked is formed over the pixel elements, and the elements are subjected to deep and shallow implants to form an p- well region 1051.

Referring to FIG. 14D, an Si0₂ layer 1053 having a thickness on the order of 0.07 micron is formed over each silicon island 1047. A layer of polysilicon having a thickness of about 0.5 micron is formed on the oxide layer 1053, doped to provide an n+ region and patterned to form a transistor gate 1055 and a diode junction 945 (FIG. 14E) . Another oxide layer 1057 having a thickness of about 0.07 micron is formed over the polysilicon. The pixel elements 1047 are masked (not shown) and doped with 2*10¹⁵ of phosphorous to provide an n+ source/drain implantation' (FIG. 14F) . After the mask is removed, the pixel elements are again masked and doped with 4*10¹⁵ of boron to provide a p+ source/drain implantation. As such, a transistor 1054, a pixel electrode 1065, and a sensor 92, 94 have been formed for pixel element 1047.

A portion 1059 of the oxide layer is then removed to form a contact for the transistor 1054. Referring to FIG. 14G, a metallization deposition is then performed to form a layer 1061 over the transistor 1054. The layer can comprise aluminum and has a thickness of about one micron. The layer 1061 serves as a pixel light shield as well as a contact for the transistor 1054.

Referring to FIG. 14H, the entire pixel can be coated with a thin (about 0.15 micron) layer of silicon nitride (not shown) . Next, a layer of amorphous silicon having a thickness of about 0.5 micron is deposited over each pixel element. The layer is then patterned to provide a matrix of black elements 1067, each black element associated with a transistor. A color filter element 1069 may be formed over the pixel electrode 1065. The color filter elements can be formed by processing an emulsion or a photoresist carrier, or by processing conventional filter materials. The individual color filter elements can be processed to provide an arrangement of three or four different color pixel elements in any of the previously described geometries.

FIG. 15 shows a partial cross sectional view of a preferred active matrix display device. The display device comprises polarizers 252a,252b, cover glass 1087, glass substrate 1056, counter electrode 1085, and liquid crystal 1081. Integrated into the active matrix is a monolithic integrated circuit 400. In a preferred embodiment, the data scanner 420, the transmission gate 426, and the select scanners 430 are integrated onto the integrated circuit 400. In an alternative embodiment, the video interface 410, encoder 440, video polarity switch 450, temperature measurer 460, and light meter 470 are also integrated onto the integrated circuit 400. In addition, a sensor 950 can be integrated into the active matrix adjacent to the pixel electrode 1065. During processing, the wafer having the SOI circuit layer 1058 is attached to a superstrate transfer body 1056, such as glass or other transparent insulator, using an adhesive 1021. Preferably the adhesive 1021 is comprised of an epoxy, such as, a cycloaliphatic anhydride; for example, EP-112 LS made by Masterbond Inc. The adhesive must satisfy the following criteria:

Excellent spectral transmission in the visible range;

Good adhesion to glass, oxides, metals, nitrides; No reactions with glass, metals, oxides, nitrides; Low shrinkage; Low warp/stress; Able to tolerate acids or bases at 100°C for extended periods without lifting, losing adhesion, or degrading; Able to withstand 180°C for 2 hours with no optical change; Good resistance to acids and solvents;

Able to tolerate dicing and heating step

(including an acid etch step with no lifting) ; Low viscosity to allow thin adhesive films; and Ability to be vacuum degassed to eliminate all bubbles.

In general, the cycloaliphatic anhydrides meet most of the above criteria. The epoxy 1021 preferably has a low cure temperature to minimize shrinkage, a very low ion content (<_ 5ppm) and spectral stability over extended time periods. The wafer having the SOI circuit layer 1058 is attached, using the adhesive 1021, to the glass superstrate 1056. The adhesive 1021 is vacuum degassed to eliminate all bubbles. The sandwich structure is then cured at a low temperature of about 100°C for about 4-8 hours which causes the adhesive 1021 to gel and minimizes the shrinkage characteristics. Then the adhesive 1021 is fully cured at a higher temperature of about 160°C for about 8 hours. This cure assures that the bonds are fully matured. Without this cure, the adhesive 1021 will not stand up to subsequent acid etching step.

The water is then cleaned and the native oxide is etched off the back surface. The wafer is put into a solution (KOH or equivalent) of 25 grams to 75 ml H₂0 at 100°C. Depending on the thickness of the wafer, it may take up to 5 hours to etch the Si 1041 and oxide 1043 layers. The solution etches silicon very rapidly, i.e., 2 to 3 microns/min. , and uniformly if the wafers are held horizontally in the solution with the etching surface face up. The etchant has a very low etch rate on oxide, so that as the substrate is etched away and the buried oxide is exposed, the etching rate goes down. The selectivity of the silicon etch rate in KOH versus the oxide etch rate in KOH is very high (200:1). This selectivity, combined with the uniformity of the silicon etching, allows the observer to monitor the process and to stop the etch in the buried oxide layer 1043 without punching through to the thin silicon layer above it. Wafers up to 25 mils thick and oxides as thin as 4000A have been successfully etched using this process. An alternative etchant is hydrazine, which has a much higher etch rate selectively or ethylene diamine pyrocatacol (EDP) .

When the silicon is completely gone, the vigorous bubbling, which is characteristic of silicon etching in KOH, abruptly stops, signalling that the etching is complete.

The thin film 1058 transferred to the respective glass superstrates 1056 is now rinsed and dried. If not already provided with circuits 1047, 400, the films 1058 can be backside circuit processed if desired, because the epoxy adhesive 1021 has very good resistance to chemicals. In addition, the epoxy is very low in stress, so the thin film 1058 is very flat and can go through conventional photolithography steps. For reasons to be explained below, the integrated circuit 400 is connected to the end pixel elements 1047 of each row of pixels by an aluminum interconnect 1400. In a preferred embodiment, the aluminum interconnect 1400 is 750 microns long. Because the integrated circuit 400 comprises dynamic shift registers and other optically sensitive components, the integrated circuit 400 must be shielded from exposure to light 1101. A mechanical frame 1200 functions to shield the integrated circuit 400 from direct exposure to light 1101. The integrated circuit 400 must be formed far enough away from the active matrix region 90 so the mechanical frame 1200 is guaranteed to shield the integrated circuit 400. The distance between the integrated circuit 400 and the active matrix region is dependent on the machined tolerances of the frame 1200 and mounting hole, and the tolerance of the glass size. A distance of about 750- 1000 microns has been found to be sufficient. Because of the relatively large distance between the integrated circuit 400 and the active matrix, an interconnect is required. The interconnect 1400 must also be shielded from incident light 1101. A shield layer 1500 formed by metallization disposition functions to shield substantially all of the interconnect 1400 from incident light 1101. In a preferred embodiment, the shield is formed a black matrix. The black matrix shield 1500 also functions to shield the integrated circuit 400 from exposure to collateral directed incident light.

FIG. 16 is a schematic diagram of a partial pixel array of the active matrix. Generally, four pixel areas 1047 are shown. The silicon material is patterned to form an array of pixel electrodes and each electrode is further patterned into a grid, serpentine, or other suitable geometry to reduce transmission loss through the pixel electrode. The individual pixel electrode 510 initially comprises a solid layer of single crystal silicon. However, the element is processed such that areas 520 of silicon are removed and strips 515 of silicon remain. As such, the resulting pixel electrode 510 resembles a grid. The open areas 520 have a width (Wl) of about 6 microns and the strips have a width (W2) of about 3 microns. In a preferred embodiment, there are four strips 515 and five removed areas 520 on the pixel electrode 510.

The grid provides an aperture through each pixel electrode 510 that improves transmission of light by reducing interference effects and also reducing reflection, absorption, and scattering caused by the pixel material. One advantage of the grid-shaped pixels is the increased light transmission through the active matrix, which results in brighter displayed images. Another advantage is that grid-shaped pixels minimize thickness variations in the single crystal silicon layer. These thickness variations cause light absorption or interference, which reduces the light transmission through the active matrix. By minimizing thickness variations, brighter displayed images can be provided.

FIG. 17 is a flow chart of the processing steps of the control processor 412. The control processor is activated when the power is turned on as step 2000. Control then flows to step 2100, where the control processor performs initializations. These initializations include loading initial data into the FPGAs. Preferably, the initial settings are factory defaults. When configured with a VGA video connector, the factory default setting is 64OH x 480V graphics mode. When configured with a Macintosh™ video connector, the default settings are 64OH x 480V. The initialization procedure 2210 may also include a diagnostic self-test. After initialization is complete, control flows to a loop beginning at step 2200.

At step 2200, a check is performed on the video signal inputs to determine whether a mode change has occurred. If a mode change has occurred, control flows to step 2300. At step 2300, the FPGAs are reconfigured to reflect the current video mode. If there is no mode change at step 2200 or after reconfiguring at step 2300, control flows to step 2400.

At step 2400, a check is performed to determine whether there are any user inputs. If there are user inputs, control flows to step 2500. At step 2500, the user commands are processed. The user inputs can include mouse functions, brightness adjustments, contrast adjustments, tuning adjustments, frame adjustments, configuration saves, configuration resets, and a graphics/text mode selection (VGA modes only) . After the user commands are processed at step 2500, or if there were no user input pending at step 2400, control flows back to the beginning of the loop at step 2200.

The brightness and contrast adjustments are provided to a digital-to-analog converter 50. The digital to analog converter 50 provides the contrast signal on signal line 51 and the brightness signal on signal line 53. The operation of the brightness and contrast adjustments will now be described with reference to FIG. 18A, which illustrates two columns of select data.

The video image is computed relative to a common plane voltage 2510, which is +9 volts in a preferred embodiment of the invention. The video signal 2512, 2518 is bounded by a white level 2511, 2517 and a black level 2513, 2519. As illustrated, the display is a drive-to-black active matrix display. The operation of a drive-to-white active matrix display is similar. The normal signal 2512 is centered about +15 volts with a range from 11.5 volts to 16 volts. The inverted signal 2518 is centered about +3 volts with a range extending from 2.5 volts to 4.5 volts. Contrast is a direct control of the video input amplifier 452. When contrast is increased, the difference between the black signal level and the white signal level is increased such that there is less resolution per video data bit. When contrast is decreased, the difference between the black signal level and the white signal level is decreased such that the resolution per video data bit is increased. Brightness controls the video input stage and determines the overall saturation of the data in a drive-to-black active matrix display. An increase in brightness decreases the difference between the common plane voltage 2510 and the white signal levels 2511, 2519 such that the center voltages are driven nearer to the common plane voltage 2510. A decrease in brightness separates the center voltages further from the common plane voltage 2510. The opposite is true in a drive-to-white active matrix display. The operation of the pixel fine tuning adjustment will be described referring to FIG. 18B. The fine tuning adjustment adjusts the sampling point to provide for a stable, locked display. The analog signal 459 must be aligned with the pixel clock 413 such that the portion of the analog signal representing the pixel value 2520 is centered on the pixel clock 413. The fine tuning adjustment shifts the pixel clock forward or backward in time by fractions of a pixel.

The graphics/text mode switch toggles between graphics and text mode in VGA-based computers. In VGA-based computers, it is impossible to distinguish between text mode (740Hx400V) , which is typically used whenever the user is at a MS-DOS prompt, and the 64OH x 400V graphics mode. The video signals appear identical, although they are not. Unfortunately, the display must be informed of which mode the VGA is operating so data may be sampled correctly. When toggled to text mode, every ninth pixel is dropped so the 720 horizontal pixels can be represented in a 640 pixel display. The graphics/text mode button is only active when operating in either of the two applicable video modes. The frame adjustment moves the display left or right by whole pixels or up and down by one scan line. The delay between scanner data and the horizontal sync and vertical sync signals is changed by the frame adjustment control. In a preferred embodiment of the invention, the available range is +/- 32 pixels horizontally and +/- 75 lines vertically.

The reset command causes the control system to be re-initialized to factory presets. The save command causes the currently active user configuration to be saved for the current video mode.

FIG. 19A is a horizontal signal timing diagram illustrating the pixel clock signal 413, the pixel data signal 411, and the video data signal 459. The pixel clock signal 413 has a clock high width tDCH and a low width tDCL. The pixel data signal 411 has a pulse width tDPW that is triggered by the rising edges of the pixel clock signal 413. The rising edge of the pixel data pulse is delayed a time tHP from a rising edge of the pixel clock signal 413. The falling edge of the pixel data pulse is delayed a time tDP from the next rising edge of the pixel clock signal 413. The pixel data pulses have a horizontal pulse period tHPD. The time from the pixel data pulse to the first data valid is defined as tDV. Table VIII provides horizontal timing parameters. TABLE VIII HORIZONTAL TIMING

FIG. 19B is a vertical signal timing diagram, illustrating the select clock signal 417 and the select data signal 419. The select clock signal 417 has a clock high width tSCH and a clock low width tSCL. Table IX provides vertical timing parameters.

TABLE IX VERTICAL TIMING

Eguivalents

While this invention has been particularly shown and described with reference and preferred embodiments thereof, it will be understood by those skilled in the art that various changes on form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

CLAIMSThe invention claimed is:

1. A control apparatus for an active matrix projection display panel having a plurality of select lines and a plurality column lines, the select lines and column lines forming an active matrix device, comprising: a video interface for receiving video signals from a video source and converting the video signals to signals comprising select line signals; a left select scanner and a right select scanner coupled to the video interface and responsive to the select line signals, the select scanners coupled to respective opposite sides of the active matrix device for generating a select line drive signal on the respective sides of a select line; and a data scanner coupled to the video interface and the columns of the active matrix device for driving the columns to selectively actuate pixel electrodes connected to each select line.

2. The control apparatus of Claim 1 further comprising a video polarity switch coupled to the video source and the video interface for reversing the polarity of the active matrix device in response to a periodic timing signal.

3. The control apparatus of Claim 1 wherein the data scanner comprises an odd column shift register array for driving the odd columns of the active matrix region and an even column shift register array for driving the even columns of the active matrix device.

4. The control apparatus of Claim 1 f rther comprising an encoder coupled to the video source for generating a superposed analog video signal from the video signals.

5. The control apparatus of Claim 4 wherein the encoder maps the video signals to a superposed color analog signal.

6. The control apparatus of Claim 4 wherein the encoder maps the video signals to a gray-scale analog signal.

7. The control apparatus of Claim 6 further comprising at least one temperature sensor disposed in the active matrix device for signaling temperature data to the control apparatus.

8. The control apparatus of Claim 6 further comprising at least one light sensor disposed in the active matrix device for signaling relative light transmission changes to the control apparatus.

9. The control apparatus of Claim 1 wherein the active matrix display panel is a multi-frequency scanning display device.

10. The control apparatus of Claim 1 wherein the select and data scanners are fabricated within the active matrix display panel.

11. A method for controlling an active matrix projection display panel having a plurality of select lines and a plurality of column lines, the select lines and column lines forming an active matrix device, comprising the steps of: receiving video signals from a video source and converting the video signals to a group of signals comprising select line signals; generating select line drive signals on respective opposite sides of a select line of the active matrix device in response to the select line signals; and driving the columns of the active matrix region to selectively actuate pixel electrodes connected to each select line.

12. The method of Claim 11 further comprising the step of reversing the polarity of the active matrix device in response to a periodic timing signal.

13. The method of Claim 11 wherein the step of driving comprises driving the odd columns of the active matrix device at one polarity and driving the even columns of the active matrix device at the opposite polarity.

14. The method of Claim 11 further comprising the step of generating a superposed analog video signal in response to the video signals from the video source.

15. The method of Claim 14 wherein the step of generating a superposed analog video signal comprises mapping the video signals to a superposed color analog signal.

16. The method of Claim 14 wherein the step of generating a superposed analog video signal comprises mapping the video signals to a gray-scale analog signal.

17. The method of Claim 16 further comprising the step of sensing the temperature of the active matrix device and signalling temperature data reflecting the temperature to affect the gain in the gray-scale analog signal.

18. The method of Claim 16 further comprising sensing light intensity in the active matrix device and signalling relative light transmission changes to affect the gray-scale analog signal.

19. The method of Claim 11 wherein the step of converting comprises operating the active matrix display panel as a multi-frequency scanning display device.

20. The method of Claim 11 further comprising providing a slide projector housing in which the active matrix device has been inserted; directing light from a light source onto the active matrix device during selective actuation of the pixel electrodes to form a video image; projecting the video image through an optical system of the slide projector onto a viewing surface.