WO1993020889A1 - Method and apparatus for rate-responsive cardiac pacing - Google Patents

Abstract

A rate-responsive cardiac pacemaker comprising a minute ventilation circuit and an activity circuit (70). The minute ventilation circuit computes a first target pacing rate as a function of measurements of the patient's blood impedance, and the activity circuit computes a second target pacing rate as a function of measured levels of patient activity. A rate control function establishes a rate-responsive pacing rate based on the first and second target pacing rates. The minute ventilation circuit delta-modulates an analog impedance waveform and maintains short-term and long-term weighted averages of delta-modulator output counts. Variations in the difference between the short-term and long-term weighted average values are determinative of the first target pacing rate. Variations in an activity sensor (20) output signal are determinative of the second target pacing rate. Physician-programmable parameters for the pacemaker include selection of a rate-response setting, upper and lower pacing rate limits, and rate-smoothing attack and decay settings.

Description

METHOD AND APPARATUS FOR RATE-RESPONSIVE CARDIAC PACING

FIELD OF THE INVENTION

This invention relates generally to the field of cardiac pacemakers, and mo particularly relates to cardiac pacemakers of the type which measure the metaboli demand for oxygenated blood and vary the pacing rate of the pacemaker in accordanc therewith.

BACKGROUND OF THE INVENTION

A wide variety of cardiac pacemakers are known and commercially availabl Pacemakers are generally characterized by which chambers of the heart they are capab of sensing, the chambers to which they deliver pacing stimuli, and their responses, any, to sensed intrinsic electrical cardiac activity. Some pacemakers deliver pacin stimuli at fixed, regular intervals without regard to naturally occurring cardiac activit More commonly, however, pacemakers sense electrical cardiac activity in one or bo of the chambers of the heart, and inhibit or trigger delivery of pacing stimuli to the hea based on the occurrence and recognition of sensed intrinsic electrical events. A so-call

"WT" pacemaker, for example, senses electrical cardiac activity in the ventricle of t patient's heart, and delivers pacing stimuli to the ventricle only in the absence electrical signals indicative of natural ventricular contractions. A "DDD" pacemake on the other hand, senses electrical signals in both the atrium and ventricle of t patient's heart, and delivers atrial pacing stimuli in the absence of signals indicative natural atrial contractions, and ventricular pacing stimuli in the absence of signa indicative of natural ventricular contractions. The delivery of each pacing stimulus a DDD pacemaker is synchronized with prior sensed or paced events.

Pacemakers are also known which respond to other types of physiologically-bas signals, such as signals from sensors for measuring the pressure inside the patient ventricle or for measuring the level of the patient's physical activity. In recent year pacemakers which measure the metabolic demand for oxygen and vary the pacing ra in response thereto have become widely available. Perhaps the most popularly employ method for measuring the need for oxygenated blood is to measure the physical activity of the patient by means of a piezoelectric transducer. Such a pacemaker is disclosed in TJ.S. Patent No. 4,485,813 issued to Anderson et al.

In typical prior art rate-responsive pacemakers, the pacing rate is determined according to the output from an activity sensor. The pacing rate is variable between a predetermined maximum and minimum level, which may be selectable by a physician from among a plurality of programmable upper and lower rate limit settings. When the activity sensor output indicates that the patient's activity level has increased, the pacing rate is increased from the programmed lower rate by an incremental amount which is determined as a function of the output of the activity sensor. That is, the rate-responsive or "target" pacing rate in a rate-responsive pacemaker is determined as follows:

Target Rate = Programmed Lower Rate + f(sensor output) where f is typically a linear or monotonic function of the sensor output. As long as patient activity continues to be indicated, the pacing rate is periodically increased by incremental amounts calculated according to the above formula, until the programmed upper rate limit is reached. When patient activity ceases, the pacing rate is gradually reduced, until the programmed lower rate limit is reached.

In an effort to minimize patient problems and to prolong or extend the useful life of an implanted pacemaker, it has become common practice to provide numerous programmable parameters in order to permit the physician to select and/or periodically adjust the desired parameters or to match or optimize the pacing system to the patient's physiologic requirements. The physician may adjust the output energy settings to maximize pacemaker battery longevity while ensuring an adequate patient safety margin. Additionally, the physician may adjust the sensing threshold to ensure adequate sensing of intrinsic depolarization of cardiac tissue, while preventing oversensing of unwanted events such as myopotential interference or electromagnetic interference (EMI). Also, programmable parameters are typically required to enable and to optimize a pacemaker rate response function. For example, Medtronic, Inc.'s Legend and Activitrax series of pacemakers are multiprogrammable, rate-responsive pacemakers having the following programmable parameters: pacing mode, sensitivity, refractory period, pulse amplitude, pulse width, lower and upper rate limits, rate response gain, and activity threshold.

For any of the known rate-responsive pacemakers, it is clearly desirable that th sensor output correlate to as high a degree as possible with the actual metabolic an physiologic needs of the patient, so that the resulting rate-responsive pacing rate may b adjusted to appropriate levels. A piezoelectric activity sensor can only be used t indirectly determine the metabolic need. The physical activity sensed can be influence by upper body motion. Therefore, an exercise that involves arm motion may provid signals that are inappropriately greater than the metabolic need. Conversely, exercise that stimulate the lower body only, such as bicycle riding, may provide a low indicatio of metabolic need while the actual requirement is very high. Therefore, it would b desirable to implement a rate-responsive pacemaker that is based on a parameter that i correlated directly to metabolic need.

Minute ventilation (V_e) has been demonstrated clinically to be a parameter tha correlates directly to the actual metabolic and physiologic needs of the patient. Minut ventilation is defined by the equation:

V_c = RR x VT where RR = respiration rate in breaths per minute (bpm), and VT = tidal volume i liters. Clinically, the measurement of V_c is performed by having the patient breath directly into a device that measures the exchange of air and computes the total volum per minute. The direct measurement of V_c is not possible with an implanted device However, measurement of the impedance changes of the thoracic cavity can b implemented with an implanted pacemaker. Such a pacemaker is disclosed in U.S Patent No. 4,702,253 issued to Nappholz et al. on October 27, 1987. The magnitud of the change of the impedance signal corresponds to the tidal volume and the frequenc of change corresponds to respiration rate.

The use of transthoracic impedance to indicate V_e has a significant spurious fals positive due to upper body myopotential interference and postural changes. Furthe slow-acting physiologic parameters such as transitory blood chemistry changes als impact the impedance amplitude. Therefore, it may be desirable to define a rate respons function f which minimizes the effects of spurious or transitory changes in impedance sensor output which do not accurately indicate the patient's metabolic needs.

Additionally, basing the pacing rate solely on V_c does not provide the optimum pacing rate increase at the onset of exercise. The VT and RR have an inherent physiologic time delay due to the response of the CO₂ receptors and the autonomic nervous system. The increase in V_c lags behind the need for increased cardiac output. Therefore, it may also be desirable to implement a rate response function f that is based on a combination of a fast responding sensor such as an activity sensor and a physiologically delayed metabolic sensor such as V_e. The combination of the activity and V_e sensor outputs for a rate response function in a manner where the faster of the two independently derived target pacing rates would be utilized as the actual pacing rate is believed to be effective. Such an 'OR' combination of sensor signals is disclosed, for example, in U.S. Patent No. 5,063,927 issued to Webb et al., which patent is incorporated herein by reference. Combining an activity-based target rate and a metabolic-based target rate in the manner suggested by

Webb et al. would provide the fast onset of an activity sensor with the sustained response of a V_c sensor. Provisions in the rate response function f would need to include lower and upper rate limits, along with a mapping function from impedance to pacing rate that could be adjusted by a physician to optimize the function for each patient.

SUMMARY OF THE INVENTION

In one disclosed embodiment of the invention, a pacemaker having an impedance based minute ventilation sensor and an acoustical energy, pressure, or other type o activity sensor computes a target rate-responsive pacing rate based upon a function of th two sensors' outputs. In the disclosed embodiment of the invention, processing of the impedance-base minute ventilation sensor occurs independently of the processing of other activity senso signals, and two or more "target" rate-responsive pacing rates are independentl determined. Further computation results in a rate-responsive pacing rate whic represents some function of each of the independently determined target rates. In one disclosed embodiment of the invention, the minute ventilation is determine using the change of impedance of the tripolar transthoracic impedance vector. A curren is forced between the pacemaker's conductive housing and the ring electrode of th pacemakers transvenous lead, and the resultant voltage is measured at the tip electrod of the lead with reference to the case. The DC component of the impedance signal i removed and the AC component processed by a delta-modulator function. The delta modulator resolves the change in the analog impedance signal voltage into digital count or pulses, the number of counts being proportional to the change. The counts ar summed over an interval of two seconds to produce the product of amplitude and rate The impedance-based target pacing period is then determined as a function of this minut ventilation signal.

In another embodiment of the invention, impedance is determined from th intracardiac vector measured from the ring electiode to the tip electrode of the pacemake lead. The signal is processed with LP filtering to remove the cardiac component. Th target pacing rate may then be determined using the processed impedance signal.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other features of the present invention will be best appreciate with reference to the detailed description of a specific embodiment of the invention which follows, when read in conjunction with accompanying drawings, wherein: Figure 1 is a diagram showing the placement in the patient of a pacemaker i accordance with one embodiment of the present invention;

Figure 2 is a block diagram of functional components of the pacemaker of Figur i;

Figure 3 is a flow diagram illustrating the process for generating certai numerical values used in computations associated with the pacing algorithm of th pacemaker of Figures 1 and 2;

Figures 4a through 4d are graphs showing families of rate-response functions f the pacemakers of Figures 1 and 2; Figure 5 is a block diagram of the impedance circuit of the pacemaker of Figures 1 and 2.

DETAILED DESCRIPTION OF A SPECIFIC EMBODIMENT OF THE INVENTION Figure 1 shows generally where a pacemaker 10 in accordance with on embodiment of the present invention may be implanted in a patient 12. It is to be understood that pacemaker 10 is contained within a hermetically-sealed, biologically iner outer shield or "can" , in accordance with common practice in the art. A pacemaker lead 14 is electrically coupled to pacemaker 10 and extends into the patient's heart 16 via vein 18. The distal end of lead 14 includes one or more exposed conductive electrodes for receiving electrical cardiac signals and/or for delivering electrical pacing stimuli t the heart 16. Lead 14 may be implanted with its distal end situated in the atrium o ventricle of heart 16.

Turning now to Figure 2, a block diagram of pacemaker 10 from Figure 1 i shown. Although the present invention will be described herein in conjunction with pacemaker 10 having a microprocessor-based architecture, it will be understood tha pacemaker 10 may be implemented in any logic based, custom integrated circui architecture, if desired. It will also be understood that the present invention may b utilized in conjunction with other implantable medical devices, such as cardioverters, defibrillators, cardiac assist systems, and the like.

In the illustrative embodiment shown in Figure 2, pacemaker 10 includes a activity sensor 20, which may be, for example, a piezoelectric element bonded to th inside of the pacemaker's shield. Such a pacemaker/activity sensor configuration is th subject of the above-referenced patent to Anderson et al., which is hereby incorporate by reference in its entirety. Piezoelectric sensor 20 provides a sensor output whic varies as a function of a measured parameter that relates to the metabolic requirement of patient 12.

Pacemaker 10 of Figure 2 is programmable by means of an external programmin unit (not shown in the Figures). One such programmer suitable for the purposes of th present invention is the Medtronic Model 9760 programmer which has bee commercially available for several years and is intended to be used with all Medtroni pacemakers. The programmer is a microprocessor device which provides a series encoded signals to pacemaker 10 by means of a programming head which transmi radio-frequency (RF) encoded signals to pacemaker 10 according to the telemetry syste laid out, for example, in U.S. Patent No. 4,305,397 issued to Weisbrod et al. o December 15, 1981, U.S. Patent No. 4,323,074 issued to Nelms on April 6, 1982, in U.S. Patent No. 4,550,370 issued to Baker on October 29, 1985, all of which a hereby incorporated by reference in their entirety. It is to be understood, however, th the programming methodologies disclosed in the above-referenced patents are identifi herein for the purposes of illustration only, and that any programming methodology ma be employed so long as the desired information is transmitted to the pacemaker. It believed that one of skill in the art would be able to choose from any of a number available programming techniques to accomplish this task. The programmer facilitates the selection by a physician of the desired paramet to be programmed and the entry of a particular setting for the desired parameter. F purposes of the present invention, the specifics of operation of the programmer are n believed to be important with the exception that whatever programmer is used mu include means for selecting an upper rate (UR), a lower rate (LR), and one of a plurali of rate response (RR) settings to be hereinafter described in greater detail.

In the illustrative embodiment, the lower rate may be programmable, for examp from 40 to 90 pulses per minute (PPM) in increments of 10 PPM, the upper rate m be programmable between 100 and 170 PPM in 10 PPM increments, and there may 16 rate response functions, numbered one through sixteen, available. In addition, the programmer may include means for selection of acceleration a deceleration parameters which limit the rate of change of the pacing rate. Typicall these parameters are referred to in rate responsive pacemakers as acceleration a deceleration settings, respectively, or attack and decay settings, respectively. These m be expressed in terms of the time interval required for the pacemaker to change betwe the current pacing rate and 90% of the desired pacing interval, assuming that the activi level corresponding to the desired pacing rate remains constant. Appropriate selectable values for the acceleration time would be, for example, 0.25 minutes, 0.5 minutes, and 1 minute. Appropriate selectable values for the deceleration time would be, for example, 2.5 minutes, 5 minutes, and 10 minutes. Pacemaker 10 is schematically shown in Figure 2 to be electrically coupled via a pacing lead 14 to a patient's heart 16. Lead 14 includes an intracardiac tip electrode 24 located near its distal end and positioned within the right ventricular (RV) or right atrial (RA) chamber of heart 16. Lead 14 is a bipolar electrode, as is well known in the art. Although an application of the present invention in the context of a single-chamber pacemaker will be disclosed herein for illustrative purposes, it is to be understood that the present invention is equally applicable in dual-chamber pacemakers.

Electrode 24 is coupled via suitable lead conductor 14 through input capacitor 26 to node 28 and to input/output terminals of an input/output circuit 30. In the presently disclosed embodiment, activity sensor 20 is bonded to the inside of the pacemaker's outer protective shield, in accordance with common practice in the art. As shown in Figure

2, the output from activity sensor 20 is coupled to input/output circuit 30.

Input/output circuit 30 contains the analog circuits for interface to the heart 16, activity sensor 20, antenna 52, as well as circuits for the application of stimulating pulses to heart 16 to control its rate as a function thereof under control of the software- implemented algorithms in a microcomputer circuit 32.

Microcomputer circuit 32 comprises an on-board circuit 34 and an off-board circuit 36. On-board circuit 34 includes a microprocessor 38, a system clock circuit 40, and on-board RAM 42 and ROM 44. In the presently disclosed embodiment of the invention, off-board circuit 36 includes a RAM/ROM unit. On-board circuit 34 and off- board circuit 36 are each coupled by a data communication bus 48 to a digital controller/timer circuit 50. Microcomputer circuit 32 may be fabricated of a custom integrated circuit device augmented by standard RAM/ROM components.

It will be understood that the electrical components represented in Figure 1 are powered by an appropriate implantable battery power source 51, in accordance with common practice in the art. For the sake of clarity, the coupling of battery power to th various components of pacemaker 10 has not been shown in the Figures.

An antenna 52 is connected to input/output circuit 30 for purposes uplink/downlink telemetry through RF transmitter and receiver unit 54. Unit 54 ma correspond to the telemetry and program logic employed in U.S. Patent No. 4,566,06 issued to Thompson et al. on December 3, 1985 and U.S. Patent No. 4,257,423 issue to McDonald et al. on March 24, 1981, both of which are incorporated herein b reference in their entirety. Telemetering analog and/or digital data between antenna 5 and an external device, such as the aforementioned external programmer (not shown may be accomplished in the presently disclosed embodiment by means of all data fir being digitally encoded and then pulse-position modulated on a damped RF carrier, substantially described in co-pending U.S. Patent Application Serial No. 468,407, file on January 22, 1990, entitled "Improved Telemetry Format", which is assigned to th assignee of the present invention and which is incorporated herein by reference. Th particular programming and telemetry scheme chosen is not believed to be important f the purposes of the present invention so long as it provides for entry and storage values of rate-response parameters discussed herein.

A crystal oscillator circuit 56, typically a 32,768-Hz crystal-controlled oscillato provides main timing clock signals to digital controller/timer circuit 50. A V_REF and Bi circuit 58 generates stable voltage reference and bias currents for the analog circuits input/output circuit 30. An analog-to-digital converter (ADC) and multiplexer unit digitizes analog signals and voltages to provide "real-time" telemetry intracardiac signa and battery end-of-life (EOL) replacement function. A ΔZ Processor 100 is utilized conjunction with output signals from impedance sensors, as shall be hereinafter describ in greater detail. A power-on-reset (POR) circuit 62 functions as a means to res circuitry and related functions to a default condition upon detection of a low batte condition, which will occur upon initial device power-up or will transiently occur in t presence of electromagnetic interference, for example.

The operating commands for controlling the timing of pacemaker 10 are coupl by bus 48 to digital controller/timer circuit 50 wherein digital timers and counters a employed to establish the overall escape interval of .the pacemaker, as well as various refractory, blanking^ and other timing windows for controlling the operation of the peripheral components within input/output circuit 30.

Digital controller/timer circuit 50 is coupled to sensing circuitry including a sense amplifier 64, a peak sense and threshold measurement unit 65, and a comparator/threshold detector 69. Circuit 50 is further coupled to receive an output signal from an electrogram (EGM) amplifier 66. EGM amplifier 66 receives, amplifies and processes electrical signals provided from multiplexor 84. Multiplexor 84 receives a signal from 1 of 2 places: 1) electrode 24, lead conductor 14 and capacitor 26, this signal being representative of the electrical activity of the patient's heart 16; and 2) an impedance waveform resulting from operation of an impedance circuit 82 (to be hereinafter described in detail).

A sense amplifier 64 amplifies sensed electrical cardiac signals and provides this amplified signal to peak sense and threshold measurement circuitry 65, which provides an indication of peak sensed voltages and the measured sense amplifier threshold voltag on multiple conductor signal path 67 to digital controller/timer circuit 50. The amplified sense amplifier signal is then provided to comparator/threshold detector 69. Sens amplifier 64 may correspond, for example, to that disclosed in U.S. Patent No. 4,379,459 issued to Stein on April 12, 1983, incorporated by reference herein in it entirety. The electrogram signal developed by EGM amplifier 66 is used on thos occasions when the implanted device is being interrogated by an external programmer, not shown, to transmit by uplink telemetry a representation of the analog electrogram o the patient's electrical heart activity, such as described in U.S. Patent No. 4,556,063 issued to Thompson et al., assigned to the assignee of the present invention an incorporated herein by reference. As previously noted, EGM amplifier 66 als selectively receives an impedance waveform which may also be transmitted by uplin telemetry to an external programmer.

An output pulse generator 68 provides pacing stimuli to the patient's heart 1 through coupling capacitor 74 in response to a pacing trigger signal developed by digita controller/timer circuit 50 each time the escape interval times out, or an externall transmitted pacing command has been received, or in response to other stored commands as is well known in the pacing art. Output amplifier 68 may correspond generally to the output amplifier disclosed in U.S. Patent No. 4,476,868 issued to Thompson on October 16, 1984 also incorporated herein by reference in its entirety. While specific embodiments of input amplifier 64, output amplifier 68, and EGM amplifier 66 have been identified herein, this is done for the purposes of illustration only. It is believed by the inventor that the specific embodiments of such circuits are hot critical to the present invention so long as they provide means for generating a stimulating pulse and provide digital controller/timer circuit 50 with signals indicative o natural and/or stimulated contractions of the heart.

Digital controller/timer circuit 50 is coupled to an activity circuit 70 for receiving, processing, and amplifying signals received from activity sensor 20. Digita controller/timer circuit 50 is also coupled, via line 80 to a ΔZ Processor circuit 100, which in turn is coupled to an impedance circuit 82. Impedance circuit 82 is coupled directly to pacing lead 14. Impedance circuit 82 measures cardiac impedance by outputting periodic biphasic current pulses on pacing lead 14, and then sensing th resulting voltages. The resulting voltages are sensed and demodulated in an AC-couple manner, to generate a voltage waveform (hereinafter "impedance waveform") whic reflects changes in impedance (i.e., with baseline impedance subtracted). The utilizatio of an impedance sensor of this type in a cardiac pacemaker is the subject of the above referenced U.S. Patent No. 4,702,253 to Nappholz et al., which is hereby incorporate by reference in its entirety. The measured impedance changes will be related t respiratory changes in frequency and magnitude. The analog impedance waveform i scaled and filtered in impedance circuit 82, and the resulting waveform provided to Δ Processor 100 for conversion to digital format, as shall be hereinafter described i greater detail.

The time-course of the impedance waveform represents the minute ventilatio parameter which will be measured for the purposes of the present disclosure in units o Ω x (breaths per minute), hereinafter referred to as "Wallys" and symbolized by th Greek letter _ -. In accordance with the presently disclosed embodiment of the invention pacemaker 10 computes two average values which are updated every two seconds. The first average value is the average number of Wally s occurring in each of the sixteen two- second intervals during the previous thirty-two seconds; this value shall be referred to as the short-term Wally average. The second average value is the average number of Wallys occurring in each of the 1024 two-second intervals during the previous 2048 seconds; this average value shall be referred to as the long-term Wally average. Every two seconds, the relative difference between the long-term Wally average and the short- term Wally average is used to deteπnine the impedance-based target pacing rate. That is, every two seconds, the difference between the long-term Wally average and the short- term Wally average is compared to the value of this difference computed two seconds before. This relative difference value represents the short-term change in respiratory impedance, and has units of 0 x (breaths per minute, per second), hereinafter referred to as "Wallys per second" and symbolized by the Greek letter Ψ.

Pacemaker 10 in accordance with the presently disclosed embodiment of the invention implements sixteen programmable rate-response settings, which define the resultant impedance-based target pacing rate for a given number of Wallys per second measured. The selectable rate-response settings are numbered 1 - 16, and are characterized by the number of Wallys per second required to achieve pacing at the programmed upper rate at that setting. In addition to the sixteen rate-response settings, pacemaker 10 is also programmable into one of four possible gain settings. The gain setting determines the factor by which the impedance waveform is scaled prior to analog- to-digital conversion. The following Table 1 sets forth the 16 rate response settings.

As noted above, impedance circuit 82 in accordance with the present invention delivers periodic biphasic current pulses to heart 16; these current pulses are applied to heart 1 via line 83 (which is coupled to lead 14). The resultant voltage waveform is received from lead 14 by impedance circuit 82, which demodulates, filters, and scales th impedance waveform before providing it to ΔZ Processor 100. In accordance with th presently disclosed embodiment of the invention, ΔZ Processor 100 is a delta-modulato type data converter. Every 62.5 milliseconds, ΔZ Processor 100 samples the impedanc waveform voltage and outputs a serial bit stream, on line 80, of between 0 and 31 logica '1' bits (where each '1' bit is called a 'count'), the number of counts indicating th magnitude of the change in the impedance waveform voltage since the last sample. Tha is, the number of counts during each sampling period is proportional to the rate o change of the impedance over time, dZ/dt. The magnitude of the change is measure in terms of a number of discrete voltage steps in either the positive or negative directio required to bring the previous reference input of a comparator to the level of the newly sampled voltage input.

The output serial bit stream of ΔZ Processor 100 shall be hereinafter referred to as DM, which is a value having units of counts per second. The data conversion function of ΔZ Processor 100 may then be described as follows:

where

and where

At = 62.5 milliseconds @)

P_fa = precision (i.e., step size) of delta modulator (4)

and

= integer part of — (5)

The serial output of ΔZ Processor 100 on line 80 is processed digitally by digital controller/timer circuit 50 to produce a control variable DZ from which the impedance- based rate-responsive target pacing rate will be calculated. The digital processing of the ADC serial output shall be hereinafter described with reference to Figure 5. For the purposes of describing the signal processing, several definitions are necessary: Long-Term Average (LTA.:

The LTA value is a parallel output word representing a weighted average of two- second delta modulator counts, with the weighting or emphasis being placed on two second counts during the latest 2048 seconds. The LTA value is updated every tw seconds.

Long-term Average (LTA. Initialization Protocol:

The LTA initialization protocol is as follows:

The 2048 second Long-Term Average (LTA) value is initialized using a interactive protocol with the programmer. The protocol also determines the correc analog gain range for ΔZ processing for each patient. The following four ranges ar available:

0 to 10 Ω (first gain range)

0 to 20 Ω (second gain range)

0 to 40 Ω (third gain range) 0 to 80 Ω (fourth gain range)

When the sensor is first enabled, a 32 second countdown is initiated in the pacemake and the programmer. When the countdown has finished, 32 seconds of delta-modulato counts are loaded into the upper bits of both the Short-Term Average (STA) value an the LTA value. This initializes the difference, DZ (STA - LTA) to zero, (where DZ i the Limited Positive Difference), and the first calculated target rate to a lower rate (LR)

Simultaneously, the programmer notifies the user to perform an interrogate which uplink the value for the LTA. If the LTA is less than or equal to the mid-range value of Δ counts (e.g., 256), then the analog gain remains in the 0 to 10 Ω range. If the value i greater than mid-range, then the analog gain is increased to the 0 to 20 Ω and th initialization protocol repeated. If the repeated LTA value is greater than mid-range then another initialization is repeated in the 0 to 40 Ω range. This process continues unti the LTA is less than or equal to mid-range or the 0 to 80 Ω range is programmed. Limited Short-Term Average (LSTA.:

The LSTA value is a parallel output word representing the average number of delta-modulator counts occurring in two seconds, over the latest 32 seconds. This value is updated every two seconds. If the rate calculation algorithm in accordance with the presently disclosed embodiment of the invention returns an impedance-based target rate higher than the programmed upper rate limit, the LSTA is not increased further, even if the output of ΔZ Processor 100 indicates that it should be increased. This prevents saturation of the rate-calculation, and resultant delay in decrease from upper rate when the delta-modulator count is reduced.

Limited Positive Difference (DZ_:

The DZ value represents a comparison between the LSTA and LTA values. The DZ value is a parallel output word which is updated every two seconds according to the following formula:

0 : LSTA < LTA

DZ = LSTA-LTA : O≤ (LSTA - LTA) ≤DZ^ (6)

DZ_^ mm : LSTA-LTA ≥DZ m_^m

The maximum increase in DZ from one two-second value to the next is limited by the UR_DIFF circuitry, as shall be hereinafter described in greater detail.

Unlimited Short Term Average (USTA_:

The USTA value is a parallel output word which represents the average number of delta-modulator counts occurring in two seconds, over the latest 32 seconds. USTA is updated every two seconds. Unlike LSTA, however, USTA is not limited by any dependance on the result of the impedance-based rate-response calculation. Unlimited Positive Difference Function (TJDZ.:

The UDZ value represents a comparison between USTA and LTA. the TJD value is a parallel output word which is updated every two seconds according to th following formula:

0 : USTA < LTA

UDZ = USTA- LTA : 0 ≤ (USTA- LTA) ≤ 127 J- rø

127 : USTA- LTA ≥ I J

Maximum DZ (MAXDZ.:

The MAXDZ value corresponds at all times to the largest UDZ value generate since MAXDZ was last reset.

Clipping (TJR DIFF,:

The UR_DIFF value is programmable to one of four selectable settings: (nominal value), .2, 4, or 8. The clipping function limits the magnitude of the inpu signal based on limits that are adjusted based upon the rate-response setting. Thi function limits the rate change due to false positive signals due to postural or non respiration muscle motion. The clipping function is disabled when LSTA is less tha LTA and during initialization. When enabled, the clipping function limits the inp signal to a maximum value computed as follows:

INPUT SIGNAL MAXIMUM = — — ^- (8)

UR DIFF

where DZ^,,, corresponds to the DZ value resulting in a target pacing period at th programmed upper rate limit (URL). Target Pacing Period (TPP_:

Each time a new DZ value is computed, the impedance-based TPP can be calculated according to the following formula:

TPP = E+ ^F (9)

DZ+G

where

TPP - new target pacing period E = downloadable constant

F = downloadable constant (10)

G - downloadable constant DZ = latest DZ value

The values E, F, and G are chosen based on the currently selected rate response setting (see Table 1 above) and the currently programmed lower rate limit (LRL) and upper rate limit (URL). The process for selecting values for E, F, and G will be best understood with reference to the flow diagram of Figure 3. In Figure 3, the process begins at block 100, where the value of E is initialized to zero. Next, in block 102 the value of G is initialized according to the following formula:

where DZ^,. is the minimum DZ value (i.e., the minimum maximum value of DZ) required to reach the programmed upper rate limit at the current rate response setting, LRP is the current lower rate period (expressed in numbers of slow clock cycles per pacing cycle) and URP is the current upper rate period (expressed in numbers of slow clock cycles per pacing cycle). In block 104, F is set to (G x LRP).

In decision block 106, two comparisons are made: if F is greater than or equal to 16,384, or if G is greater than or equal to 512, process flow branches to block 110. If F is not greater than 16,384 and if G is not greater than or equal to 512, process flo branches to block 108.

In block 108, the integer part of the calculation F / DZ^ + G) is compared wit URP + 1. If these values are equal, the process stops, as indicated by STOP symbo 112 in Figure 4. If the two values compared in block 108 are not equal (or, if a "yes result was reached in decision block 106) process flow proceeds to block 110, where th value of G is set to 511. Then, in block 114, F is calculated according to the followin formula:

F = G x (12)

In block 116, E is calculated according to:

E - inti0.5 +LRP -a (13)

Next, in decision block 118, F is compared with the value 16,384 and E i compared with zero. If F is greater than or equal to 16,384 or E is less than zero process flow branches to block 120; otherwise, process flow stops, as indicated by STO symbol 122. In block 120, G is decremented by one. In decision block 124, G i compared with zero. If G equals zero, process flow branches to block 126; if G doe not equal zero, process flow returns to block 114, and blocks 114, 116, and 118 ar repeated. In block 126, G is calculated according to equation 11 described wit reference to block 102 above. In block 128, the value F = G x LRP is computed, an process flow stops, as indicated by STOP symbol 130.

The resultant mapping of DZ values to target pacing rates achieved through th computations described by equations (1) through (13) above may be best appreciated wit reference to Figures 4a through 4d, which are graphs showing the impedance-based target pacing period (TPP) verses DZ value for all sixteen rate response settings, for six combinations of programmed URL and LRL.

The graph of Figure 4a, for example, shows the family of sixteen rate response curves resulting from setting the URL to 170 pulses per minute (PPM) and the LRL to

40 PPM. In Figure 4b, URL and LRL are 100 and 90 PPM, respectively. In Figure 4c, URL and LRL are 100 and 40 PPM, respectively, and in Figure 4d, URL and LRL are 120 and 70 PPM, respectively.

It should be noted with reference to Figures 4a through 4d that the computations of equations 1 through 13 above ensure that for any combination of programmed URL, programmed LRL, and programmed rate-response setting, the pacing rate remains variable along the full range between LRL and URL.

It is to be understood that Figure 4a through 4d depict the families of rate- response curves for only some selected combinations of URL and LRL; however, it is believed by the inventors that a person of ordinary skill in the art could reconstruct the family of rate-response curves for any allowable combination of URL and LRL through application of equations 1 through 13 above. In accordance with the presently disclosed embodiment of the invention, programming an LRL to a rate greater than or equal to URL is not allowed. Following calculation of a impedance-based target pacing period (TPP) in the manner described above, a rate smoothing function is calculated. As would be apparent to one of ordinary skill in the art, a rate smoothing function limits the rate of change in the rate-responsive pacing period. The rate-smoothing function of pacemaker 10 in accordance with the presently disclosed embodiment of the invention is described in terms of variable NEWPP, which is defined as follows:

: TPP< CURPP

NEWPP = { (14) : TPP≥ CURPP

where NEWPP is the "smoothed" target period, TPP is the impedance-based rate responsive target pacing period as before; CURPP is the currently active rate-respons period; ATT is a programmed rate smoothing attack constant; and DEC is a programme rate smoothing decay constant. In accordance with the presently disclosed embodime of the invention, ATT and DEC may take on programmed values of one through seven

After NEWPP has been calculated, the current pacing period (CURPP) for th next pacing cycle is replaced with the NEWPP value. The new rate-responsive pacin rate is related to the CURPP value as follows:

RATE-RESPONSIVE RATE - 60 x/ beats (15)

(CURPP + I) x 25& min

where f is the frequency of system clock 56, typically 32,768-Hz, and 258/f is the perio of a "slow-clock" signal derived from the system clock. The slow-clock period is multiple of the system clock period, and the slow-clock period is the basic unit in whic various cardiac cycle timing intervals are measured in pacemaker 10.

Turning now to Figure 6, a block diagram of the circuitry within digit controller/timer circuit 50 which is responsible for computing the impedance-based rat responsive pacing rate as described herein is shown. As can be seen from Figure several of the synchronous (i.e., clock-driven) components of the rate-response circuitr to be hereinafter described in greater detail, have applied thereto an input sign TWOSCLK. TWOSCLK is a two-second clock signal that is derived from system cloc 56 in a conventional manner. It is to be understood that it is the same TWOSCLK sign that is being simultaneously applied to several components of the rate-response circuitr even though the various TWOSCLK inputs in Figure 6 are not shown as being interconnected.

In addition, several components of the circuitry of Figure 6 are computational elements requiring externally supplied parameter values, such as are provided by a physician using an external programming device. In Figure 6, programmable parameter values supplied to pacemaker 10 by means of a telemetry system such as described hereinabove are identified by their parameter name (e.g., UR_DIFF, E, F, G, etc..) within an ellipse, underneath a "DOWNLINK" label. For example, the impedance based-rate response setting (DZ RR#), which is a number between one and sixteen as previously described, is shown in Figure 6 as being applied to DECODE circuit 200 via a four-conductor data path 202. For the sake of clarity, it is to be understood in Figure 6 that the label "DOWNLINK" above a parameter name within an ellipse will- serve as a representation that the parameter value identified in the ellipse is a value that is provided to pacemaker 10 by means of the telemetry system described hereinabove, including antenna 52 and RF Transmitter/Receiver 54 shown in Figure 2. Similarly, it is to be understood that the label "UPLINK" associated with a given data path in Figure 6 is intended to represent a data value which is available to telemetry circuit 54 to be transmitted to an external programmer, as previously described. For example, the UPLINK label on line 245 in Figure 6 is to be taken as an indication that the MAXDZ value on line 245 is one of the values which can be transmitted to an external programmer upon interrogation of pacemaker 10.

In Figure 6, the input signal DM is shown being applied by line 88 to the count (C) input of TWO-SECOND COUNTER 204, which also receives the TWOSCLK signal at its reset (R) input. DM, which is the serial bit-stream output of ΔZ Processor 100 previously described with reference to Figure 2, is also applied to one input of AND gate

206.

The TWOSCLK signal applied to the reset input of TWO-SECOND COUNTER 204 causes the count value of TWO-SECOND COUNTER 204 to be reset to zero every two seconds. Immediately after reset, the count value in TWO-SECOND COUNTER 204 is incremented by one for every pulse of the DM signal on line 88. Since the number of pulses in the serial bit stream DM corresponds to the change in the inpu voltage to ΔZ Processor over the last 62.5 milliseconds, the count value in TWO SECOND COUNTER 204 will vary accordingly.

The count value of TWO-SECOND COUNTER 204 is applied on 10-bit line 20 to a comparator 210. The signal on output line 212 from comparator 210 is asserte whenever the 10-bit value on line 208 becomes greater than or equal to the 11-bit valu applied on line 214 from an adder 216. The signal on line 212 is applied to an invertin input of an OR gate 218, the output of which is applied to a second input of AND gat 206. Comparator 210, OR gate 218, and AND gate 206 implement the UR_DIF clipping function described hereinabove. The output of OR gate 218 is typically a logica

"1", going to a logical "0" value during initialization, when clipping of the input sign is required, as will be hereinafter described.

When the output of OR gate 218 is a logical " 1 " , the serial bit stream DM on lin 88 is propagated through AND gate 206 and applied on line 220 to the inputs of MAXDZ circuit 222, a SHORT-TERM AVERAGE (STA) circuit 224, and a LONG

TERM AVERAGE (LTA) circuit 226. MAXDZ circuit 222 produces a valu NEW_MTA every two seconds, according to the recursive formula:

NEW MTA = (— )MTA +(— )DM (16)

116 ). { 16)

where MTA is the most recently calculated NEW_MTA value and DM is the sum of th number of pulses occurring in the DM bit stream in the last two-second interval. Ever two seconds (as determined by TWOSCLK) MAXDZ circuit 222 produces a NEW_MT value on 10-bit output line 223, and this value is latched in MTA LATCH 228 so th it is available on line 230 until a new NEW_MTA value is produced two seconds late

Operation of SHORT-TERM AVERAGE (STA) circuit 224 is substantiall identical to that of MAXDZ circuit 222. The DM serial bit stream is applied, via AN gate 206 and line 220 to an input of SHORT-TERM AVERAGE (STA) circuit 22 Every two seconds, SHORT-TERM AVERAGE (STA) circuit 224 produces a value NEW_STA on line 225, and this value is latched in STA LATCH 232 so that the NEW_STA value is available on line 234 for two seconds until a new NEW_STA value is calculated. The value NEW_STA is computed according to the following recursive formula:

NEW_STA = f— \sTA +(— )DM (17)

{16) [ iβ)

where STA is the most recently computed NEW_STA value and DM is the sum of the number of pulses occurring in the DM bit stream in the last two-second interval.

Similarly, LONG-TERM AVERAGE (LTA) circuit 226 produces a value

NEW_LTA on 10-bit output line 227 every two seconds, and this value is latched in LTA LATCH 236 so that it is available on line 238 for two seconds until a new

NEW_LTA value is calculated. The NEW_LTA value is computed every two seconds according to the following recursive formula:

where LTA is the most recently computed NEW_LTA value and DM is the sum of the number of pulses occurring in the DM bit stream in the last two-second interval. Subtracting circuit 240 receives the value latched in MTA LATCH 228 at one input and the value latched in the LTA latch at another input. Subtracting circuit 240 performs the computation (MTA minus LTA). If (MTA minus LTA) is less than zero, subtracting circuit 240 produces a zero binary value on 7-bit output line 242; if (MTA minus LTA) is greater than 127, subtracting circuit 240 produces a binary value of 127 on output line 242. If (MTA minus LTA) is between zero and 127, the actual result of the computation (MTA minus LTA) is produced on output line 242. As should be apparent to one of ordinary skill in the art, subtracting circuit performs the subtractio and clipping functions necessary to produce the variable UDZ previously discussed wit reference to equation (7) above.

The UDZ value on line 242 is applied to inputs of a comparator 244 and a latc 246. Another input of comparator 244 has applied thereto, via line 245, the contents latch 246. If comparator 244 determines that the UDZ value on line 242 is greater tha the UDZ value currently stored in latch 246, comparator 244 asserts the signal on li 248, which is coupled to the enable input of latch 246. In this manner, whenever a UD value greater than any previously calculated UDZ value appears on line 242, it is store in latch 246. Thus, latch 246 holds a value corresponding to the MAXDZ val previously discussed. It should be noted that line 245 is associated with an "UPLIN label, indicating that the MAXDZ value may be transmitted by telemetry circuit 54 an antenna 52 to an external programmer performing an interrogation of pacemaker 10.

Subtracting circuit 250 receives the NEW_STA value on line 225 at one input an the NEW_LTA value on line 227 at another input. Subtracting circuit 250 performs t computation (NEW_STA minus NEWJ TA). If the result of this computation yields result less than zero, subtracting circuit 250 produces a binary zero value on 7-bit outp line 252. If the result of the computation (NEW_STA minus NEW_LTA) is greater th 127, subtracting circuit 250 produces a binary value 127 on output line 252. If the resu of the computation (NEW_STA minus NEW_LTA) is between zero and 127, the actu result of the computation is produced on line 252. It should be apparent to one ordinary skill in the art, therefore, that subtracting circuit 250 is performing t subtraction and clipping functions associated with the Limited Positive Difference (D function previously described with reference to equation (6) above. The DZ output val from subtracting circuit 250 is conducted on line 252 to the input of DZ latch 254. No that the output of DZ latch 254 is associated with an "UPLINK" label, indicating that D is one of the values which may be transmitted to an external programming device up interrogation of pacemaker 10, as previously described.

The DZ value in latch 254 is applied to computational unit 256. Also applied computational unit 256 are several programmable parameter values E, F, G, a DZ_UR. The programmable parameter values are provided to pacemaker 10 via telemetry, as previously described. Using these values, computational unit 256 performs the computation defined by equation (9) above, to determine a target pacing period (TPP) value. The TPP value produced by computational circuit 256 is limited to a minimum value of DZ_UR, which is one of the externally programmable values. That is, if the result of the computation performed by computational circuit 256 is less than DZ_UR, the value DZ_UR is substituted for the newly-computed TPP value. The TPP value is conducted on 8-bit line 258 to a rate-smoothing circuit 260.

Rate smoothing circuit 260 receives, in addition to the TPP value from computational circuit 256, downlink-telemetered values RSA and RSD, corresponding to externally programmed rate smoothing attack and decay parameters, respectively, previously discussed with reference to equation (14). Rate smoothing circuit performs the calculations defined in equations (14) and (15) above, and provides the resulting "smoothed" target period NEWPP to RR_RATE REGISTER 278._. The NEWPP value stored in register 278 is provided to one input of comparator 274.

With continued reference to Figure 6, an UR COUNTER 262 and an RR COUNTER 264 each receive a SLCK signal at their count inputs. SLCK is the "slow- clock" signal previously discussed with reference to equation (15); SLCK defines the basic unit of time in which various cardiac cycle timing intervals are measured. The output of an OR gate 266 is applied to the reset input of RR COUNTER 264, and the output of an OR gate 268 is applied to the reset input of UR COUNTER 268. The output of OR gate 266 is asserted whenever a sensed cardiac event occurs or a paced cardiac event occurs; thus, RR COUNTER 264 is reset whenever a sensed or paced cardiac event occurs. The output of OR gate 268 is asserted whenever the output of OR gate 266 is asserted, or whenever a cardiac event is sensed during a refractory period.

A comparator 270 receives the value held in the UR COUNTER at one of its inputs, and the downlink-telemetered DZ_UR value at its other input. If the UR COUNTER value is greater than or equal to the DZ_UR value, the output signal on line 272 is asserted. Comparator 274 receives, in addition to the NEWPP value from RR_RATE REGISTER 278 as previously described, the value held in the RR COUNTER 264. If comparator 274 determines that the RR COUNTER value is greater than equal to the NEWPP "smoothed" target pacing period stored in RR_RATE REGISTE 278, the signal on output line 276 is asserted. The output signals from comparators 2 and 274 are applied to the inputs of an AND gate 280; when the signals on lines 272 a 276 are simultaneously asserted, the output of AND gate 280 is asserted. The output

AND gate 280 is labelled DZ_TTME-OUT, and this signal is asserted when t impedance-based rate-responsive algorithm in accordance with the present inventi indicates that a pacing pulse should be delivered.

A comparator 282 in Figure 6 receives at one input the NEWPP value stored RR_RATE REGISTER 278, and receives the downloaded value LT FRZ at anoth input. The "Long-Term Freeze" function prevents the loss of rate-response duri prolonged periods of exercise. When comparator 282 determines that the rate-responsi pacing rate (NEWPP) exceeds the midpoint of the programmed URL and LRL (i.e. , FRZ), the signal HOLD LTA is asserted, temporarily inhibiting the averaging of t LTA.

The downlinked value DZ RR#, corresponding to the programmed rate respon setting 1 - 16 for pacemaker 10, is received by decoder circuit 200. Decoder circuit 2 translates the programmed rate-response setting into a value representing the minimu DZ value (DZ,,,,,,) required to reach the programmed upper rate limit at the selected rat response setting. The translation of a DZ RR# value to a DZ_^ value occurs accordi to the following table:

The

value produced by decoder 200 is provided on 7-bit line 290 to a shifter 292, and to an input of a comparator 294. Shifter 292 shifts the DZ,_^ value 1, 2, 3, or 4 places to the left, depending upon the value URJDIFF downlinked to pacemaker 10. The UR_DIFF value is used in ."clipping" the DM input bit stream, as previously discussed with reference to equation (8). The shifted DZ,_^ value from shifter

292 is provided on 11-bit line 296 to an input of adder 216. Adder 216 adds the shifted DZ,_^ value to the current short-term average value from STA latch 232, and provides the result of this addition on line 214 to comparator 210. In the event that the value of TWO-SECOND COUNTER 204 does not exceed the value on line 214, the signal on line 212 stays at a logical "0" level. Since line 212 is applied to an inverting input of

OR gate 218, the output of OR gate 218 stays at a logical " 1 " level whenever the signal on line 212 is at a logical "0" level. However, if the value of TWO-SECOND COUNTER 204 exceeds the value on line 214, the output signal on line 212 is asserted. If no other input signals to OR gate 218 are asserted when line 212 is asserted, the output of OR gate 218 will go to a logical "0" level. When the output of OR gate 218 goes to a logical "0", the DM bit stream on line 88 is prevented from propagating through AN gate 206. As a result, the MAXDZ, STA, and LTA circuits 222, 224, and 226 will n receive further DM bit pulses.

A comparator 294 receives the NEW_DZ value on line 252 at one input and t DZ,,,,,. value from decoder 200 at another input. If comparator 294 determines that t

NEW_DZ value exceeds the DZ^, value, the output signals CLIP STA and HOL NEXT LTA are asserted. The CLIP STA and HOLD NEXT signals assure th NEW_DZ (i.e., STA minus LTA) does not exceed DZ,,,,,, as described in the definiti of LSTA hereinabove. A single bit latch 300 receives an output signal on line 302 from subtracti circuit 250. If subtracting circuit 250 determines that the NEW_STA value from li 225 is greater than the NEW_LTA value on line 227, the output sign DISABLE_URDIFF from latch 300 is asserted. The signal DISABLE JRDIFF is o of the inputs to OR gate 218. When LSTA is less than LTA, DISABLE_URDIFF asserted; this effectively disables the UR_DIFF clipping function, since the DM stream on line 88 cannot be prevented from propagating through AND gate 206 wh DISABLEJJRDIFF is asserted.

From the foregoing detailed description of a specific embodiment of the inventio it should be apparent that a rate-responsive pacemaker has been disclosed which capable of automatically adjusting its pacing rate in response to changes in min ventilation as measured by transthoracic impedance. While a particular embodiment the present invention has been disclosed in detail, it is to be understood that this has be done for illustrative purposes only, and should not be taken as a limitation upon t scope of the present invention. It is contemplated by the inventors that vario alterations, substitutions, and modifications to the disclosed embodiment may be ma without departing from the spirit and scope of the invention as set forth in the append claims.

For example, while the present disclosure relates to a single chamber pacema which would operate in the VVIR or AAIR mode, the invention is also equally applica to dual chamber pacemakers of all types, including DDDR, DDIR, VDDR, and DV type pacemakers. In such embodiments, the interval to be varied may be the interval between atrial pacing pulses (DVIR and DDDR), the interval between ventricular pacing pulses (DDDR, DDIR, VDDR and DVIR), or the interval between a ventricular pulse and the next subsequent atrial pacing pulse (DDDR, DDIR, and DVIR). Moreover, the present invention is also believed to be useful in the context of multiple sensor pacemakers, in which the pacing rate is determined by a plurality of measured physical parameters. Li such embodiments, the desired rate-responsive pacing interval for one sensor might be combined with the desired rate-responsive pacing interval for another sensor by weighted or unweighted averaging or by other methods.

Rate Response Programming

The mapping of the DZ values to pacing rates as shown in Figures 4a through 4d is the impedance pacing rate response (RR). The following two interactive protocols can be used to optimize the RR for each patient:

Breathing Protocol: This protocol provides an approximation of the maxima respiration by observing the DZ values during 10 seconds of maximal breathing.

During the breathing protocol the patient is instructed to take maximal breaths during a 10 second countdown. TheDZ counts that result are loaded into the upper bits of the USTA. At the completion of the 10 second countdown, the value is stored in th

MAXDZ register and uplinked to the programmer. The programmer then uses a look-u table to recommend an appropriate value for DZ RR.

Exercise Protocol: This protocol provides optimization of the RR based on th MAXMV value produced during exercise.

At the beginning of the protocol, the previous MAXMV value is cleared. Th patient is then instructed to perform an appropriate level exercise for a minimum of minutes. During the protocol the MAXMV register records the peak DZ value. At th completion of the protocol the MAXMV value is uplinked and the programmer then use a look-up table to recommend an optimal value for RR.

Thus, the present specification should be regarded as exemplary, rather tha limiting in nature, with regard to the following claims.

Claims

WHAT IS CLAIMED IS:

1. A pacemaker, enclosed within a housing, comprising:

a pulse generator electrically coupled to a patient's heart via a cardiac lead, an coupled to a rate control circuit, said pulse generator responsive to triggering signal from a rate control circuit to generate a pacing pulse;.

said rate control circuit producing triggering signals at a rate varying betwee predetermined upper and lower pacing rates;

an activity sensor coupled to said patient, producing an output signal indicati of patient activity;

an impedance circuit, coupled to said heart via said cardiac lead and coupled a ΔZ processor, said impedance circuit producing an impedance volta waveform corresponding to changes in impedance in said heart;

said ΔZ processor periodically sampling said impedance voltage waveform a in response to each said sample producing a serial bit stream outp signal, the number of logical '1' bits (hereinafter referred to as 'counts in said bit stream output signal corresponding to a change in sa impedance voltage waveform;

said rate control circuit receiving said bit stream output signal, and responsive said bit stream output signal to count said counts occurring during plurality of successive two-second intervals and to calculate the followi values: LTA (Long-Term Average): an average count, over a predetermined long-term interval, of said counts occurring in each two-second portion of said long- term interval;

LSTA (Limited Short-Term Average): an average count, over a predetermined short-term interval, of said counts occurring in each two-second portion of said short- term interval, where said rate control circuit constrains said LSTA value to a range determined by said predetermined upper and lower pacing rates;

DZ (Limited Positive Difference): a value representing a comparison of LSTA and LTA, defined as

0 : LSTA < LTA _DZ = {LSTA-LTA : O≤ (LSTA- LTA) ≤DZ_H

DZ_m : LSTA-LTA ≥DZ m_^m,

where DZ_^ is a predefined upper limit on said DZ value and where said rate control circuit producing triggering pulses at a rate determined as a function of said DZ value.

2. A method of pacing a patient's heart, comprising the steps of:

(a) producing an impedance waveform corresponding to changes in impedance in said heart; (b) delta-modulating said impedance waveform at a predetermined sampling rate to produce a serial output bit stream, such that for first and second successive samples, said output bit stream after said second sample comprises a sequence of N logical '1' bits (hereinafter referred to as 'counts'), where N reflects a change in said impedance waveform betwee said first and second samples;

(c) computing an LTA (Long-Term Average) value representing an averag count, over a predetermined long-term interval, of counts occurring durin each two-second portion of said long-term interval;

(d) computing an LSTA (Limited Short-Term Average) value representing a average count, over a predetermined short-term interval, of count occurring in each two-second portion of said short term interval;

(e) computing a DZ (Limited Positive Difference) value, representing comparison of said LTA and said LSTA values, according to the formul

0 : LSTA < LTA

DZ = LSTA- LTA : O ≤ (LSTA- LTA) ≤DZ_n

DZ__ : LSTA-LTA ≥DZ__

where DZ_^ is a predefined upper limit on said DZ value; (f) delivering cardiac pacing pulses to said heart at a rate determined as function of said DZ value.

3. The method of claim 2 further comprising: (a) initializing said DZ (Limited Positive Difference) value to zero; and

(b) initializing said pacing rate to a lower rate (LR).

4. The method of claim 3 further comprising:

(a) energizing a delta-modulator for a predetermined loading period and (b) loading output counts during said loading period from said delt modulator into said LTA (Long-Term Average) value and into said LST (Limited Short-Term Average) value.

5. The method of claim 4 further comprising:

(a) interrogating said LTA (Long-Term Average) value with programmer; and

(b) calculating an analog gain range value for said delta-modulator.

6. The method of claim 5 further comprising:

(a) setting gain range value to a first gain range if said LTA value is less than or equal to a mid-range value of said delta-modulator counts; and

(b) setting said gain range value to a second gain range if said LTA value is greater than a mid-range value of said delta-modulator counts, said second gain range being a greater gain range value than said first gain range.

7. The method of claim 6 further comprising: adjusting said gain range value to a third gain range if said LTA value is greater than a mid-range value determined after said gain range value has been set at said second gain range, said third gain range being a greater range value than said second gain range.

8. The method of claim 7 further comprising: adjusting said gain range value to a fourth gain range if said LTA value is greater than a mid-range value determined after said gain range value has been set at said third gain range, said fourth gain range being a greater range value than said third gain range.

9. A pacemaker, enclosed within a housing, comprising: a pulse generator electrically coupled to a patient's heart via a cardiac lead, and coupled to a rate control circuit, said pulse generator responsive to a triggering signal from a rate control circuit to generate a pacing pulse; said rate control circuit producing triggering signals at a rate varying between predetermined upper and lower pacing rates; an activity sensor coupled to said patient, producing an output signal indicative of patient activity; an impedance circuit, coupled to said heart via said cardiac lead and coupled to a ΔZ processor, said impedance circuit producing an impedance voltage waveform corresponding to impedance in said heart; said ΔZ processor periodically sampling said impedance voltage wavefor and in response to each said sample producing a serial bit stieam output signal the number of logical '1' bits (hereinafter referred to as 'counts') in said bi stream output signal corresponding to a change in said impedance voltag waveform; said rate control circuit comprising an LTA circuit, receiving said bi stream output signal and responsive to said bit stream output signal to comput an LTA value corresponding to an average count, over a predetermined long-ter interval, of said counts occurring in each two-second portion of said long-ter interval; said rate control circuit further comprising an LSTA circuit, receiving sai bit stream output signal and responsive to said bit stream output signal to comput a LSTA value corresponding to an average count, over a predetermined short term interval, of said counts occurring in each two-second portion of said shor term interval, where said rate control circuit constrains said LSTA value to range determined by said predetermined upper and lower pacing rates; said rate control circuit further comprising a DZ circuit, receiving sai LSTA and said LTA values and computing a DZ value according to

0 : LSTA < LTA

DZ ~ LSTA-LTA : O ≤ (LSTA- LTA) ≤DZ_m

DZ_^ mm : LSTA- LTA ≥DZ m_mm_m

where DZ^, is a predefined upper limit on said DZ value;

said rate control circuit producing triggering pulses at a rate determine as a function of said DZ value.

10. An implantable cardiac pacemaker, comprising: a pulse generator, coupled to a patient's heart via a pacemaker lead, said pulse generator responsive to a pacing trigger signal to deliver pacing pulses to said heart; a minute volume circuit, comprising an impedance circuit coupled to a second target pacing rate computing circuit, said minute volume circuit responsive to an impedance signal from said impedance circuit to compute a first target pacing rate value as a function of said impedance signal; an activity circuit, comprising an activity sensor coupled to a first target pacing rate computing circuit, said activity circuit responsive to an activity signal from said activity sensor to compute a second target pacing rate value as a function of said activity signal; a rate control circuit, coupled to said activity circuit, said minute volume circuit, and said pulse generator, said rate control circuit responsive to signals representing said first and second target pacing rate values to issue a pacing trigger signal at a moment in time determined as a function of said first and second target pacing rate values.