WO1993020514A1

WO1993020514A1 - Self-controlled write back cache memory apparatus

Info

Publication number: WO1993020514A1
Application number: PCT/US1993/003270
Authority: WO
Inventors: Tim Y. T. Lau
Original assignee: Video Technology Computers, Ltd.; Vtech Computers, Inc.
Priority date: 1992-04-07
Filing date: 1993-04-06
Publication date: 1993-10-14
Also published as: AU4279793A

Abstract

A self-controlled microcomputer write back cache memory apparatus (100) for the controlled storage of digital data in a high speed microcomputer (101) including memory means (107) for storing digital data in the form of cache lines, comparator means (110) for determining whether the data requested by the CPU is present in the memory means, cache controller (101) means for generating control signals otherwise produced by the CPU (101) toward producing a memory write cycle and buffers (106 and 111) to facilitate the controlled storage of the digital data. The apparatus (100) is connected between the CPU (101) and the main memory (102) of the microcomputer and serves to intercept CPU requests for data from the main memory (602), interrupt the CPU (101) and independently control the control bus (133), address bus (104) and data bus (105) within the microcomputer toward manipulating and storing digital data between the CPU (101) and the main memory (102).

Description

Title Of Invention;

Self Controlled Write Back Cache Memory Apparatus

Technical Field

The present invention relates generally to- the control and storage of digital data in a high speed microcomputer system, and in particular, to a self- controlled "write back" cache memory system capable of interrupting the central processing unit (CPU) and controlling the system bus.

BACKGROUND ART

There are a number of alternatives for storing computer programs and data for use in computers each of which typically differ in complexity, cost, access time, access mode and volatility. One of the earliest forms of storage, punched cards, was tech¬ nologically simple, inexpensive, and permanent. Access to a given element of data stored on punched cards typically required on the order of 10 seconds. A subsequent generation of digital storage was magnetic tape which was usually on the order of three times faster than punched cards. However, the data stored on magnetic tape could only be accessed in a predetermined sequence resulting in diminished performance with increase memory size. Today, semiconductor memory devices can randomly access data in nanoseconds. The increased speed of these random-access memories (RAM's) is achieved as a result of increased cost and complexity.

There are two major types of random-access memories (RAM's), static and dynamic. All RAMs are composed of arrays of storage cells, each independ¬ ently accessible for read and/or write operations. Static RAMs (SRAMs) and dynamic RAMs (DRAMs) differ in the type of storage cells utilized. Each cell of an SRAM is a flip-flop device, where as DRAM cells are capacitance devices. Because the electrical charge stored on capacitance devices decays with time, DRAMs need to provide a "refresh" cycle be¬ tween memory access operations and thus possess slower access times than their static counterpart. However, "faster" SRAM cells require more transis¬ tors than their dynamic cousins, which makes each cell larger and more expensive to produce.

Initially, microprocessors did not have the need to have access to memory much faster than DRAMs were able to supply it. However, as the speed of microprocessors has continued to increase over the past years, and especially in view of today's high speed 80386 and 80486 microprocessor based PC's, the need for a higher performance memory has become necessary. While, a total shift to SRAMs is possi¬ ble, such expense is unnecessary because program execution is likely to be confined to a small ad¬ dress space of the large main memory. Therefore, only a small, high-speed memory which can interact with the large main memory is necessary to achieve higher performance. This small high-speed memory residing between the CPU and main memory is known as a cache. A cache stores the program code or data used most frequently by the microprocessor. When the CPU requests a piece of data from the main memory, this request is intercepted by the cache. If the re¬ quested data has already been loaded into the cache (a "cache hit") then the data can be retrieved from the faster cache memory immediately without having to access the slower main memory. However, if the data is not in the cache (a "cache miss") it is read from the main memory into the CPU and cache simultaneous- ly, with an increased access time.

Cache memory is usually divided into small blocks called "cache lines" containing data and address ("tag") fields and validity bits. The tag field represents a portion of the main memory ad- dress from which the data was copied. Cache memo¬ ries by definition are smaller than the main memo¬ ries they support and two addressing schemes have been used to facilitate quick location of data: direct-mapped and set associative. Direct mapping, based on the predetermined number of cache lines, assigns main memory addresses cache lines contigu¬ ously to the last cache line and then, returns to the first cache line and continues assignment. This cyclical arrangement is mathematically expressed as cache line location = Modulo_NCL(main memory address) (where NCL is the number of cache lines) . Set associative mapping uses the same type of cyclical arrangement, but with sets of cache lines instead of a single cache line. This allows the cache to store more than one "equivalent" main memory location (locations whose Modulo_NCL are equal) , thus minimiz¬ ing the number of cache misses.

Caches also differ in the procedures for writ¬ ing new data to main memory. The "write-through" protocol requires the CPU to transfer the data to both the cache and main memory on every write cycle, even when the targeted address has already been assigned to the cache. This ensures that the cache never differs from the main memory. This method is much slower than the alternate, "write-back" proto- col.

In a "write-back" cache, when data is written to the cache a "dirty bit" is added to each data word. This bit indicates whether the cache data is the same as the main memory data. Where the dirty bit is set, indicating that the cache data and main memory data do not match, then the high impedance buffer is closed and the cache performs a DRAM write cycle, writing the cache data into main memory. Where the dirty bit is not set, CPU write cycle results in new data in the cache and a setting of the dirty bit. The main memory is not affected by this process.

Presently^', most standard "write back" cache memories rely on high impedance buffering to isolate the cache and main memory from the CPU during write back cycle. The major shortcoming of some current "write back" caches is the use of these high imped¬ ance buffers to isolate the cache data from the CPU data during a CPU write cycle. The introduction of these buffers increases the delay in this crucial path in CPU read and write cycles, thus increasing the CPU wait states. This added delay make these cache implementations unpractical at higher CPU speeds. In fact, at very high speed operations, it may be impossible to add a buffer between the CPU and the cache. While, "write through" caches avoid this buffer by simultaneously writing to both the cache and main memory, this method reintroduces the wait states inherent in DRAM write cycles, a limita¬ tion the SRAM cache is intended to avoid.

Another limitation in some current "write back" caches is the "slave" nature of the devices. These cache controllers are dependent on the CPU to con- trol, or "master", the bus for all of the cache's external operations. This requires the CPU to allo¬ cate processor time to manage data and address buses during cache write back cycle.

Another limitation in some current "write back" caches is the complexity of DRAM memory controller design due to the introduction of write-back cycles which differ from the CPU write cycle.

Accordingly, it is an object of the present invention to decrease delay in the memory data path by eliminating the use of high impedance buffers to isolate the memory devices (DRAM and SRAM) from the CPU during cache write back cycles by providing a cache controller which can master the control, data and address busses during write back cycles. Another object of the invention is to place the cache memory data bus on the CPU data bus allowing the cache controller to perform cache write back cycles during all CPU cycles, including memory read and write thereby allowing increased performance of the overall system.

It is a further object of the present invention to provide a cache controller which is "transparent" to the main memory controller such that it only "sees" the CPU interface by omitting a special cache write back cycle making the design of the main memory controller less complex.

It is an associated object of the present invention to provide better system reliability through simplification of the cache and DRAM cir- cuitry and elimination of the high impedance buff¬ ers, due not only to the master device nature of the present invention, but also the implementation of a cache with direct mapping.

These and other objects of the invention will become apparent in light of the present specifica- tion and drawings.

Disclosure Of The Invention

In operation, the present invention operates to write back data from the cache to the main memory as follows. During a write back cycle, where data is written from the cache memory to the main memory, the cache controller acts as a multi-processor device. The cache controller first requests the CPU to release the address and data buses by asserting the BOFF signal to the CPU. At the same time as the BOFF signal is asserted the cache controller latches the physical address that needs to be written back. After the CPU releases its buses, the cache control¬ ler will take control of the CPU, the control, address and data buses. The cache controller will act as the CPU to perform the following functions: 1) generate and assert the appropriate control signals otherwise generated by the CPU to produce a memory write cycle, 2) gate the latched address for the write back cycle onto the CPU address bus, and 3) gate the cache memory data which need to be written back to the main memory onto the CPU data bus.

After the cache controller receives the appro¬ priate signal from the DRAM controller, indicating that the write cycle to DRAM has completed, it will repeat the foregoing steps until all data has been written back to the main memory.

The cache controller will update the dirty bits in the cache memory to indicate that the line is clear. The cache controller will then inform the CPU to restart its last bus cycle by negating the BOFF signal.

As can be seen, the present invention differs from the prior art write back cache in that the cache controller acts as a master device during the cache write back cycle. In addition, the cache memory data bus is situated on the CPU data bus which provided for very high speed operation such that the cache controller can perform cache write back cycles during all CPU cycles (which includes memory read and memory write operations) . In situa¬ tions where the cache memory sits on the CPU data bus, the conventional write back cache cannot per- form write back cycle during a CPU memory write cycle, i.e., it cannot write directly to the cache memory during a cache miss write cycle. Since the new high performance CPU's include internal cache memory, up to 70 percent of the CPU memory bus cycles are memory write. The performance of the CPU system will be decreased if the external cache cannot perform cache miss write allocation. More¬ over, the main memory controller (DRAM controller) sees only the CPU interface, so the control logic does not have to implement the special write back cycle.

Brief Description Of The Drawings

Fig. la of the drawings is a simplified block diagram of the SELF-CONTROLLED "WRITE BACK" CACHE MEMORY APPARATUS shown comprising the inter- connection of cache memory, tag cache, status cache, comparator, cache controller, and address bus write back buffer and their connection to the CPU and main memory;

Fig. lb of the drawings is a block diagram of cache line representation of data storage in the present invention;

Fig. lc of the drawings is a block diagram of the address bus;

Fig. Id of the drawings is a timing dia- gram of a Cache Write Back cycle of the present invention;

Figs. 2A and 2B of the drawings together comprise a block diagram of the status cache, tag cache and comparator of the present invention; Figs. 3A and 3B of the drawings together" comprise a block diagram of a portion of the cache controller of the present invention specifically illustrating the validity bit processor, SRAM write enable controller, CPU hold acknowledge controller, and cache read and DRAM buffer controller;

Figs. 4A and 4B of the drawings together comprise a block diagram of a portion of the cache controller of the present invention specifically illustrating the write back cache control signal generator, write back cache control signal decoder, and dirty bit processor;

Figs. 5A and 5B of the drawings together comprise a block diagram of the address bus write back buffer of the present invention specifically illustrating the bus simulation buffers used by the present apparatus during cache write back cycles;

Figs. 6A and 6B of the drawings together comprise a block diagram illustrating the cache memory of the present invention shown comprising two of the four BURST SRAM ICs;

Figs. 7 and 8 of the drawings are logic diagrams representing the logic performed by the validity bit processor of the present invention;

Figs. 9a and 9b of the drawings are logic diagrams representing the logic performed by the cache memory write enable controller of the present invention;

Fig. 10 of the drawings is a logic diagram representing the logic performed by the DRAM buffer output enable controller of the present invention;

Figs. 11 through 13 of the drawings are logic diagrams representing the logic performed by the cache read controller of the present invention; Figs. 14 through 19 of the drawings are logic diagrams representing the logic performed by the write back signal generator of the present invention;

Fig. 20 of the drawings is a logic diagram representing the logic performed by the tag write controller of the present invention;

Figs. 21 through 28 of the drawings are logic diagrams representing the logic performed by the write-back signal decoder of the present inven- tion; and

Figs. 29 through 33 of the drawings are logic diagrams representing the logic performed by the dirty bit controller of the present invention. Best Mode For Carrying Out The Invention

While this invention is susceptible of embodi¬ ment in many different forms, one specific embodi¬ ment is shown in the drawings and will herein be described in detail with the understanding that the present disclosure is to be considered as an exem¬ plification of the principles of the present inven¬ tion and is not intended to limit the invention to the embodiment illustrated. Fig. IA of the drawings is a block diagram of the functional stages of the SELF-CONTROLLED "WRITE BACK" CACHE MEMORY APPARATUS 100 and is shown as comprising CPU 101, main memory DRAM 102, data buffer 103, cache controller 106, cache memory 107, tag cache 108, status cache 109, comparator 110 and address bus write back buffer 111. Apparatus 100 is designed to be utilized in a personal computer system with a high performance CPU 101 and main memory DRAM 102. CPU 101 is illustrated as being of the type which is interruptible through application of BOFF/ signal 126. BOFF/ signal 126 when applied to CPU 101 causes CPU 101 to "back off" the bus, terminating its current cycle on the bus. When BOFF/ signal 126 is removed, the "terminated" cycle is restarted. As shown in Fig. IA, apparatus 100 in eludes a number of components which track and store information and data accessible to main memory 102 for use by CPU 101..

In the present invention, the cache memory is divided into blocks called "cache lines", illustrat¬ ed in Fig. IB, which is the smallest unit that can be allocated to physical memory at one time. Digi¬ tal data which passes through apparatus 100 is manipulated and stored on the basis of the contents of cache lines, each containing four 32-bit data words, an 8-bit tag, and a status word comprising four validity bits (one for each data word) and four dirty bits (one for each data word) . A portion of each cache line is stored in one of three different components of apparatus 100, namely cache memory 107, tag cache 108, and status cache 109.

Cache memory 107 is composed of four 32K x 9 bit BURSTRAM type synchronous SRAM chips (MCM62486) manufactured by MOTOROLA which store the data word portion of the cache lines. The BURSTRAM SRAM is used because it supports self-timed writes and incorporates an internal burst sequence counter. While the BURSTRAM SRAM simplifies the external logic needed to drive cache memory 107, apparatus 100 can make use of standard SRAM for cache memory 107 through the use of additional external logic known to those with ordinary skill in the art.

Tag cache 108 and status cache 109 are 8K x 8 bit SRAMs which store the status word for each cache line. Tag cache 108 stores the tag portion of the cache line. The "tag" is a subset of the most significant bits of the main memory address of the four data words in the corresponding cache line. In the preferred embodiment, the tag comprises the eight most significant bits (PA24-PA17 113) of the 21-bit address used by main memory 102. Status cache 109 stores one validity and one dirty bit for each of the four data words in the cache line. The validity bit indicates that the associated word is valid. The dirty bit indicates that the associated data word was written from CPU 101 only into cache memory 107, that it is not present in main memory 102, and therefore that the data needs to be writ- ten back to main memory 102 under certain circum- stances .

The information stored in cache memory 107, tag cache 108, and status cache 109 is referenced and correlated using bits 2 - 16 of the address bus, designated as PA2-16 112a (and referred to herein as "ADDR-A" 112a) and bits 4 - 16 of the address bus, designated as PA4-16 112b (and referred to herein as "ADDR-B" 112b) . ADDR-A 112a is the third through seventeenth bits of the address on address bus 104 and is therefore associated to the data words on data bus 105. ADDR-B 112b contains only the fifth through seventeenth bits of address bus 104. ADDR-A 112a is used to address all 32,768 32-bit words available in cache memory 107. The four 32 bit data words comprising each cache line are stored in four contiguous memory locations in cache memory 107. Since each addressable line in tag cache 108 and status cache 109 stores the control information for the entire cache line (i.e. the four data words) , tag cache 108 and status cache 109 will need to access the same control information for each set of four locations in cache memory 107. Thus, the two least significant bits, PA2 and PA3, are unnecessary to tag cache 108 and status cache 109 such that these components can be addressed with ADDR-B 112b.

Comparator 110 is a standard 8-bit comparator whose output is low when the two 8-bit inputs are identical and in the present invention comprises a 74FCTX521B type device manufactured by IDT. Compa¬ rator 110 accepts as inputs PTAG 114 which comprises the eighteenth through twenty fifth bits of the address bus saved in tag cache 108 in a past cycle and CTAG which is the current value of PA17-24 113 from address bus 104 toward effectively comparing the current tag to the past tag value so as to determine whether there has been a cache hit . Whether there has been a cache hit is reflected by the value of TAGMACH/ 115 which is , in turn, fed into cache controller 106 which thus senses whether a cache hit has occurred. The TAGMACH signal is generated by cache controller 106 and is the match signal pin of comparator 110. It indicates whether the current CPU cycle is in the cache. Address bus write back buffer 111 is used during cache write back cycles to simulate address bus 104 and various control signals found on control bus 133 . Address bus write back buffer 111 is composed of three octal D-type transparent latches and one octal buffer with tri-state outputs , such as 74F373 and 74F244 , respectively. The assertion of BOFF/ 126 backs CPU 101 off address bus 104 and control bus 133 causing these busses to float as long as BOFF/ 126 is asserted. Address bus write back buffer 111 transmits the necessary signals generated by cache controller 106 toward manipulat¬ ing the main memory 102 and CPU 101 by grounding some signals , tying others to Vcc, latching the desired address (ADDR-A 112a plus PTAG 114 ) onto the bus , and passing BOFF_ADS/ signal 201 out on to control bus 133 which used to regenerate ADS/ 120 for cache memory 107 such that it can output data words to data bus 105 during the write back cycle.

Cache controller 106 in the present invention is composed of six preprogrammed programmable logic arrays which implement the major functions of appa¬ ratus 100 , namely, controlling address bus 104 ; data bus 105 ; data buffer 103 ; and main memory 102 during cache write back cycles . The specific logic func- tions performed by cache controller 106 are de- scribed with reference to Figs . 7 through 33 using logic diagrams which represent the functions pro- grammed into the various programmable logic arrays of apparatus 100. Generally, cache controller 106 operates to update status information contained in tag cache 108 and status cache 109 ; controls reading from and writing to cache memory 107 ; and masters the system buses , including address bus 104 , control bus 133 and data bus 105 . TAGWR/ signal 116 generated by cache controller 106 controls the writing of CTAG 113 to tag cache 108 and the writing of validity bits 117 and dirty bits 118 to status cache 109 . CACHE_0E/ s ignal 119 ; ADV/ s ignal 121 ; and WE/ signal 122 control the output and write enabling of cache memory 107 . BOFF_BUF_EN/ signal 123 enables Address bus write back buffer 111 to drive address bus 104 , control bus 133 , and data bus 105 , when BOFF/ signal 126 is asserted on CPU 101 by cache controller 106. BUFFEN/ signal 125 controls the flow of data through data buf f er 103 which is shown connected between data bus 105 and main memory 102 . BUFFEN is derived from the buffer output enable pin of DRAM memory 102 and is an active low signal . B0FF_ADS/ signal 201 regenerates ADS/ signal 120 on control bus 133 which times cache memory 107 data output onto data bus 105 . The interrelation of these and other signals will become clear in light of the following description of the operation of apparatus 100.

In operation, when CPU 101 accesses memory, the command is intercepted by apparatus 100 . Cache controller 106 using TAGMACH/ signal 115 from compa¬ rator 110 , validity bits 117 and dirty bits 118 from status cache 109 determines whether the current cycle is a: (1) CPU cache hit read; (2) CPU cache miss read; (3) cache-master cache hit read; (4) CPU cache hit write; (5) CPU cache miss write; or (6) cache-master cache hit write, in accordance with the pattern shown in Table 1.

"xx" — doesn't affect cycle selection

Table l: conditions for potential cycles of apparatus 100

CPU Cache Hit Read

A CPU Cache Hit Read cycle occurs when CPU 101 is reading from a memory location which has already been allocated to the cache which is indicated when CTAG 113 from address bus 104 is equal to PTAG 114 from tag cache 108 addressed by ADDR-B 112b (cache hit) , and validity bits 117 addressed by ADDR-B 112b are also set. The status of the dirty bits 117 is ignored as it is irrelevant whether the addressed dirty bits 118 are set because read operations are non-destructive.

Once cache controller 106 determines that the cycle is a CPU hit read cycle, main memory 102 is inhibited from activating (through assertion of NO_DRAM/ signal 172) because the data is available in cache memory 107 which can be accessed from the faster cache memory 107 without having to access the slower main memory 102 and thus satisfying CPU 101's request. From the beginning of the cycle, the address indicated by CPU 101, ADDR-A 112a, is avail¬ able at the address pins of cache memory 107 so the requested data is output onto data bus 105 by cache memory 107 as soon as cache controller 106 enables its outputs by asserting CACHE_OE/ 119. There has been no alteration of the data in cache memory 107 so there is no need to update tag cache 108 and status cache 109 as this is a read cycle.

CPU Cache Miss Read

A CPU cache miss read cycle occurs when CPU 101 is reading from a main memory location which has not yet been allocated in the cache as indicated when CTAG 113 from address bus 104 is not equal to PTAG 114 from tag cache 108 as addressed by ADDR-B 112b and dirty bit 118a through 118d from status cache 109 as addressed by ADDR-B 112b are not set. Be¬ cause there was a cache miss, cache controller 106 determines whether the cache data, which would be destroyed by writing the new data from main memory 102, needs to be written back to main memory 102. Accordingly, the status of dirty bits 118 is rele¬ vant in this case because the data which CPU 101 will obtain from main memory 102 (because it is not in cache memory 107) will also be written into cache memory 107 by cache controller 106. In this case, the data in cache memory 107 at the location identi- fied by ADDR-B 112b is either invalid or not dirty, such that no write back is necessary and apparatus 100 waits, passively monitoring control bus 133 for valid data on data bus 105. While determining the cycle type and waiting for the data from main memory 102, ADDR-A 112a is available at the address pins of cache memory 107, such that once valid data is available on data bus 105 cache controller 106 asserts WE/ 122 storing the data in cache memory 107 at the address indicated by ADDR-A 112a as clocked by ADS/ 120 which is generated by CPU 101. At the same time, cache controller 106 asserts TAGWR/ 116 which causes tag cache 108 to store CTAG 113 and status cache 109 to store the new validity bits 117 and dirty bits 118 generated by cache controller 106 at the address indicated by ADDR-B 112b.

Cache-Master Cache Hit Read

A Cache-Master Cache Hit Read cycle occurs when CPU 101 is attempting to read a memory location which can not be read from cache memory 107 (a cache miss) and where the apparatus 100 would thus write the data read from the address sought to be accessed by CPU 101 to cache memory 107; and where cache memory 107 contains data from a different address which has not yet been written to main memory 102; and where writing to that address in cache memory 107 would result in the loss of data previously stored in cache memory 107 if it is not first writ- ten back to main memory 102 before the intended address is read from memory.

During a write back cycle, data is written from cache memory 107 to main memory 102. Cache control- ler 106 acts as a microprocessor device mastering control bus 133, address bus 104, data bus 105, main memory 102, and CPU 101 by asserting BOFF/ 126. Timing in write back operation is crucial to insure proper transfer of data by apparatus 100, so refer- ence should also be had to Fig. ID in association with the following paragraphs.

In operation, CPU 101 will have latched an address onto address bus 104 and set W/R 160 LOW to indicate that it wishes to read from the main memory location designated by the signals on address bus 104. The control logic in Apparatus 100 views this address as ADDR-B 112b and CTAG 113 which is used to access PTAG 114 from tag cache 108 and compare it with CTAG 113 in comparator 110 resulting in TAGM- ACH/ 115 which if HIGH, as shown at marker 135, indicates that a cache miss has occurred. ADDR-B 112b is also used to access the associated set of dirty bits 118 which are fed into cache controller 106 resulting in the generation of DIRTY signal 197 by dirty bit processor 192. In this case, DIRTY signal 197 is HIGH indicating that the data current¬ ly in cache memory 107 needs to be written back to main memory 102. TAGMACH/ 115 HIGH and DIRTY 197 HIGH causes write back cache controller 191 to generate BOFF_REQ/ 158 shown at marker 135 in Fig. ID, indicating to write back cache signal generator 190 the need to assert BOFF/ 126. BOFF/ 126 is asserted, as shown at marker 136 in Fig. ID, by write back cache signal generator 190 on CPU 101 causing the CPU to release the bus. BOFF/ 126 also causes BOFF_BUF_EN/ 123 to go LOW thus enabling address write back cache buffer 111 to drive the system buses for the write back operation. BOFF_REQ originates with cache controller 106 and is the BOFF request signal, or write back request signal and is active low.

The assertion of BOFF/ 126 also generates BOFF_ADS 201 which is fed through address write back bus 111 out onto control bus 133 as ADS/ 120 and is used to time cache memory 107 during the write back operation. At this point ADS/ 120 is clocking cache memory 107 so that it can write the data stored in ADDR-A in cache memory 107 back to main memory 102. Since W/R 160 is HIGH, main memory 102 interprets ADS/ 120 as a CPU write cycle causing the data currently on data bus 105, which was latched from cache memory 107 when CACHE_OE/ 119 was asserted to be written into the main memory location indicated by ADDR-A 112a plus PTAG 114 which is latched onto address bus 104 by address write back buffer 111.

Apparatus 100 now waits for the DRAMRDY/ 127 signal to indicate that main memory 102 has complet¬ ed writing the data to main memory 102. As shown in Fig. ID at marker 138, cache controller 106 completes a total of four write cycles to main memory 102 after which cache controller 106, specif¬ ically, dirty bit processor 192, which clears DIRTY 197. Write back cache controller 191 then asserts TAG_WR_REQ/ 179 to cause write back cache signal generator 190 to generate TAGWR/ 116 causing new dirty bits 118 to be written to status cache 109. TAG_WR_REQ is the tag write request signal to ac¬ knowledge cache controller 106 that the memory cycle needs to update the tag memory. This is an active low signal. The assertion of TAGWR/ signal 116 by write back cache signal generator 190 causes BOFF/ 126 to return to the non-asserted HIGH position shown by marker 137 thus releasing the system buses back to CPU 101. At this point CPU 101 will restart the aborted read cycle, and since the cache line is no longer dirty, (this will act like a cache miss read) the data read from main memory 102 is written into cache memory 107 in a CPU Miss Read cycle. Validity bit processor 150 also clears validity bits 117 after the write back cycle has been completed which would then be loaded into status cache 109 along with dirty bits 118. DRAMRDY originates with DRAM 102 and is the DRAM ready output from the DRAM controller. This is to inform CPU 101 or cache controller 106 that the present DRAM cycle is fin¬ ished. The signal is active low. DRAMRDY is active only if TRANS_REF is not active. DRAMRDY will force low if transparent refresh is active, so DRAMRDY in some cases should gate with TRANS_REF.

CPU Cache Hit Write

A CPU Cache Hit Write cycle occurs when CPU 101 is writing to a memory location which has already been allocated to the cache which is indicates when CTAG 113 from address bus 104 is equal to PTAG 114 from tag cache 108. In this case, it is irrelevant whether validity bits 117 and/or dirty bits 118 are set because this CPU operation is meant to alter the contents of the main memory location in the first place, so the alteration of cache memory 107 saves having to perform a write back operation which would only be overwritten later by the future write back cycle needed to place the data currently on data bus 105 from cache memory 107 into main memory 102. Once cache controller 106 determines that the cycle is a CPU hit write cycle, the data on data bus 105 is written to cache memory 107, tag cache 108 stores CTAG 113 and status cache 108 stores validity bits 117 and dirty bits 118. During the cycle determination, ADDR-A 112a is available at the address pins of cache memory 107 and the data is available at its data pins. Thus, once cache con¬ troller 106 asserts WE/ signal 122 the data is stored at the address indicated by ADDR-A 112a as clocked by ADS/ 120 which is generated by CPU 101. If validity bit 117 or dirty bit 118 need to be set, cache controller 106 asserts TAGWR/ 116 which stores CTAG 113 in tag cache 108 and validity bits 117 and dirty bits 118 in status cache 109 at the address indicated by ADDR-B 112b. Validity bits 117 and Dirty bits 118 are set because the data is stored directly in cache memory 107. Tag cache 108 is rewritten even though PTAG 114 is already equal to CTAG 113, because parallel writing to tag cache 108 and status cache 109 results in a simpler design. As status cache 109 must be rewritten (unless dirty bit 118 is already set) , no additional time is required for this parallel write to tag cache 108.

CPU Cache Miss Write

A CPU Cache Miss Write cycle occurs when CPU 101 is writing to a memory location which has not yet been allocated in the cache which is indicated when CTAG 113 is not equal to PTAG 114 from tag cache 108 location ADDR-B 112b and dirty bits 118 from status cache 109 are not set. The dirty bit is checked in this case, because the data to be written to cache memory 107 is for a different main memory location than the data currently in cache memory 107, even though they have identical ADDR-A 112a. (In the present embodiment with an 8-bit tag, 256 main memory locations will have identical ADDR-A 112a.) The status of validity bits 117 is irrele¬ vant because the data will be overwritten by the current cycle, however, if the data is invalid, the status of dirty bits 118 is irrelevant because the data is not valid and therefore is not written back to main memory 102.

Once cache controller 106 determines that the cycle is a CPU miss write cycle, the process contin¬ ues as it did in the case of CPU hit write cycle described above. Of course, in this case it is necessary to overwrite tag cache 108.

Cache-Master Cache Hit Write

A Cache Master Cache Hit Write cycle occurs when CPU 101 is writing to a memory location which has not yet been allocated in the cache, but an equivalent main memory location is already in cache memory 107. Where CTAG 113 is not equal to PTAG 114 from tag cache 108 and dirty bits 118 and validity bits 117 are set, the data currently in cache memory 107 must be written to main memory 102 before CPU 101 can write to the cache. This requires a write back cycle which is performed as described above with reference to a cache-master cache hit read cycle.

Apparatus 100 receives control and address signals from CPU 101 and main memory 102 through control bus 133 and address bus 104. M/IO signal 170 is the memory/input-output signal from CPU 101 which indicates that the current CPU cycle is a memory access. W/R signal 160 from CPU 101 signals whether the current memory access is a write or a read. BLAST/ signal 193 from CPU 101 signals the last burst cycle. BEO-BE3 signals 163 are the byte enable outputs of CPU 101 indicating which bytes of data bus 105 are currently valid. BEO-BE3 originate with the byte enable pins of CPU 101. CPUHLDA signal 129 is the CPU hold acknowledge pin which informs the system that CPU 101 is not currently the bus master. CPUHLDA originates with CPU 101 and is the CPU hold acknowledge pin. It is used to indi¬ cate a DMA or bus master mode and is an active high signal. DRAMRDY/ signal 127 from main memory 102 informs the bus master (CPU 101 or apparatus 100) that the DRAM cycle is finished. ADRAMRDY/ signal 128 is the advanced DRAMRDY signal which is generat¬ ed one CPU clock cycle earlier than DRAMRDY/127. ADRAMRDY originates with DRAM 102 and is the ad- vanced DRAMRDY signal. The signal is active during memory read cycles. The signal is generated one CPU clock earlier than the DRAMRDY. This signal is used to update the tag bit information during a burst line fill. Apparatus 100 uses DRAMRDY/ 128 to update tag cache 108 and status cache 109 during a burst line fill. TRAN_REF/ 178 is generated by main memory 102 indicating that the DRAM is currently busy handling a transparent refresh. TRAN_REF originates with DRAM 102 and is the transparent refresh pin of the DRAM controller to inform cache controller 106 that DRAM 102 is doing a transparent refresh. This is an active low signal and will be low in transparent refresh.

Figs. 2A and 2B of the drawings together com- prise a block diagram of tag cache 108, status cache 109, and comparator 110. Tag cache 108 is composed of 8K x 8 bit SRAM 140, inverter 143 (74AS1004) , and an octal buffer 142 (74F244) having tri-state out¬ puts. In the present embodiment, a 7C185 SRAM manufactured by CYPRESS is used. SRAM 140 is ad¬ dressed by ADDR-B 112b which is a subset of address bus 104, as shown in Fig. IC. TAGWR/ 116 controls the functions of SRAM 140 and buffer 142. TAGWR/ 116 is connected directly to the write enable pin of SRAM 140 and the enable pin of buffer 142. TAGWR/ 116 is also connected to the output enable pin of SRAM 140 through inverter 143 which prevents SRAM 140 from being write enabled and output enabled simultaneously. When TAGWR/ 116 is HIGH, buffer 142 is disabled and SRAM 140 outputs PTAG 114 from in SRAM 140 as addressed by ADDR-B 112b. When TAGWR/ 116 is LOW, buffer 142 connects CTAG 113 to the data pins of SRAM 140, designated by PTAG 114, which is then written to SRAM 140 which is write enabled and output disabled.

Status cache 109 consists of 8k x 8 bit SRAM 141 (7C185) and inverter 143 (74AS1004) . Status cache 109 utilizes the same type of SRAM as tag cache 108 in the present embodiment. SRAM 141 is addressed by ADDR-B 112b which is a subset of ad¬ dress bus 104. TAGWR/ 116 is connected directly to the write enable pin of SRAM 141. It is also con¬ nected to the output enable pin of SRAM 141 through inverter 143 which prevents SRAM 141 from being write enabled and output enabled simultaneously. When TAGWR/ 116 is HIGH, SRAM 141 outputs validity bits 117 and dirty bits 118 from the memory location in SRAM 141 addressed by ADDR-B 112b. When TAGWR/ 116 is LOW, validity bits 117 (on pins 11, 12, 13 and 15) and dirty bits 118 (on pins 16, 17, 18 and 19) which are generated by cache controller 106 are written to SRAM 141 which is write enabled and output disabled.

Figs. 3A, 3B, 4A and 4B together illustrate cache controller 106 which is shown comprising validity bit processor 150, SRAM write enable con¬ troller 151, CPU hold acknowledge controller 152, cache read controller 153, write back cache signal generator 190, write back cache controller 191, and dirty bit processor 192. Specifically, Figs. 3A and 3B of the drawings comprise a block diagram of validity bit processor 150, SRAM write enable con¬ troller 151, CPU hold acknowledge controller 152 and cache read controller 153. Validity bit processor 150 is implemented using a programmable logic array which processes validity bits 117; handles all cache related cycles; and clears validity bits 117 after write-back cycles are completed. In the present invention validity processor 150 is a PHILIPS PAL model PLUS 20R4 device with a 20R4-15 device used for 20 MHz CPU's, a 20R4-10 for 25 MHz CPU's, and a 20R4-7 for 33 and 50 MHZ CPU's.

Validity bit processor 150 receives as inputs ADRAMRDY/ 128; validity bits 117; TAGMACH/ 115; CACHEMISS/ 154; BOFF/ 126; L_ ADS/ 155; ALL/ 157; BOFF_REQ/ 158; TAG_WR_REQ/ 179; and 1STCYC/ 171. Validity bit processor 150 creates as outputs valid¬ ity bits 117 and 4DWMACH/ 180. The output enable of validity bit processor 150 is controlled by TAGWR/ ne which is generated by write back cache signal generator 190 (shown in Fig. 4B) . ALL is used to indicate whether cache controller 106 needs to compare the 4 bytes in the cache line. It is active low if the system needs to compare four double words. SRAM write enable controller 151 is implemented using a programmable logic array which controls the writing of all data written to cache memory 107. In the present invention, SRAM write enable controller 151 is a PHILIPS PAL model PLUS 20L8 device with a 20L8-15 device used for 20 MHz CPU's, a 20L8-10 for 25 MHz CPU's, and a 20L8-7 for 33 and 50 MHz CPU's. SRAM write enable controller 151 receives as inputs TAGMACH/ 115; L_ADS/ 155; FAST_M/ 159; D_ADS/ 156; DRAMRDY/ 127; W/R 160; MEM_ACC/ 161; DIRTY 197; BEO- BE3 163; BOFF_REQ/ 164; WB_EN/165; INVALID/ 166; and TRAN_REF/ 178; 4DWMACH/ 180; and TAG_WR_REQ/ 179. L_ADS is one clock delay of the ADS signal and is used to define a write pulse to cache memory 107 during a zero wait state cache write cycle (WRTADS) . L_ADS is active low and is not active during write back cycles and CPUHLDA cycles. FAST_M originates with DRAM 102 and is the memory decoding signal to indicate the memory is a valid cacheable cycle. It is an active low signal. D_ADS is one clock delay of L_ADS if there is no CPU Ready CPURDY detected. It is used to generate a write pulse during non-zero wait state cache write cycles. It is an active low signal. MEM_ACC originates with cache controller 106 and is used to indicate that the present cycle is a valid cachable cycle. It is an active low signal. INVALID is used to indicate that the cycle is a DMA cycle and it need to update the cache, depending on the cache hit or cache miss and is active low.

SRAM write enable controller 151 outputs WEO-3 122 which is connected to the BURSTRAM SRAM chips contained in cache memory 107 to write enable those chips. CPU hold acknowledge controller 152 is an AND gate (74F08) with inputs BOFF/ 126 and CPUHLDA 129 which outputs ACPUHLDA 130. ACPUHLDA 130 is used to disable the CPU hold acknowledge during cache write back cycles. This is necessary because CPU 101 will respond to some "slave" device request signals even while BOFF/ 126 is asserted which may cause a con¬ flict with main memory 102.

Cache read controller 153 is implemented using a programmable logic array which enables data buffer 103 when required; informs the remaining logic of a cache miss; output enables data from cache memory 107; and informs the remainder of cache controller 106 that the current cycle will be completed by apparatus 100. In the present invention cache read controller 153 is a PHILIPS PAL model PLUS 20L8 device with a 20L8-15 device used for 20 MHz CPU's, a 20L8-10 for 25 MHz CPU's, and a 20L8-7 for 33 and 50 MHz CPU's. Cache read controller 153 receives as inputs D_ADS/ 156; BHLDA/ 167; CACHEN 168; 12CYC/ 169; W/R 160; M/IO 170; 1STCYC/ 171; NO_DRAM/ 172; TAGMACH/ 115; BOFF_BUF_EN/ 123; DMA_CACH_RD/ 173; MEM_SLOT/ 174; KEN/ 175; REFRESH/ 176; PA31 184; 4DWMACH/ 180; PA25 183. Cache read controller 153 outputs the following functions: BUFFEN/ 125; CACH- MISS/ 154; CACHE_0E/ 119; and CACRDYEN/ 177. BHLDA is essentially the same as the CPUHLDA signal except that it is a latched version and is used by the system. CACHEN originates with cache controller 106 and is the static signal to enable or disable the cache. It is an active high signal. 12CYC is the first two cycle signal. During DMA, bus master mode, CPU bus idle state, 1st and 2nd CPU cycle, this signal is low. During CPU 3rd cycle to end of cycle, it is high. M/IO is the memory/10 pin from CPU 101. 1STCYC is the first cycle signal. During DMA, bus master mode, CPU bus idle state, 1st CPU cycle, this signal is low. During CPU 2nd cycle to end of cycle, it is high. NO_DRAM originates with cache controller 106 and inhibits the DRAM control- ler from activating, because the data is from cache memory 102. This is an active low signal. DMA_CACH_RD originates with cache controller 106 and enables the buffer enable of cache memory 102 if the present DMA cycle is a cache hit read and dirty bit set. It is used only in DMA or but master mode and is an active low signal. MEM_SLOT is the logic AND'ing of MEMR and MEMW which are, in turn, the memory read and memory write signals from the I/O expansion slot. KEN is the internal cacheable signal to CPU 101 and is active low. REFRESH in¬ forms cache controller 106 that the system is per¬ forming a refresh cycle and is active low. CACRDYEN originates with cache controller 106 and is the cache ready enable control signal to enable or disable the generation of the READY signal to CPU 101. This is an active low signal. Since cache memory 107 is using synchronous SRAM which is ADS related, cache controller 106 has to regenerate only one ADS to cache memory 107 during DMA MEMR or MEMW cycles. Thus, ADS is an active low signal. WEO-WE3 is the cache memory write enable pin outputs origi¬ nating with cache controller 106.

Figs. 4A and 4B of the drawings comprise a block diagram of write back cache signal generator 190, write back cache controller 191 and dirty bit processor 192. Write back cache signal generator 190 is implemented using a programmable logic array which processes requests from write back cache controller 191 to generate signals to the remainder of cache controller 106. In the present invention write back cache signal generator 190 is a PHILIPS PAL model PLUS 20R8 device with a 20R8-15 device used for 20 MHz CPU's, a 20R8-10 for 25 MHz CPU's, and a 20R8-7 for 33 and 50 MHz CPU's. Write back cache signal generator 190 receives as inputs ACPUR- DY/ 131; L_ADS/ 155; ADRAMRDY/ 128; BLAST/ 193; WB_SEL 194; 4DWMACH/ 180; TAGMACH/ 115; P_TERM1/ 202; L_DIRTY/ 203; TAG_WR_REQ/ 179; BOFF_REQ/ 164. Write back cache signal generator 190 outputs BOFF/ 126; BOFF_BUF_EN/ 123; READY_1/ 200; BOFF_ADS/ 201; TAGWR/ 116; and WB_EN/ 165. ACPURDY in normal cycle is the CPU ready signal. During cache write back cycles it is not activated (high) regardless of the CPU ready. WB_SEL is the static signal between a write through and a write back cache. BLAST is the last burst cycle from CPU 101.

Write back cache controller 191 is implemented using a programmable logic array which is responsi¬ ble for determining the current cycle of apparatus 100 and responding to various logic requests. In the present invention Write back cache controller 191 is a PHILIPS PAL model PLUS 20L8 device, with a 20L8-15 device used for 20 MHz CPU's, a 20L8-10 for 25 MHz CPU's, and a 20L8-7 for 33 and 50 MHz CPU's. rite back cache controller 191 receives as inputs CACHEN 168; PA25 183; DWORD/ 195; BIOS/ 196; M/IO 170; W/R 160; BHLDA/ 167; FAST_M 159; TAGMACH/ 115; 4DWMACH/ 180; DIRTY 197; WB_EN/ 165 (enabled upon initialization of CPU 101) BOFF_BUF_EN/ 123; L_DIRTY; 203. Write back cache controller 191 outputs the following functions: TAG_WR_REQ/ 179; B0FF_REQ/ 164; P_TERM1/ 202; NO_DRAM/ 172; READY_0/ 199; MEM_ACC/ 161; MEMR/ 198; and DMA_CACH_RD/ 173. DWORD is the same as the ALL signal. BIOS is the system BIOS memory decode and inhibits cache control- ler 106 to update the cache if the present cycle is a BIOS memory cycle. This is an active low signal. 4DWMACH originates with cache controller 106 and is the four double word match signal. This informs 5 cache controller 106 that the present cycle is burstable and is an active low signal. L_DIRTY originates with cache controller 106 and is the last dirty signal to inform the controller that the write back is about to finish. It is an active low sig- ° nal. DMA is the latched version of MEM_SLOT. P_TERM1 originates with cache controller 106 and is a function of the need to minimize pin counts.

Dirty bit processor 192 is implemented using a programmable logic array which processes dirty bits 5 118. In the present invention dirty bit processor 192 is a PHILIPS PAL model PLUS 20L8 device, with a 20L8-15 device used for 20 MHz CPU's, a 20L8-10 for 25 MHz CPU's, and a 20L8-7 for 33 and 50 MHz CPU's. Dirty bit processor 192 receives as inputs 0 BOFF_BUF_EN/ 123; ACPURDY/ 131; L_ADS/ 155; TAG_WR_REQ/ 179; DIR[0..3] 118; BOFF_REQ/ 164; WB_EN/ 165; ALL/ 157; 1STCYC/ 171; PA2 205; and PA3 204. Dirty bit processor 192 is output enabled by TAGWR/ 116. When TAGWR/ 116 is LOW the DIR[0..3] 5 118 will be output. L_DIRTY/ 203 and DIRTY 197 are always output. DIR[0..3] 118; PA2 205; and PA3 204 are enabled only during cache write back cycles.

Figs. 5A and 5B of the drawings comprise a block diagram of address bus write back buffer 111. 0 Address write back buffer 111 is composed of three octal D-type transparent latches 211, 212 and 213 (74F373) and one octal buffer 214 having tri-state outputs (74F244) . Address write back buffer 111 controls address bus 104 and control bus 133. Octal 5 buffer 210 has tri-state outputs which are connected to control bus 133 and is controlled through BOFF_BUF_EN/ 123 which is generated by cache con¬ troller 106. When BOFF_BUF_EN/ 123 is HIGH, octal buffer 210's output pins are high impedance and do not affect the operation of control bus 133. After cache controller 106 asserts BOFF/ 126, address bus 104 and control bus 133 lines will "float" because apparatus 100 is bus master. BOFF_BUF_EN/ 123 will be set LOW enabling the inputs to octal buffer 210 out onto control bus 133 to drive these floated signals. For all write back operations, some controls signals are constant: BEO-3 216 are set LOW; /C 215 set HIGH (identifying data vs. command such as when addressing external I/O units) ; BLAST/ 193 set LOW; W/R 160 set HIGH; and M/IO 170 is set HIGH. Only B0FF_ADS/ 201, the clock signal used by cache memory 107 during write back cycles, varies during write back cycles. B0FF_ADS/ 201 is generat¬ ed by cache controller 106 and passed through octal buffer 210 out onto ADS/ 120 which is connected to cache memory 107 through control bus 133.

Octal D-type transparent latches 211, 212, and 213 latch ADDR-B 112b and PTAG 114 (PA17-24) into their memories while BOFF/ 126 is changing from high to low. The memory address on these lines when BOFF/ 126 is pulled LOW by cache controller 106 is held by latches 211, 212, and 213 which are is output enabled by BOFF_BUF_EN/ 123 onto address bus 104 when BOFF_BUF_EN/ 123 is pulled LOW. Thus, the main memory address of the data which will be output by cache memory 106 is on address bus 104 which will allow apparatus 100 to write back the cache data into the correct location in main memory 102.

Figs. 6A and 6B of the drawings comprise a block diagram of two of the four BURSTRAM SRAM chips designated 220a and 220b used in cache memory 107. SRAMs 220 are 32k x 9 bit BURSTRAM SRAM manufactured by MOTOROLA (MCM62486) which are used to store the data of the cache line shown is Fig. IB. Because SRAM 220 is only 9 bits wide, four SRAMS are used to store each 32 bit data word, plus parity bits. All four SRAM 220's are addressed by ADDR-A 112a which is a subset of address bus 104, shown in Fig. IC; advanced by ADV/ 121 (as suggested by MOTOROLA product specifications which are publicly available); output enabled by CACHE_OE/ 119; and clocked by ADS/ 120. SRAM 220a receives data bits 0 through 7 and is write enabled by WEO 122a. SRAM 220b receives data bits 8 through 15 and is write enabled by WEI 122b. SRAM 220c (not shown) receives data bits 16 through 23 and is write enabled by WE2 122c. SRAM 220d (not shown) receives data bits 24 through 31 and is write enabled by WE3 122d. Each SRAM also stores one of 4 data parity bits, DPO-3, 221 which were generated by CPU 101 when it wrote the data onto data bus 105. DPO-3 originates with CPU 101 and is the data parity bit of CPU 101.

Figs. 7 and 8 of the drawings are logic dia¬ grams representing the logic functions performed by validity bit processor 150 of cache controller 106. Fig. 7 shows the generation of 4WDMACH 180 which indicates whether the data word being accessed is valid. The function is comprised of AND gates 230, 231, 232, 233, and 234 whose outputs are fed as inputs into NOR gate 235 which in turn outputs 4WDMACH 180. The inputs to the AND gate 230 are validity bits 117 from tag cache 108 (shown as IWVO (input word valid) through IWV3 in fig. 7) ; CACHE- MISS 154 which is generated by cache read control DRAM buffer enable 153 indicates that the requested data is not available in cache memory 107; ALL 157, which is generated by the system, indicates that cache controller 106 must analyze all 4 data words in the cache line; and QO through Q3 designate which data word from the cache line is being accessed. (QO means DWO is being accessed.) If ALL is HIGH, 4DWMACH is HIGH when the entire cache line is valid, otherwise 4DWMACH is HIGH when the particular data word to be accessed is valid. QO through Q3 are the minterms of PA2 and PA3:

Fig. 8 shows the generation of OWVO (output word valid) which is new validity bit 117a. The function is comprised of AND gates 250 , 251, 252 , 253 , 254, 255, 256 , and 257 whose outputs are fed as inputs to NOR gate 258 which outputs OWVO. As with many of the other logic functions in cache control¬ ler 106 , the number of "gates" could be minimized, however, since speed is crucial, all functions are implemented in a two-stage architecture in the PAL design to minimize the number of levels between inputs and outputs. It is contemplated that the use of higher speed technologies , such as ASIC, which would allow minimization of gates resulting in more levels with no degradation in performance. One of the inputs to the AND gates is OWVO, which is gener¬ ated by this function, thus creating a feedback loop ; ADRAMRDY 128 which is the advanced ready signal from main memory 102 indicating the current DRAM cycle will finish in one clock cycle; TAG_WR_REQ 179 which is generated by write back cache controller 191 indicating that cache control¬ ler 106 needs to update tag cache 108 and status cache 109; ALL 157 which is generated by the system to indicate that cache controller 106 needs to compare all four data words in the cache line; QO which signifies that data word 0 (DWO) from the cache line is being accessed; TAGMACH 115 generated by comparator 110 signifying that PTAG 114 contained in tag cache 108 matches CTAG 113; IWVO 117a from status cache 109 indicating whether the word is currently valid; L_ADS 155 generated by the system is one clock delay of ADS/ 120 and is used to define a write pulse to cache memory 107 during a zero wait state cache write cycle; BOFF_REQ 158 which is generated by write back cache controller 191 indi¬ cates that cache controller 106 needs to request control of the system buses; PA2, the least signifi- cant addressing bit on address bus 104; PA3, the second least significant bit on address bus 104; 1STCYC 171 generated by the system indicates that apparatus 100 is bus master, the bus is currently idle, or CPU 101 is in its first cycle; BOFF 126 generated by write back cache signal generator 190 is asserted to obtain control of system buses. OWVO

117a is HIGH when the data currently accessed from cache memory 107 is from CPU 101 or main memory 102.

OWVl, OWV2, and OWV3 are similar to OWVO 117a and are the validity bits for the remaining three data words contained in each cache line. The only differences between OWVO and OWVl, for instance, involves replacing the OWVO inputs with OWVl; QO with Ql; IWVO with IWV1; and PA2 to PA2/. OWVO, OWVl, OWV2 AND OWV3 are register outputs and are clocked by the CPU clock. The design of the other circuits for OWV2 and OWV3 are thus obvious to one with ordinary skill in the art.

Figs. 9A and 9B of the drawings are logic diagrams representing the logic comprising SRAM write enable controller 151. Fig. 9A shows the generation of two intermediate values TI and T2 which are used in SRAM write enable controller 151 (shown in Fig. 9B) . AND gate 270 has as inputs MEM_ACC 161 which is generated by write back cache controller 191 shown in Fig. 22 using CPU 101 sig¬ nals to inform SRAM write enable controller 151 that the present cycle is a valid cachable cycle; FAST_M 159 is generated by main memory 102 to indicate that the memory is a valid cachable cycle; and W/R 160 which indicates whether the current memory access is a read or write cycle. The inputs to AND gate 271 are MEM_ACC 161; FAST_M 159; WR 160; DRAMRDY 127 which is generated by main memory 102 to inform the current bus master (CPU 101 or cache controller 106) that main memory 102 has completed its cycle; and TRAN_REF 178 which is also generated by main memory 102 to indicate that main memory 102 is undergoing a transparent refresh and therefore cannot be ac- cessed. The outputs of AND gates 270 and 271 are fed into various gates shown on Fig. 9B which shows the generation of WEO 122a which is the write enable signal for one of the four BURSTRAM SRAM chips in cache memory 107. The function is comprised of AND gates 272, 273, 274, 275 and 276 whose outputs are fed as inputs into NOR gate 277 resulting in the output of WEO 122a. The inputs to AND 272 are TI (shown in Fig. 9A) ; L_ADS 155 which is generated by the system as one clock delay of ADS/ 120 and is used to define a write pulse to cache memory 107 during a zero wait state cache write cycle; BEO 163a which is generated by CPU 101 to indicate that a particular byte (in this case byteO) on data bus 105 is enabled; TAGMACH 115 which is generated by compa¬ rator 110 to indicate a cache hit; 4DWMACH 180 which is generated by validity bit processor 150 to indi¬ cate that the accessed data is valid; DIRTY 197 which is generated by dirty bit generator 192 to indicate that the accessed data has not been written to main memory 102; and WB_EN 165 which is generated by write back cache signal generator 190 to indicate to the remaining functions in cache controller 106 that the current cycle is a write back cycle. The inputs to AND 273 are TI; D_ADS 156 which is one clock delay of L_ADS 155 and is used to generate a write pulse during a one wait state cache write cycle; BEO 163a; TAG_WR_REQ 179 which is generated by write back cache controller 191 to indicate tiiat tag cache 108 and/or status cache 109 need to be updated; and BOFF_REQ 164 which is generated by write back cache controller 191 to indicate that cache controller 106 needs to take over the system buses by asserting BOFF/ 126. The inputs to AND 274 are T2 (shown in Fig. 9A) and TAGMACH 115. The inputs to AND 275 are T2; TAGMACH 115; and 4DWMACH 180. The inputs to AND 276 are INVALID 166 which is generated by the system to indicate that the current cycle is a cache master cycle and the cache memory 107 will need to be updated; TAGMACH 115; 4DWMACH 180; and BEO 163a. The only difference between the function shown in Fig. 9B for WEO 122a and the remaining three write enable signals is the substi¬ tution of BE1 163b, BE2 163c, or BE3 163d for BEO 163a depending upon which write enable signal is desired (i.e. for WEI 122b use BE1 163b). Fig. 10 of the drawings is a logic diagram representing functions performed by the DRAM buffer enable portion of cache read controller 153. The figure shows the generation of BUFFEN 125 which, when asserted, causes data buffer 103 between data bus 105 and main memory 102 to be enable. BUFFEN 125 will be HIGH if the current memory access cycle can be handled by apparatus 100. The function is comprised of AND gates 290, 291 and 292 whose out- puts are fed as inputs into NOR gate 293 resulting in output BUFFEN 125. The inputs to AND 290 are NO_DRAM 172 which is generated by write back cache controller 191 to inhibit main memory 102 from activating because the requested data is available in cache memory 107; BHLDA 167 which is generated by the system to indicate that CPU 101 is not the master but rather apparatus 100 is; M/IO 170 which is generated by CPU 101 to indicate a memory access cycle; W/R 160 which is also generated by CPU 101 to indicate whether the current memory access is a read or write; 1STCYC 171 which is generated by the system to indicate that either CPU 101 is in its first cycle, apparatus 100 is mastering the system buses, or the buses are currently idle; MEM_SL0T 174 which is generated by the system and is the AND of MEMR and MEMW which are generated by the system to indicate whether a memory read or memory write needs to be performed on the I/O expansion slot. The inputs to AND 291 are N0_DRAM 172; BHLDA 167; M/IO 170; W/R 160; and 12CYC 169 which is generated by the system to indicate that either CPU 101 is in its first or second cycle, apparatus 100 is master of the system buses, or the system buses are idle. The inputs to AND 292 are N0_DRAM 172; BHLDA 167; MEM_SL0T 174; and REFRESH 176 which is generated by the system to inform cache controller 106 that the system is performing a refresh cycle.

Figs. 11 through 13 of the drawings are logic diagrams representing the logic performed by cache read controller 153. Fig. 11 shows generation of CACRDYEN 177 which is the cache ready enable control signal to enable or disable the generation of a ready signal to CPU 101. The function is comprised of AND gates 294 and 295 whose outputs are fed as inputs into NOR gate 296 resulting in CACRDYEN 177. The inputs to AND 294 are BHLDA 167 which is gener¬ ated by the system to indicate that CPU 101 is not system master; BOFF_BUF_EN 123 which is generated by write back cache signal generator 190 to enable address bus write back buffer 111 to drive the system buses; 12CYC 171 which is generated by the system to indicate that either CPU 101 is in its first or second cycle, apparatus 100 is bus master, or the system buses are idle; CACHEN 168 which is set by the configuration software at initialization to enable or disable apparatus 100; M/IO 170 which is generated by CPU 101 to indicate a memory access cycle; W/R 160 which is generated by CPU 101 to indicate whether the access is a read or write; PA31 184 is generated by the system to indicate whether a math co-processor is present in the computer; and PA25 183 also generated by the system to indicate whether or not the present operation is cachable (HIGH indicates a non-cachable operation) . The inputs to AND 295 are BHLDA 167; BOFF_BUF_EN 123; 1STCYC 171; CACHEN 168; M/IO 170; W/R 160; PA31 194; PA25 183; TAGMACH 115; 4DWMACH 180; and KEN 175 which is generated by main memory 102 and is the internal cachable signal to CPU 101. Fig. 12 shows the generation of CACHEMISS 154 which indicates whether the requested data is avail¬ able in cache memory 107. When CACHEMISS 154 is LOW this indicates that CPU 101's memory access request cannot be handled by apparatus 100, and thus CPU 101 must obtain the data from main memory 102. The function is comprised of AND gates 297, 298, and 299 whose outputs are fed as inputs into NOR gate 300 resulting in output CACHEMISS 154. The inputs to AND gate 297 are CACHEMISS 154 which is feedback from the output of the current function; BHLDA 167 indicating whether CPU 101 is bus master; 1STCYC 171 which is generated by the system to indicate that either CPU 101 is in its first cycle, apparatus 100 is the bus master, or the busses are idle; W/R 160 which indicates whether the current memory access cycle is a read or write cycle; M/IO 170 which indicates that the current cycle is a memory access cycle; KEN 175 which is generated by main memory 102 as its internal cache cachable signal; TAGMACH 115 which is generated by comparator 110 indicating whether CTAG 113 matches PTAG 114; and D_ADS 156 which is generated by the system and is used to generate a write pulse for cache memory 107 during a non-zero wait state cache write cycle. The inputs for AND 298 are CACHEMISS 154; BHLDA 167; 1STCYC 171; W/R 160; M/IO 170; KEN 175; TAGMACH 115; 4WDMACH 180 which is generated by validity bit processor 150 to indicate that the currently ac¬ cessed data word is valid; and D_ADS 156. The inputs to AND 299 are CACHEMISS 154; 1STCYC 171; and -KEN 175.

Fig. 13 shows the generation of CACHE_0E 119 which output enables cache memory 107. When CACHE_OE 119 is LOW the data contained in cache memory 107 which is addressed by ADDR-A 112a will be output onto data bus 105. The function is comprised of AND gates 301, 302, 303 and 304 whose outputs are fed as inputs into NOR gate 305 which results in output CACHE_OE 119. The inputs to AND 301 are 5 BHLDA 167; BOFF_BUF_EN 123 which is generated by write back cache controller 191 to enable address bus write back buffer 111 (shown in Fig. IA) ; 1STCYC 171; CACHEN 168; M/IO 170; W/R 160; PA31 184; PA25 183; TAGMACH 115; 4WDMACH 180; and KEN 175. The

10 inputs to AND 303 are BHLDA 167, BOFF_BUF_EN 123; and CACHEN 168. The inputs to AND 304 are BHLDA 167; DMA_CACHE_RD 173 which is generated by write back cache controller 191 to enable the buffer enable of cache memory 107 if the present cycle is a

15 cache hit read and the associated dirty bit is set; REFRESH 176 which is generated by the system to inform cache controller 106 the system is performing a refresh cycle; and CACHEN 168.

Figs. 14 through 19 of the drawings are logic

20 diagrams representing the logic performed by write back signal generator 190. Fig. 14 shows the gener¬ ation of WB_EN 165 (which is a register output and is clocked by the CPU clock) which indicated to the remaining logic in cache controller 106 that the

²5 cache write back mode is enabled. This function is performed by AND gates 310, 311 and 312 whose out¬ puts are fed as inputs into OR gate 313 to result in WB_EN 165. The inputs to AND gate 310 are WB_SEL 194 which is set by the configuration software at

3⁰ system initialization to allow the user to select between a write through and write back cache; BOFF 126 which is generated by write back cache signal generator 190 to cause CPU 101 to release address bus 104, control bus 133 and data bus 105 so that

35 cache controller 106 can perform a write back cycle;

$5- and ACPURDY 131 which is generated by the system to indicate that CPU 101 is ready to begin the next command. The inputs to AND gate 311 are WB_EN 165 which is generated by the current function thus 5 creating a feedback loop; BOFF 126; and ACPURDY 131. The inputs to AND gate 312 are WB_EN 165 and BOFF 126.

Fig. 15 shows the generation of BOFF_BUF_EN 123 (again a register output clocked by the CPU clock) ° which enables address bus write back buffer 111 to drive address bus 104, control bus 133, and data bus 105. The function is comprised of AND gates 330 and 331 whose outputs are fed as inputs into OR gate 332 resulting in BOFF_BUF_EN 123. The inputs to AND 5 gate 330 are BOFF_BUF_EN 123 which is generated by inverting the output of the current function thus creating a feedback path; WB_SEL 194 which is set by the configuration software at system initialization to allow the user to select between a write through 0 and write back cache; WB_EN 165 which is generated by write back cache signal generator 190 and indi¬ cated to all logic in cache controller 106 that the cache write back mode is enabled; BOFF 126 which is generated by write back cache signal generator 190 5 to cause CPU 101 to release the system buses; and READY_1 200 which is generated by write back cache signal generator 190 to inform the system ready logic that the present cycle is a one wait state cycle (the one wait state cycle occurs only if cache controller 106 needs to update tag cache 108 and status cache 109) . The inputs of AND gate 331 are BOFF_BUF_EN 123; WB_SEL 194; WB_EN 165; and TAGWR 116 which is generated by write back cache signal controller 190 to update the contents of tag cache 5 108 and status cache 109. BOFF BUF EN 123 is LOW when the current cycle is a write back cycle.

Fig. 16 shows the generation of BOFF 126 which is a register output clocked by the CPU clock. When asserted, BOFF causes CPU 101 to release address bus 104, control bus 133 and data bus 105. The function is performed by AND gates 333 and 334 whose outputs are fed as inputs into OR gate 335 which in turn outputs BOFF 126. The inputs to AND gate 333 are BOFF 126 which is the inverse of the output of this function thus creating a feedback loop; WB_SEL 194 which indicates whether apparatus 100 is a write through or write back cache; WB_EN 165 which indi¬ cates to the logic in cache controller 106 that the current cycle is a write back cycle; L_ADS 155 which is generated by the system and is one clock delay of ADS 120 which is used to define a write pulse to cache memory 107 during a zero wait state cache write cycle; and B0FF_REQ 164 which is gener¬ ated by write back cache controller 191 to indicate that BOFF 126 needs to be asserted. The inputs to AND gate 334 are BOFF 126 which is generated by this function thus creating a feedback loop; WB_SEL 194; WB_EN 165; and TAGWR 116 which is generated by write back cache signal generator 190 to indicate that tag cache 108 and status cache 109 are to be updated. When BOFF 126 is LOW, CPU 101 backs off all of the system buses allowing apparatus 100 to perform a write back operation to main memory 102.

Fig. 17 shows the generation of READY_1 200 (which again is a register output clocked by the CPU clock) which indicates to the system ready logic that the present cycle of apparatus 100 is a one wait state cycle. This occurs only where cache controller 106 needs to update tag cache 108 and/or status cache 109. The function is comprised of AND gates 326, 327, and 328 whose outputs are fed as inputs into NOR gate 329 resulting in the output of READY_1 200. The inputs to AND gate 326 are READY_l 200 which creates an inverse feedback loop; L_ADS 155 which defines a write pulse to cache memory 107 during a zero wait state cache write cycle; B0FF_REQ 164 which is generated by write back cache control¬ ler 191 to indicate that apparatus 100 needs to master the system buses to perform a write back operation; and SLOW. The inputs to AND gate 327 are READY_1 200; BOFF 126; BOFF_BUF_EN 126; and SLOW. The inputs to AND gate 328 are READY_1 200; BOFF 126; WB_EN 165 which indicates that the current cache is in write back mode; L_ADS 155 which de- fines a write pulse to cache memory 107 during a zero wait state cache write cycle; TAG_WR_REQ 179 which indicates that new status data needs to be written to tag cache 108 and/or status cache 109 B0FF_REQ 164 which is generated by write back cache controller 191 to indicate that apparatus 100 needs to master the system buses so that it can perform a write back operation; and ACPURDY 131 which is generated by the system to indicate, in a normal cycle, that CPU 101 is ready for the next command, however, during write back cycles, this signal is held HIGH.

Fig. 18 shows the generation of ALT_ADS 337 which is a register output clocked by the CPU clock is used to slow down a write back cycle by apparatus 100. The function is comprised of AND gates 323 and 324 whose outputs are connected as inputs to NOR gate 325 whose output is ALT_ADS 337. The inputs to AND 323 are ALT_ADS 337 which is generated by this function thus creating a feedback loop; BOFF_BUF_EN 126 which is generated by write back cache signal generator 190 to enable address bus write back buffer 111 to drive the system buses during write back operations only; BOFF 126 which forces CPU 101 to release the system buses so that cache controller 106 could perform a write back cycle; and READY_1 200 which is generated by write back cache signal generator 190 to indicate that the current cycle is a one wait state cycle, The inputs to AND 324 are ALT_ADS 337 which is generated by this function thus creating an inverse feedback loop; BOFF_BUF_EN 126; BOFF 126; ACPURDY 131 which is generated by the system to indicate that CPU 101 is ready for the next command, however, during write back cycles it is held HIGH; and L_DIRTY 203 which is generated by dirty bit generator 192 to indicate that the write back cycle is about to finish.

Fig. 19 shows the generation of BOFF_ADS 201 which is fed into address bus write back buffer 111 and out onto control bus 133 as ADS 120 and is used to control the timing of cache memory 107 during write back operations. This signal is a register output clocked by the CPU clock. The function is comprised of AND gates 319, 320, and 321 whose outputs are fed as inputs into NOR gate 322 whose output is B0FF_ADS 201. The inputs of AND 319 are B0FF_ADS 201 thus creating an inverted feedback loop; SLOW; BOFF_BUF_EN 126 which enables address bus write back 111 to drive address bus 104, control bus 133, and data bus 105; BOFF 126 which forces CPU 101 to release the system buses so that cache con¬ troller 106 can perform a write back cycle; and READY_1 200 which indicates that the current cycle is a one wait state cycle. The inputs to AND gate 320 are B0FF_ADS 201; SLOW; BOFF_BUF_EN 126; BOFF 1261; ACPURDY 131 which indicates that, in normal operation, CPU 101 is ready for the next command, however, during write back cycles this signal is held HIGH; and L_DIRTY 203 which is generated by dirty bit generator 192 to indicate that the write back cycle is going to finish. The inputs to AND gate 321 are BOFF_ADS 201; SLOW; and ALT_ADS 337 which is generated by write back cache signal gener¬ ator 190 and is used to slow down write back cycles. Fig. 20 of the drawings is a logic diagram representing the logic comprising write back cache signal controller 190. Fig. 20 shows the generation of TAGWR 116 which is a register output clocked by the CPU clock which controls the updating of tag cache 108 and status cache 109 through direct con- nection to the write enable pin of SRAMs 140 and 141 and connection to the output enable pins of SRAMs 140 and 141 through inverter 143 (shown in Figs. 2A and 2B) . The function is comprised of AND gates 314, 315, 316, and 317 whose outputs are fed as inputs into NOR gate 318, whose output is TAGWR 116. The inputs to AND 314 are TAGWR 116 which is gener¬ ated by the current function therefore creating a feedback loop; P_TERM1 202 which is generated by write back cache controller 191 (shown in Fig. 25) to minimize the number of pins required in the fabrication of the PAL for write back cache signal generator 190; BLAST 193 which is generated by CPU 101 to indicate the last burst cycle from CPU 101; ADRAMRDY 128 which is generated by main memory 102 one CPU clock cycle earlier than DRAMRDY 127 which is used by apparatus 100 to update the information in tag cache 108 and status cache 109; and TAGMACH 115 which indicates PTAG 114 is equivalent to CTAG 113 ("cache hit") . The inputs to AND 315 are TAGWR 116; P_TERM1 202; BLAST 193; ADRAMRDY 128; TAGMACH 115; and 4DWMACH 180 which is generated by validity bit processor 150 to indicate that the data word currently being accessed in cache memory 107 is valid. The inputs to AND gate 316 are TAGWR 116; WB_EN 165 which is generated by write back cache signal generator 190 to indicate that the current cache is in write back mode; TAG_WR_REQ 179 is generated by write back cache controller 191 to indicate to write back cache signal generator 190 that the contents of tag cache 108 and/or status cache 109 need to be updated; L_ADS 155 which is generated by the system is used to define a write pulse to cache memory 107 during a zero wait state cache write cycle; ACPURDY 131 which is generated by the system, in normal cycles to indicate that CPU is ready for the next command, however, during write back cycles this signal is held HIGH; BOFF_REQ 164 which is generated by write back cache controller 191 to indicate to write back cache signal generator 190 to assert BOFF 126 to cause CPU 101 to release the system buses so that cache controller 106 can perform a write back cycle. The inputs to AND gate 317 are TAGWR 116; BOFF_BUF_EN 123 which is generat¬ ed by write back cache signal generator 190 to enable address bus write back buffer 111 to drive address bus 104, control bus 133, and data bus 105; BOFF 126 which is generated by write back cache signal generator 190 and asserted to cause CPU 101 to release the system buses; ACPURDY 131; and L_DIRTY 203 which is generated by dirty bit proces¬ sor 192 to indicate that the write back cycle is about to finish. When TAGWR 116 is LOW this will cause tag cache 108 and status cache 109 to write the data currently available at its inputs (i.e. CTAG 113, validity bits 117, and dirty bits 118). Figs. 21 through 28 of the drawings are logic diagrams representing the logic performed by write back cache controller 191. Fig. 21 shows the gener¬ ation of CACHE_MEM which is the output of AND gate 350 whose inputs are FAST_M 159 which is generated by main memory 102 to indicate to the memory that it is a valid cachable cycle; BIOS 196 which is gener¬ ated by the system to indicate that this a BIOS memory decode thus not cacheable; M/IO 170, generat- ed by CPU 101, indicates that the current cycle is a memory access cycle; and PA25 183 which is generated by the system on address bus 104, as shown in Fig. IC, indicating whether the current cycle is a cacha¬ ble cycle (HIGH indicates a non-cachable cycle) . Fig. 22 shows the generation of MEM_ACC 161 which is the output of NAND gate 351 whose inputs are BHLDA 167 which is generated by the system to inform the system that apparatus 100 is the current master of the system; BIOS 196; M/IO 170; and PA25 183.

Fig. 23 shows the generation of DMA__CACH_RD 173 which is the output of NAND gate 352 whose inputs are BHLDA 167; MEMR 198 which is generated by the system 1/0 SLOT indicating a memory read from the 1/0 expansion slot; FAST_M 159; BIOS 196; TAGMACH 115 which is generated by comparator 110 to indicate whether there is a cache hit; 4WDMACH 180 which is generated by validity bit processor 150 to indicate that the currently accessed data word is valid; and DIRTY 197 which is generated by dirty bit processor 192 to indicate that the currently accessed data word needs to be written back to main memory 102.

Fig. 24 shows the generation of READY_0 199 which is the output of NAND gate 353 and indicates that the current cycle of apparatus 100 is a zero wait state cycle. The inputs to AND gate 353 are BOFF_BUF_EN 123 which is generated by write back cache signal generator 190 to enable address bus write back buffer 111 to drive the system buses during write back operations; BHLDA 167 which is generated by the system to indicate that the system is currently mastered by apparatus 100; WB_EN 165 which is generated by write back cache signal gener¬ ator 190 and indicates that the current cache is in a write back mode; BIOS 196 which is generated by the system to indicate that the current memory cycle is a BIOS memory cycle and therefore not cachable; M/IO 170 which is generated by CPU 101 to indicate that the current cycle is a memory access cycle; PA25 183 which is available on address bus 104 indicates whether the current cycle is a valid cachable cycle (when LOW) ; and W/R 160 which is generated by CPU 101 to indicate whether the memory cycle is a read or write cycle. Fig. 25 shows the generation of P_TERM1 202 which is the output of NAND gate 354 and is used to minimize the number of pins required in the PAL used to implement write back cache signal generator 190. The inputs to AND gates 354 are BHLDA 167; W/R 160; and CACHE_MEM which is generated internally in write back cache controller 191 (as shown in Fig. 21) .

Fig. 26 shows the generation of BOFF_REQ 164 which indicates to write back cache signal generator 190 that the next cycle is a write back cycle and therefore BOFF 126 must be asserted. The function is comprised of AND gate 355, 356 and 357 whose outputs are fed as inputs into NOR gate 358 result¬ ing in BOFF_REQ 164. The inputs to AND 355 are BOFF_BUF_EN 123 which is generated by write back cache signal generator 190 and is used to enable address bus write back buffer 111 at drive the system buses during write back operations; BHLDA 167 which is generated by the system indicates that the system is currently mastered by apparatus 100; WB_EN 165 is generated by write back cache signal genera¬ tor 190 to indicate that the current cache in write back mode; CACHE_MEM is generated by write back cache controller 191 (as shown in Fig. 21) and signifies that the current memory access cycle is cachable; W/R 160, generated by CPU 101, indicates whether the current memory access cycle is a read or write cycle; TAGMACH 115, generated by comparator 110, indicates whether the current cycle is a cache hit; L_DIRTY 203 which is generated by dirty bit processor 192 indicates that the write back cycle is finishing; and DWORD 195 which is generated by the system and indicates that cache controller 106 needs to compare all four bytes of the data word. The inputs to AND 356 are BOFF_BUF_EN 123; BHLDA 167; CACHE_MEM; W/R 160; TAGMACH 115; and DIRTY 197 which is generated by dirty bit processor 192 to indicate that the currently accessed data word in cache memory 107 needs to be written back to main memory 102. The inputs to AND 357 are BOFF_BUF_EN 123; BHLDA 167; CACHE_MEM; W/R 167; TAGMACH 115; 4DWMACH 180 which is generated by validity bit processor 150 to indicate that the currently accessed data word in cache memory 107 is valid; and DIRTY 197.

Fig. 27 shows the generation of TAG_WR_REQ 179 which is used by write back cache controller 191 to indicate to write back cache signal generator 190 that tag cache 108 and status cache 109 need to be updated through the assertion of TAGWR 116. The function is comprised of AND gates 359, 360, 361, 362, and 363 whose outputs are fed as inputs into NOR gate 364 which outputs TAG_WR REQ 179 . The inputs to AND 359 are BOFF_BUF_EN 123 which is generated by write back cache signal generator 190 to enable address bus write back buffer 111 to drive the system buses during write back cycles ; BHLDA 167 which is generated by the system to indicate that apparatus 100 is currently bus master ; WB_EN 165 which is generated by write back cache signal gener¬ ator 190 to indicate that the current cache is in write back mode; CACHE_MEM which is generated inter¬ nally indicates whether the current cycle is a cachable cycle ; W/R 160 which is generated by CPU 101 indicating whether the current memory access cycle is a read or write cycle ; and DWORD 195 is generated by the system to indicate that cache controller 106 needs to compare al l four bytes contained in the cache line indicated by the address on ADDR-A 112a and located in cache memory 107. The inputs to AND gate 360 are BOFF_BUF_EN 123 ; BHLDA 167 ; WB_EN 165 ; CACHE_MEM ; W/R 160 ; DWORD 195 ; TAGMACH 115 which is generated by comparator 110 indicating whether or not there is a cache hit; and 4DWMACH_^ 180 which is generated by validity bit processor 150 to indicate whether the currently accessed data word is valid. The inputs to AND gate 3 6 1 BOFF_BUF_EN 12 3 ; BHLDA 167 ; WB_EN 165 ; CACHE_MEM; W/R 160 ; TAGMACH 115 ; and 4WDMACH 180 . The inputs to AND 362 are BOFF_BUF_EN 123 ; BHLDA 167 ; CACHE_MEM; W/R 160 ; TAGMACH 115 ; and DIRTY 197 which is generated by dirty bit processor 192 and

-indicates that the currently accessed data word in cache memory 107 needs to be written back to main memory 102 and is therefore dirty. The inputs to AND

363 are BOFF_BUF_EN 123 ; BHLDA 167 ; CACHE_MEM; W/R 160 ; TAGMACH 115 ; 4DWMACH 180 ; and DIRTY 197 . Fig. 28 shows the generation of NO_DRAM 172 which is used to inhibit main memory 102 from acti¬ vating because the data currently requested by CPU 101 is available in cache memory 107. The function is performed by AND gates 365, 366, 367, 368, 369, and 370 whose outputs are fed as inputs into NOR gate 371 whose output is NO_DRAM 172. The inputs to AND 365 are BOFF_BUF_EN 123 which is generated by write back cache signal generator 190 to enable address bus write back buffer 111 to drive the system buses during a write back cycle; BHLDA 167 indicates that apparatus 100 is cache master; WB_EN 165 which is generated by write back cache signal generator 190 indicates that the current cache is in write back mode; CACHE_MEM is generated within write back cache controller 191 (as shown in Fig. 21) and indicates that the current cycle is a cachable cycle; W/R 160 is generated by CPU 101 indicating that the current memory access cycle is a read or write cycle; and DWORD 195 indicates that cache controller 106 needs to compare all four bytes contained in the cache line contained in cache memory 107 as addressed by ADDR-A 112a. The inputs to AND 366 are BOFF_BUF_EN 123; BHLDA 167; WB_EN 165; CACHE_MEM; W/R 160; DWORD 195; TAGMACH 115 which is generated by comparator 110 and indicates a cache hit; and 4DWMACH 180 which is generated by validity bit controller 150 and indicates that the currently accessed data word in cache memory 107 is valid. The inputs to AND 367 are BOFF_BUF_EN 123; BHLDA 167; CACHE_MEM; W/R 160; TAGMACH 115; and DIRTY 197 which is generated by dirty bit processor 192 and indicates that the currently accessed data word in cache memory 107 must be written back to main memory 102. The inputs to AND 368 are BOFF_BUF_EN 123; BHLDA 167; CACHE_MEM; W/R 160; TAGMACH 115; 4DWMACH 180; and DIRTY 197. The inputs to AND 369 are BOFF_BUF_EN 123; BHLDA 167; CACHE_MEM; W/R 160; TAGMACH 115; 4DWMACH 180; and CACHEN 168 which is generated by cache controller 106 in response to the configuration software and is used to enable or disable apparatus 100. The inputs to AND 370 are BHLDA 167; MEMR 198 which are gener¬ ated by the system to indicate that the current memory access cycle is a memory read cycle; FAST_M 159 which is generated by main memory 102 to indi¬ cate to the memory that this is a valid cachable cycle; BIOS/ 196 which is generated by the system to inhibit cache controller 106 from updating cache memory 107 when the present cycle is a BIOS memory cycle; TAGMACH 115; 4DWMACH 180; and DIRTY 197.

Figs. 29 through 33 of the drawings are logic diagrams representing the logic performed by dirty bit processor 192. Fig. 29 shows the generation of PA2 104a which is the least significant address bit, shown in Fig. IC, on address bus 104 and is active only during write back cycles. The function is comprised of AND gates 380 and 381 whose outputs are fed as inputs to OR gate 382 whose output in turn PA2 104a. The inputs to AND 380 are LDIR1 and LDIRO which are generated by dirty bit processor 192. The inputs to AND 381 are LDIR3; LDIR2; LDIR1; and LDIRO which are all generated within dirty bit processor 192. Fig. 30 shows the generation of PA3 104b which is the next to least significant bit on address bus 104 shown in Fig. IC. This signal is active only during cache write back cycles. The function is comprised of AND gates 383 and 384 whose outputs are fed as inputs to OR gate 385 which outputs PA3 104b. The inputs to AND 383 are LDIR2; LDIR1; and LDIRO which are all generated internally within dirty bit processor 192. The inputs to AND 384 are LDIR3; LDIR2; LDIR1; and LDIRO which are all again inter- nally generated by dirty bit processor 192.

Fig. 31 shows the generation of DIRTY 197 which indicates that the currently accessed data from cache memory 107 needs to be written back to main memory 102 because it probably differs from the data currently held in main memory 102. The function is comprised of AND gates 386, 387, 388, 389, and 390 whose outputs are all fed as inputs, to NOR gate 391 along with input WB_EN 165 resulting in output DIRTY 197. The inputs to AND 386 are ALL 157, generated by the system, indicates whether cache controller 106 needs to compare all four data words in the cache line; DIRO 118a which is obtained from status cache 109; DIR1 118b which is also obtained from status cache 109; DIR2 118c also from status cache 109; and DIR3 118d which is also from status cache 109. The inputs to AND 387 are ALL 157; PA3 204; PA2 205; and DIRO. The inputs to AND 388 are ALL 157; PA3 204; PA2 205; and DIR1. The inputs to AND 389 are ALL 157; PA3 204; PA2 205; and DIR2. The inputs to AND 390 are ALL 157; PA3 204; PA2 205; and DIR3.

Fig. 32 shows the generation of LDIRO which is a register output and is clocked by the CPU clock. The function is comprised of 392, 393, 394, 395, 396, 397, 398, and 399 whose outputs are all fed as inputs to NOR gate 400 which in turn has an output of LDIRO. The inputs to AND 392 are LDIRO which is the feedback of this function; PA2 205; PA3 204; L_ADS 155, generated by the system, used to define a write pulse to cache memory 107 during a zero wait state cache write cycle; TAG_WR_REQ 179 which is generated by write back cache controller 191 to signal to write back cache signal generator 190 that tag cache 108 and/or status cache 109 need to be updated and therefore TAGWR 116 must be asserted; B0FF_REQ 164 is generated by write back cache con¬ troller 191 and is used to tell write back cache signal generator 190 to generate BOFF 126 such that CPU 101 releases the system buses so that cache controller 106 can perform a write back cycle; and ACPURDY 131 which is generated by the system, in a normal cycle, signals that CPU 101 is ready for the next command, however, during cache write back cycles, this signal is held HIGH. The inputs to AND 393 are LDIRO 118a which is the inverted signal available from status cache 109 indicating whether the data word stored in cache memory 107 has been written back to main memory 102; L ADS 155; BOFF_REQ 164; ACPURDY 131. The inputs to AND 394 are LDIRO; DIRO 118a; PA2 205; L_ADS 155; TAG_WR_REQ 179; BOFF_REQ 164; and ACPURDY 131. The inputs to AND 395 are LDIRO; DIRO 118a; PA3; L_ADS 155; TAG_WR_REQ 179; B0FF_REQ 164; and ACPURDY 131. The inputs to AND 396 are LDIRO; BOFF_BUF_EN 123 which enables address bus write back buffer 111 to drive the system buses during write back cycles; and ACPURDY 131. The inputs to AND 397 are LDIRO; BOFF_BUF_EN 123; ACPURDY 131; and PA2 205. The inputs to AND 398 are LDIRO; BOFF_BUF_EN 123; ACPURDY 131; and PA3 204. The inputs to AND 399 are LDIRO; BOFF_BUF_EN 123; and 1STCYC 171 which is generated by the system to indicate that CPU 101 is in its first cycle, the apparatus 100 is bus matter, or the system bus is idle. Fig. 33 shows the generation of L DIRTY 203 which informs cache controller 106 that the write back cycle is going to finish. The function is comprised of AND gates 401, 402, 403, 404 and 405 whose outputs are fed as inputs to NOR gate 406 which in turn outputs L_DIRTY 203. The inputs of AND gate 401 are BOFF_BUF_EN 123; LDIR3; LDIR2; LDIR1; and LDIRO. The inputs to AND gate 402 are BOFF_BUF_EN 123; LDIR3; LDIR2; LDIR1; and LDIRO. The inputs to AND gate 403 are BOFF_BUF_EN 123; LDIR3; LDIR2; LDIR1; and LDIRO. The inputs to AND gate 404 are BOFF_BUF_EN 123; LDIR3; LDIR2; LDIR1. The inputs to AND 405 are BOFF_BUF_EN 123; DIRO 118a; DIR1 118b; DIR2 118c; and DIR3 118d.

Those portions of the present invention which are described herein as comprising programmable array logic devices were generated by the following PAL equations which those skilled in the art may readily understand and implement. The PAL compiler used to generate these equations is the AMD PALASM go Version 1.1 compiler.

CHIP:VALIDITY BIT CONTROLLER 150

CLK PA2 PA 3 /IWVO /IWV1 /IWV2 /IWV3 /TAGMACH /CACHEMISS /BOFF /L_ADS GND

/TAGWR /ALL /TAG_WR_REQ /1STCYC /OWVO /OWVl /OWV2 /0WV3 4DWMACH /ADRAMRDY /B0FF_REQ VCC

; IWV[0..3] (INPUT WORD VALID) ARE THE INPUT BITS WHICH INDICATE THE 32 BIT

; WORD INDICATED BY PA2 AND PA3 IS VALID, OWV[0..3] (OUTPUT WORD VALID) ARE ; THE OUTPUT BITS WHICH ARE WRITTEN TO THE WORD VALID CACHE THEY RETAIN

; THE THREE OTHER WORD STATUS BITS WHICH MAKE UP THE QUAD WORD AND UPDATE

; THE CURRENTLY ADDRESSED WORD INDICATED BY PA2 AND PA3.

STRING QO '/PA2 * /PA3'

STRING Ql 'PA2 * /PA3'

STRING Q2 '/PA2 * PA3'

STRING Q3 'PA 2 * PA3'

EQUATIONS

4DWMACH = ALL * IWVO * IWV1 * IWV2 * IWV3 * /CACHE¬ MISS

+ /ALL * QO * IWVO

+ /ALL * Ql * IWV1

+ /ALL * Q2 * IWV2

+ /ALL * Q3 * IWV3 OWVO := /OWVO * ADRAMRDY * /TAG_WR_REQ * ALL * QO

+ / OWVO * ADRAMRDY * /TAG_WR_REQ * ALL * TAGMACH * IWVO

+ /OWVO * L_ADS * TAG_WR_REQ * /BOFF_REQ * QO

+ /OWVO * L_ADS * TAG_WR_REQ * BOFF_REQ *

IWVO

+ /OWVO * L_ADS * TAG_WR_REQ * /BOFF_REQ * TAGMACH * PA2 * IWVO

+ /OWVO * L_ADS * TAG_WR_REQ * /BOFF_REQ * TAGMACH * PA3 * IWVO

+ OWVO * /1STCYC

+ OWVO * BOFF

OWVl := /OWVl * ADRAMRDY * /TAG_WR_REQ * ALL * Ql

+ /OWVl * ADRAMRDY * /TAG_WR_REQ * ALL * TAGMACH * IWV1

+ /OWVl * L_ADS * TAG_WR_REQ * /BOFF_REQ * Ql

+ /OWVl * L_ADS * TAG_WR_REQ * BOFF_REQ * IWV1

+ /OWVl * L_ADS * TAG_WR_REQ * /BOFF_REQ * TAGMACH * /PA2 * IWV1

+ /OWVl * L_ADS * TAG_WR_REQ * /BOFF_REQ * TAGMACH * PA3 * IWV1 + OWVl * /1STCYC

+ OWVl * BOFF

OWV2: = /OWV2 * ADRAMRDY * /TAG_WR_REQ * ALL * Q2

+ /OWV2 * ADRAMRDY * /TAG_WR_REQ * ALL * TAGMACH * IWV2

+ /OWV2 * L_ADS * TAG_WR_REQ * /BOFF_REQ * Q2

+ /OWV2 * L_ADS * TAG_WR_REQ * BOFF_REQ * IWV2

+ /OWV2 * L_ADS * TAG_WR_REQ * /BOFF_REQ * TAGMACH * PA2 * IWV2

+ /OWV2 * L_ADS * TAG_WR_REQ * /BOFF_REQ * TAGMACH * /PA3 * IWV2

+ OWV2 */lSTCYC

+ OWV2 * BOFF

OWV3 : = /OWV3 * ADRAMRDY * /TAG_WR_REQ * ALL * Q3

+ / OWV3 * ADRAMRDY * /TAG_WR_REQ * ALL * TAGMACH * IWV3

+ /OWV3 * L ADS * TAG WR REQ * /BOFF REQ * Q3 + /OWV3 * L_ADS * TAG_WR_REQ * BOFF_REQ * IWV3

+ /OWV3 * L_ADS * TAG_WR_REQ * /BOFF_REQ * TAGMACH * /PA2 * IWV3

+ /OWV3 * L_ADS * TAG_WR_REQ * /BOFF_REQ *

TAGMACH * /PA3 * IWV3

+ OWV3 * /1STCYC

+ OWV3 * BOFF

CHIP:SRAM WRITE ENABLE CONTROLLER 151

/D_ADS /DRAMRDY /4DWMACH WR /TAGMACH /MEM_ACC DIRTY /BEO /BE1 /BE2 /BE3 GND

/BOFF_REQ /WB_EN /CWO /REF /FAST /TAG_WR_REQ /L_ADS /CW1 /CW2 /CW 3 /INVALID VCC

STRING TI 'MEM_ACC * FAST * WR'

STRING T2 'MEM_ACC * FAST * /WR * DRAMRDY * /REF¹

EQUATIONS

CWO = TI * L_ADS * BEO * TAGMACH *4DWMACH *^' DIRTY * WB_EN

+ TI * D_ADS * BEO * TAG_WR_REQ * /BOFF_REQ

+ T2 * /TAGMACH

+ T2 * TAGMACH * /4DWMACH

+ INVALID * TAGMACH * 4DWMACH * BEO

CW1 = TI * L_ADS * BE1 * TAGMACH * 4DWMACH * DIRTY * WB EN + TI * D_ADS * BE1 * TAG_WR_REQ * /BOFF_REQ

+ T2 * /TAGMACH

+ T2 * TAGMACH * /4DWMACH

+ INVALID * TAGMACH * 4DWMACH * BE1

CW2 = TI * L_ADS * BE2 * TAGMACH * 4DWMACH * DIRTY * WB_EN

+ TI * D_ADS * BE2 * TAG_WR_REQ * /BOFF_REQ

+ T2 * /TAGMACH

+ T2 * TAGMACH * /4DWMACH

+ INVALID * TAGMACH * 4DWMACH * BE2

CW3 = TI * L_ADS * BE3 * TAGMACH * 4DWMACH * DIRTY * WB_EN

+ TI * D_ADS * BE3 * TAG_WR_REQ * /BOFF_REQ

+ T2 * /TAGMACH

+ T2 * TAGMACH * /4DWMACH

+ INVALID * TAGMACH * 4DWMACH * BE3 CHIP:CACHE READ CONTROLLER 153

/D_ADS /BHLDA CACHEN /12CYC WR MIO /ISTCYC /NO_DRAM

/TAGMACH NC /BOFF_BUF_EN

GND

/DMA_CACHE_RD /DMA /CACRDYEN PA25 /REFRESH /4DWMACH PA31 /CACHE_OE /CACHMISS /BUFFEN /KEN VCC

EQUATIONS

CACHMISS = /CACHMISS * /BHLDA * /ISTCYC * /WR * MIO * KEN * /TAGMACH * D_ADS

+ /CACHMISS * /BHLDA * /ISTCYC * /WR * MIO * KEN * TAGMACH

/4DWMACH * D_ADS

+ CACHMISS * /ISTCYC * KEN

BUFFEN = /NO_DRAM * /BHLDA * MIO * WR * /ISTCYC * /DMA

+ /NO_DRAM * /BHLDA * MIO * /WR * /12CYC

+ /NO_DRAM * BHLDA * DMA * /REFRESH CACHE_OE = /BHLDA * /BOFF_BUF_EN * 12CYC * CACHEN * MIO * /WR * /PA31 *

/PA25

+ /BHLDA * /BOFF_BUF_EN * /ISTCYC * CACHEN * MIO * /WR * /PA31 *

/PA25 * TAGMACH * 4DWMACH * KEN

+ /BHLDA * BOFF_BUF_EN * CACHEN

+ BHLDA * DMA_CACHE_RD * /REFRESH * CACHEN

CACRDYEN = /BHLDA * /BOFF_BUF_EN * 12CYC * CACHEN * MIO * /WR * /PA31 *

/PA25

+ /BHLDA * /BOFF_BUF_EN * /ISTCYC * CACHEN * MIO * /WR * /PA31 *

/PA25 * TAGMACH * 4DWMACH * KEN

CHIP:WRITE BACK CACHE SIGNAL GENERATOR 190

CPUCLK /CPURDY /L_ADS /SLOW /ADRAMRDY /BLAST WB_SEL /4DWMACH /TAGMACH /P_TERM1 /LAST_DIRTY GND

OE /TAG_WR_REQ /WB_EN /ALT_ADS NC /TAGWR /BOFF_ADS /READY_1 /BOFF_BUF_EN /BOFF /BOFF REQ VCC

EQUATIONS

WB_EN : = WB_SEL * /BOFF * CPURDY

+ WB_EN * /BOFF * /CPURDY

+ WB EN * BOFF

TAGWR : = / TAGWR * P_TERM1 * BLAST * ADRAMRDY * /TAGMACH

+ / TAGWR * P_TERM1 * BLAST * ADRAMRDY * TAGMACH * /4DWMACH

+ /TAGWR * WB _EN * TAG_WR_REQ * L_ADS * /CPURDY * /BOFF_REQ

+ /TAGWR * BOFF_BUF_EN * BOFF * CPURDY * LAST DIRTY BOFF_ADS := /BOFF_ADS * /SLOW * /BOFF_BUF_EN * BOFF

* READY_1

+ /BOFF_ADS * /SLOW * BOFF_BUF_EN * BOFF

* CPURDY * /LAST_DIRTY

+ /BOFF_ADS * SLOW * ALT_ADS

ALT_ADS : = /ALT_ADS * /BOFF_BUF_EN * BOFF * READY_1

+ /ALT_ADS * BOFF_BUF_EN * BOFF * CPURDY * /LAST_DIRTY

READY_1 : = /READY_1 * L_ADS * BOFF_REQ */SLOW

+ /READY_1 * BOFF */BOFF_BUF_EN * SLOW

+ /READ _1 * / BOFF * WB_EN * L_ADS * TAG WR REQ * /BOFF REQ * /CPURDY

BOFF_BUF_EN := /BOFF_BUF_EN * WB_SEL * WB_EN * BOFF * READY_1

+ BOFF_BUF_EN * WB_SEL * WB_EN * /TAGWR BOFF := /BOFF * WB_SEL * WB_EN * L_ADS * BOFF_REQ

+ BOFF * WB_SEL * WB_EN * /TAGWR

CHIP: RITE BACK CACHE CONTROLLER 191

CACHEN PA25 /DWORD /BIOS MIO WR /BHLDA /FAST /TAGM¬ ACH /4DWMACH DIRTY GND

/WB_EN /BOFF_BUF_EN /DMA_CACHE_RD /MEMR /MEM_ACC

/READY_0 /NO_DRAM /P_TERM1

/BOFF REQ /TAG WR REQ LAST DIRTY VCC

STRING CACHE_MEM 'FAST * /BIOS * MIO * /PA25'

EQUATIONS

MEM_ACC = /BHLDA * /BIOS * MIO * /PA25

DMA_CACHE_RD = BHLDA * MEMR * FAST * /BIOS * TAGMACH * 4DWMACH * DIRTY

READY_0 = /BOFF_BUF_EN * /BHLDA * WB_EN * /BIOS * MIO * /PA25 * WR

P TERM1 = /BHLDA * /WR * CACHE MEM

TAG__WR_REQ = / BOFF_BUF_EN * / BHLDA * WB_EN * CACHE_MEM * WR * DWORD

+ / BOFF BUF EN * / BHLDA * WB EN * CACHE_MEM * WR */DWORD

* TAGMACH * 4DWMACH

+ / BOFF_BUF_EN * / BHLDA * / WB_EN * CACHE_MEM * WR * TAGMACH * 4DWMACH

+ /BOFF_BUF_EN * /BHLDA * CACHE_MEM * /WR

* /TAGMACH * DIRTY

+ /BOFF_BUF_EN * /BHLDA * CACHE_MEM * /WR

* TAGMACH * /4DWMACH * DIRTY

NO_DRAM = /BOFF_BUF_EN * /BHLDA * WB_EN * CACHE_MEM * WR * DWORD

+ /BOFF_BUF_EN * /BHLDA * WB_EN * CACHE_MEM * WR */DWORD *

TAGMACH * 4DWMACH

+ /BOFF_BUF_EN * /BHLDA * CACHE_MEM * /WR * /TAGMACH * DIRTY

+ /BOFF_BUF_EN * /BHLDA * CACHE_MEM * /WR * TAGMACH * /4DWMACH * DIRTY

+ /BOFF_BUF_EN * /BHLDA * CACHE_MEM * /WR * TAGMACH * 4DWMACH * CACHEN

+ BHLDA * MEMR * FAST * /BIOS * TAGMACH *

4DWMACH * DIRTY B0FF_REQ = /BOFF_BUF_EN * /BHLDA * WB_EN * CACHE_MEM * WR * /TAGMACH *

LAST_DIRTY * DWORD

+ /BOFF_BUF_EN * /BHLDA * CACHE_MEM * /WR * /TAGMACH * DIRTY

+ /BOFF_BUF_EN * /BHLDA * CACHE_MEM * /WR * TAGMACH * /4DWMACH * DIRTY

CHIP:DIRTY BIT PROCESSOR 192

CPUCLK /BOFF_BUF_EN /CPURDY /L_ADS /TAG_WR_REQ DIRO DIR1 DIR2 DIR3 /BOFF_REQ /WB_EN GND

OE /ALL PA3 PA2 /LDIR3 /LDIR2 /LDIRl /LDIRO /DIRTY /LAST_DIRTY /ISTCYC VCC

EQUATIONS

PA3 = LDIR2 * /LDIRl * /LDIRO

+ LDIR3 * /LDIR2 * /LDIRl * /LDIRO

PA3.TRST = BOFF_BUF_EN

PA2 = LDIRl * /LDIRO

+ LDIR3 * /LDIR2 * /LDIRl * /LDIRO

PA2.TRST = BOFF BUF EN

LDIR3 := /LDIR3 * PA2 * PA3 * L_ADS * TAG_WR_REQ * /BOFF_REQ * /CPURDY

+ /LDIR3 * /DIR3 * L_ADS * BOFF_REQ * /CPURDY

+ /LDIR3 * /DIR3 * /PA2 * L_ADS * TAG_WR_REQ * /BOFF REQ * /CPURDY 4- /LDIR3 * /DIR3 * /PA3 * L_ADS * TAG_WR_REQ * /BOFF_REQ * /CPURDY

+ LDIR3 * BOFF_BUF_EN * /CPURDY

+ LDIR3 * BOFF_BUF_EN * CPURDY * /PA2

+ LDIR3 * BOFF_BUF_EN * CPURDY * /PA3

+ LDIR3 * /BOFF_BUF_EN * /ISTCYC

LDIR2 := /LDIR2 * /PA2 * PA3 * L_ADS * TAG_WR_REQ * /BOFF_REQ * /CPURDY

+ /LDIR2 * /DIR2 * L_ADS * BOFF_REQ * /CPURDY

10 + /LDIR2 * /DIR2 * PA2 * L_ADS * TAG_WR_REQ * /BOFF_REQ * /CPURDY

+ /LDIR2 * /DIR2 */PA3 * L_ADS * TAG_WR_REQ * /BOFF_REQ * /CPURDY

+ LDIR2 * BOFF_BUF_EN * /CPURDY

^~X> + LDIR2 * BOFF_BUF_EN * CPURDY * PA2

+ LDIR2 * BOFF_BUF_EN * CPURDY */PA3

+ LDIR2 * /BOFF_BUF_EN */ISTCYC LDIRl := /LDIRl * PA2 * /PA3 * L_ADS * TAG_WR_REQ * /BOFF_REQ * /CPURDY

+ /LDIRl * /DIRl * L_ADS * BOFF_REQ * /CPURDY

+ /LDIRl * /DIRl * /PA2 * L_ADS * TAG_WR_REQ * /BOFF_REQ * /CPURDY

+ /LDIRl * /DIRl * PA3 * L_ADS * TAG_WR_REQ * /BOFF_REQ * /CPURDY

+ LDIRl * BOFF_BUF_EN * /CPURDY

+ LDIRl * BOFF_BUF_EN * CPURDY * /PA2

+ LDIRl * BOFF_BUF_EN * CPURDY * PA3

+ LDIRl * /BOFF BUF EN * /ISTCYC

LDIRO := /LDIRO * /PA2 * /PA3 * L_ADS * TAG_WR_REQ * /BOFF_REQ * /CPURDY

+ /LDIRO * /DIRO * L_ADS * BOFF_REQ * /CPURDY

+ /LDIRO * /DIRO * PA2 * L_ADS * TAG_WR_REQ

* /BOFF_REQ * /CPURDY

+ /LDIRO * /DIRO * PA3 * L_ADS * TAG_WR_REQ

* /BOFF_REQ * /CPURDY

+ LDIRO * BOFF_BUF_EN */CPURDY

+ LDIRO * BOFF BUF EN * CPURDY * PA2 + LDIRO * BOFF BUF EN * CPURDY * PA3

+ LDIRO */BOFF_BUF_EN */ISTCYC

DIRTY = ALL * DIRO * DIRl * DIR2 * DIR3

+ /ALL * /PA3 * /PA2 * DIRO

+ /ALL * /PA3 * PA2 * DIRl

+ /ALL * PA3 * /PA2 * DIR2

+ /ALL * PA3 * PA2 * DIR3

+ /WB EN

LAST_DIRTY - BOFF_BUF_EN * LDIR3 * /LDIR2 * /LDIRl * /LDIRO

+ BOFF_BUF_EN */LDIR3 * LDIR2 * /LDIRl * /LDIRO

+ BOFF_BUF_EN */LDIR3 * /LDIR2 * LDIRl * /LDIRO

+ BOFF_BUF_EN */LDIR3 * /LDIR2 * /LDIRl

+/BOFF BUF EN * DIRO * DIRl * DIR2 * DIR3

Claims

1. A self-controlled microcomputer write back cache memory apparatus for the controlled storage of digital data in a high speed microcomputer where said apparatus is connected between and is transpar¬ ent to the CPU and the main memory of said microcom¬ puter and which apparatus serves to interrupt the CPU and independently control the control bus, address bus and data bus within said microcomputer toward manipulating and storing digital data between the CPU and the main memory so as to minimize the time required to satisfy the CPU's request for digital data and thus enhance the overall perform¬ ance of the microcomputer, said self controlled microcomputer write back cache memory apparatus comprising:

- memory means operably connected to said address bus, said control bus and said data bus of said microcomputer, said memory means serving to store storing said digital data in the form of cache lines containing a data word corresponding to the digital data requested by the CPU, a tag correspond¬ ing to a portion of the digital address in said main memory at which said data word is stored, a validity bit indicating the validity of said data, and a dirty bit indicating whether the data word associated with said tag is also stored in said main memory;

- comparator means operably connected to said memory means for determining whether said digital data requested by said CPU is stored in said memory means and generating as an output a signal indicat¬ ing whether said digital data is present in said memory means and thus need not be retrieved from said main memory, or alternative whether said digital data is not present said memory means thus requiring that said digital data be retrieved from said main memory of said microprocessor;

- cache controller means operably connected to said CPU, said memory means, and said comparator means acting as a master device serving to generate and assert the appropriate control signals otherwise produced by said CPU to produce a memory write cycle to control the writing of digital data from said cache memory to said main memory;

- address bus write back buffer means serving to transmit control signals generated by said cache controller means to said address bus and said con¬ trol bus toward manipulating said main memory and said CPU;

- data buffer means for alternatively enabling and disabling said main memory to prevent said CPU from accessing said main memory means when said digital data requested by said CPU is available in said memory means of said apparatus.

2. The invention according to Claim 1 in which said memory means comprises: - cache memory means for storing said data word portion of said cache line;

- tag cache means for storing said tag portion of said cache line;

- status cache means for storing said validity bit and said dirty bit portion of said cache line. 3. In a write back cache memory device of the type which is connected between the CPU and the main memory of the microcomputer and which serves store digital data in the form of cache lines in a cache memory toward transferring said digit data between said main memory and said CPU in a manner designed to minimize the time required to satisfy the CPU's request for digital data, the improvement which comprises: - a self controlled cache controller connected to said CPU, said cache memory and said main memory for independently interrupting the CPU and independ¬ ently controlling said control bus, address bus and data bus within the microcomputer toward manipulat- ing and storing said digital data in a manner which frees said CPU to perform other tasks unrelated to reading and writing digital data thus further en¬ hancing the performance of said microcomputer.

AMENDED CLAIMS

[received by the International Bureau on 7 September 1993 (07.09.93); original claims 1-3 replaced by amended claims 1-5 (4 pages)]

1. A cache controller apparatus for controlling an external write-back cache memory and arbitrating a system bus, the system bus containing a data bus, an address bus and a control bus, which link togeth¬ er devices in a system including, a microprocessor unit being connected to the system through the system bus, cache memory storing a plurality of cache lines, each of said cache lines containing data, an address tag, one or more validity bits and one or more dirty bits, a main memory connected to the system through the system bus, said cache controller apparatus comprising:

- means for determining the state of said data in said cache memory with respect to a microproces¬ sor memory access command, said determining means connected to said cache memory directly and to said microprocessor unit through the system bus, said determining means serving to determine whether said microprocessor memory access command necessitates a cache write-back cycle; - means for maintaining status information in said plurality of cache lines, such that said deter¬ mining means may determine the current state of any of said data contained within said plurality of cache lines; - means for servicing said microprocessor memory access command when said cache write-back cycle is not necessary, said service means connected directly to said cache memory;

- means for direfcting said cache write-back cycle, connected to said system through the system bus for transparently controlling the writing of one or more cache lines from said cache memory to said main memory, said write-back cycle serving to simu- late said system bus cycle controlled by said micro¬ processor unit; and

- means for preventing said main memory from responding to said microprocessor memory access command when said servicing means is servicing said microprocessor memory access command; said cache memory being directly connected to said microprocessor unit through said data bus, whereby delay in transferring data between said microprocessor unit and said cache memory is sub- stantially minimized.

2. In the invention according to Claim 1 wherein said determining means comprises: means for comparing said address tag con- tained within said cache line accessed by said microprocessor memory access command to a portion of a main memory address contained within said micro¬ processor memory access command to determine whether a cache-hit has occurred; - means for verifying the validity of said data contained within said accessed cache line; means for establishing whether said data contained within said accessed cache line may differ from a value existing in a corresponding location in said main memory, said establishing means utilizing

' said one or more dirty bits contained within said accesssed cache line; and said determining means determining whether said microprocessor memory access command necessi- tates a cache write-back cycle based upon said 0

comparing means, said verifying means, said estab¬ lishing means and whether said microprocessor memory access command is a memory write cycle.

3. The invention according to Claim 1 wherein said directing means comprises: means for latching a main memory address contained within said microprocessor memory access command such that said main memory address may be placed onto the address bus during said cache write¬ back cycle;

- means for forcing said microprocessor unit to relinquish the system bus, said forcing means fur¬ ther causing said microprocessor unit to reassert said microprocessor memory access command at the completion of said cache write-back cycle;

- means for causing said main memory to write said data into said main memory address placed onto the address bus by said latching means, said causing means simulating a microprocessor write cycle to obviate the need for a specialized cache write-back cycle; and means for terminating said cache write-back cycle after said main memory has accepted said data thereby allowing said forcing means to cause said microprocessor memory, access command to be reas¬ serted by said microprocessor unit.

4. The invention according to Claim 3 wherein said invention microprocessor unit is of the INTEL 386 and 486 microprocessor family, having a BOFF signal which causes said microprocessor unit to back off the system bus while it is asserted, said forc¬ ing means utilizes said BOFF signal. 3 1

5. A method of controlling a system for a cache memory write-back cycle in a system including, a system bus containing a data bus, an ad¬ dress bus and a control bus, which link together devices in the system, a microprocessor unit being connected to the system through the system bus, cache memory connected directly on the data bus, said cache memory storing a plurality of cache lines, each of said cache lines containing data, an address tag, one or more validity bits and one or more dirty bits, a main memory connected to the system through the system bus, the method comprising the steps of:

(a) latching a write-back address from the address bus, the write-back address having been asserted by the microprocessor unit during a micro¬ processor memory access command that necessitated the cache write-back cycle;

(b) forcing the microprocessor unit to relinquish the system bus;

(c) placing the latched write-back address onto the address bus and a microprocessor memory write command onto the control bus;

(d) writing the data from the location in the cache memory corresponding to the write-back address into the main memory, so as to preserve the data from the cache memory; and (e) relinquishing control of the system bus, thus allowing the microprocessor unit to restart the microprocessor memory access command which had previously necessitated the cache write-back cycle.