WO1993019487A1 - Integrated circuit module having microscopic self-alignment features - Google Patents

Integrated circuit module having microscopic self-alignment features Download PDF

Info

Publication number
WO1993019487A1
WO1993019487A1 PCT/US1993/002602 US9302602W WO9319487A1 WO 1993019487 A1 WO1993019487 A1 WO 1993019487A1 US 9302602 W US9302602 W US 9302602W WO 9319487 A1 WO9319487 A1 WO 9319487A1
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuit
holes
input
circuit module
output pads
Prior art date
Application number
PCT/US1993/002602
Other languages
French (fr)
Inventor
Mohammad Akhavain
Ken Walter Economy
Original Assignee
Unisys Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Unisys Corporation filed Critical Unisys Corporation
Priority to JP51677293A priority Critical patent/JP3215424B2/en
Publication of WO1993019487A1 publication Critical patent/WO1993019487A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10135—Alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/10165—Alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/10175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16111—Disposition the bump connector being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8012—Aligning
    • H01L2224/80136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/80138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8014—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/81139—Guiding structures on the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8114—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/81141—Guiding structures both on and outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion

Definitions

  • the embodiments of all of the FIG's. 1 thru 8 can be modified by replacing the polyimide stack 12c with additional ceramic layers on the ceramic substrate 12b. With this modification, the input/output pads 12d of the interconnect member would lie on the top ceramic layer. Also, one extra layer of ceramic could be added to the top of the substrate in which alignment holes are patterned which correspond to the holes in layer 12e of FIG's. 1, 2A- 2F, and 3A-3C. Likewise, this extra ceramic layer could have holes which correspond to the holes in the top layer of stack 31 in Fig. 5; or the holes in layer 51 in Fig. 7, or the holes in the top layer of stack 61 in Fig. 8.

Abstract

An integrated circuit module (Figs. 2A-2F) having microscopic self-alignment features comprises: 1) an integrated circuit chip (11a) having a plurality of input/output pads (11b) in a pattern on a surface thereof; 2) an interconnect member (12c) having a surface which includes input/output pads (12d) in a pattern that matches the pattern of pads on the integrated circuit chip; and, 3) one of the surfaces (12e-12f) has a predetermined number of holes of one-half to fifty mils deep and the other surface has a predetermined number of protrusions (11c) of one-half to fifty mils high which are shaped to fit into the holes and prevent the surfaces from sliding on each other when the input/output pads on both of the surfaces are aligned.

Description

INTEGRATED CIRCUIT MODULE HAVING MICROSCOPIC SELF-ALIGNMENT FEATURES
BACKGROUND OF THE INVENTION
This invention relates to integrated circuit modules of the type in which one or more integrated circuit chips are mounted on an interconnect member such that multiple input/output pads on each chip are connected to corresponding input/output pads on the interconnect member. In the above type of integrated circuit module of the prior art, the interconnect member has included a substrate which holds a single chip or which holds multiple chips. This substrate can be made of ceramic or silicon or epoxy glass. Thousands of patterned conductive signal lines are provided within and/or on top of the substrate; and, those signal lines include input/output pads which are arranged in a pattern that matches the input/output pads on each chip. One example of such a prior art interconnect member is described in United States patent 4,721,831 entitled "Module for Packaging and Electrically Intercon¬ necting Integrated Circuit Chips on a Porous Substrate, and Method of Fabricating Same" by H. Vora issued 01/26/88. There, in Fig. 1, reference numeral 10 identifies the interconnect module and reference numeral 12 identifies the chips; and in Fig. 2, reference numeral 21 identifies the input/output pads on the interconnect module. Now, a technical problem which somehow needs to be solved when fabricating integrated circuit modules of the above type is how to align the input/output pads on each chip with the corresponding input/output pads on the interconnect module while the chips are being attached to the interconnect module. This is a difficult problem because the input/output pads typically have small dimen¬ sions (e.g. - ten mils), are large in total number (e.g. - one hundred) , and are blocked from view by the chip when the chip is placed on top of the interconnect member. However, if the input/output pads on a chip get misaligned with the corresponding input/output pads on the module, all electrical signals (including data signals, control sig¬ nals, power and ground signals) will be misrouted to and from the chip; and, the resulting structure will be co - pletely inoperable.
In the prior art, this problem of how to align the input/output pads on a chip to the input/output pads on an interconnect module was overcome by using specialized alignment machines. But, those machines are very complex and thus are very expensive. One such machine, for exam¬ ple, called a "M-9" from the Research Devices Division of the American Optical Corporation, provides an infrared light beam to "see" through the chip and thereby view when the input/output pads on the chip and the interconnect module are in line. But, this machine costs over $100,000. Another machine, called a MRSI-503M from Micro Robotics Systems, Inc. provides an optical probe with dual optical paths which fits between the chip and the substrate as they are positioned over each other so that their input/output pads can be viewed and lined up. But, this machine also costs over $100,000. Further, the above costs are for manually operated versions of both machines; automated versions cost over $200,000.
Accordingly, a primary object of the present invention is to provide an improved integrated circuit module that includes novel microscopic physical features on the chips and on the interconnect module which enable their input/output pads to be self-aligned without any alignment equipment.
BRIEF SUMMARY OF THE INVENTION In accordance with the present invention, an integrated circuit module having microscopic self-alignment features comprises: a) an integrated circuit chip having a plurality of input/output pads in a pattern on a surface thereof, b) an interconnect member having a surface which includes input/output pads in a pattern that matches the pattern of pads on the integrated circuit chip, and c) one of the surfaces has a predetermined number of holes that are one-half to fifty mils deep, and the other surface has a predetermined number of protrusions that are one-half to fifty mils high and which are shaped to fit into the holes and prevent the surfaces from sliding on each other when the input/output pads on both of the surfaces are aligned. With this structure, the input/output pads on the chip are aligned automatically with the input/output pads on the interconnect member without any alignment equipment by the steps of placing the chip on the interconnect member such that the protrusions separate the two surfaces; and, sliding the chip by hand in random directions on the interconnect member until the protrusions drop into the holes and stop the sliding motion. This stopping of the sliding action indicates that alignment has occurred. Thereafter, the aligned input/output pads are joined together by reflowing a solder paste between them. BRIEF DESCRIPTION OF THE DRAWINGS
Various preferred embodiments of the present invention are described in detail herein in conjunction with the accompanying drawings wherein: Fig. 1 is an enlarged sideview of an integrated circuit module which is a first embodiment of the inven¬ tion;
FIG's. 2A thru 2F are further enlarged views of a portion of the Fig. 1 module which show a preferred process by which the module is fabricated;
FIG's. 3A thru 3C are icrophotos of certain parts of an actual module that was fabricated by the process of FIG's. 2A thru 2F;
Fig. 4 is an enlarged view of a portion of another integrated circuit module which is a first modifi¬ cation to the Fig. 1 module;
Fig. 5 is an enlarged view of a portion of another integrated circuit module which is a second modifi¬ cation to the Fig. 1 module; Fig. 6 is an enlarged view of a portion of another integrated circuit module which is a third modifi¬ cation to the Fig. 1 module;
Fig. 7 is an enlarged view of a portion of another integrated circuit module which is a fourth odifi- cation to the Fig. 1 module; and.
Fig. 8 is an enlarged view of a portion of another integrated circuit module which is a fifth modifi¬ cation to the Fig. 1 module. DETAILED DESCRIPTION
Referring now to Fig. 1, it shows a magnified view of an integrated circuit module 10 which is one preferred embodiment of the present invention. Included in this module 10 are a plurality of integrated circuit chips 11 and an interconnect member 12 for those chips. Ref¬ erence numerals 11a, lib, and lie indicate the principal parts of each of the chips 11 which are relevant to the present invention. Likewise, reference numerals 12a, 12b, 12c, 12d, 12e, and 12f indicate the principal parts of the interconnect member 12 which are relevant to the present invention.
Part 11a is a silicon die on which thousands of transistors have been made by any conventional integrated circuit fabrication process. Part lib is an input/output pad on a surface of the die 11. And, part lie is a reflow¬ ed solder bump which prior to being reflowed was attached to one of the input/output pads lib but not to the inter¬ connect member 12. Part 12a is an input/output pin. Part 12b is a co-fired multi-layer ceramic substrate having thousands of patterned conductive signal lines (not shown) which lie on and go through the ceramic layers. Part 12c is a stack of several layers of polyimide, having thousands of patterned conductive signal lines (not shown) on each polyimide layer, which is integrated onto the substrate 12b. Part 12d is an input/output pad on the polyimide stack 12c. Part 12e is a layer of photoresist which has holes over each of the input/output pads 12d. And, part 12f is a reflowed solder fillet which prior to being reflowed was attached to an input/output pad 12d and partially filled the hole in the photoresist layer 12e. On each chip 11, the input/output pads lib are arranged in some particular pattern; and, on the inter¬ connect member 12, the input/output pads 12d are arranged in a matching pattern. These matching patterns of the input/output pads lib and 12d must be aligned before the solder lie and 12f is reflowed. Otherwise, if the input/- output pads lib and 12d are misaligned, the electrical signals which those pads carry between the chip 11 and the interconnect member 12 will be routed incorrectly. Now, in accordance with the present invention, the input/output pads lib are aligned automatically with the input/output pads 12d by simply positioning the solder bumps lie into the holes of the photoresist layer 12e. This positioning of the solder bumps lie into the holes of layer 12e is easily achieved without any expensive align¬ ment equipment by the steps of: a) placing the chip 11 on the interconnect member 12 such that the solder bumps lie rest on the photoresist layer 12e; and b) sliding the chip 11 by hand in random directions on the photoresist layer 12d until the solder bumps lie drop into the photoresist layer holes and stop sliding. This stopping of the sliding action can be felt, and it indicates that alignment has occurred. Thereafter, the solder lie and 12f is reflowed so that it joins the aligned input/output pads. To fully appreciate the difficulty of the align¬ ment problem which the above steps a) and b) overcome, recall that in Fig. 1 the module 10 is magnified so that all of the parts lla-llc and 12a-12f can be seen. However, in the actual module 10, the dimensions of the parts lib, lie, 12c, 12d, 12e, and 12f are microscopic.
In particular, the solder bumps lie are between one-half mil and fifty mils high; the patterned layer 12e is between one-half mil and fifty mils thick; and, the depth of the holes that are provided in layer 12e into which the solder bumps drop are less than the thickness of that layer. However, those holes must be at least one-half mil deep in order for the sidewalls of the holes to resist the sliding motion of the solder balls with a force of at least one pound so that it can be felt. Preferably, to provide extra slide resisting force and accommodate varia¬ tions in flatness between the chip 11 and interconnect member 12, the holes in layer 12e into which the solder bumps drop are at least one mil deep. Also preferably, to increase the packing density of the solder bumps lie, those bumps are one to twenty mils high and layer 12e is one to twenty mils thick. In the Fig. 1 modules, the total number of input/output pads lib on any one chip 11 can be several thousand. Each such pad is between one mil and fifty mils on a side, and the spacing between pads can be as small as the thickness of layer 12e. Consequently, without provid- ing the holes in the patterned resist layer 12e for the solder bumps lie to fall into, it is essentially impossible to align the input/output pads by hand.
Referring next to FIG's. 2A-2F, they show a complete process for fabricating the module 10. Initially in this process, the patterned photoresist layer 12e is formed by covering parts 12c and 12d of the interconnect member 12 with an unpatterned layer of photoresist, expos¬ ing the unpatterned photoresist layer to ultraviolet light through a mask which blocks the light over just the input/- output pads 12d, and removing the unexposed photoresist. Fig. 2A shows the result of this step. Here, the mask which blocks the light over the input/output pads can be aligned with those pads within a tenth of a micron by a mask aligner, such a model MA56W from Karl Suss Corporation for example.
Thereafter, as is shown in Fig. 2B, the openings in the photoresist layer 12e are filled with a solder paste 12f. This is achieved by pushing the solder paste 12f into the openings with a "squeegee". One example of a suitable material is a fine pitch solder paste having a minus 400 mesh size from Heraeus, Inc. Subsequently, the structure of Fig. 2B is sub¬ jected to a high temperature for a predetermined time interval in order to vaporize and remove a portion of the solder paste 12f' leaving the fillets 12f. Fig. 2C shows the result of this step. This high temperature vaporizing step is carried out by passing the structure of Fig. 2B through an infrared heating belt furnace having a prede¬ termined temperature profile which is set as a function of the particular solder that is used. As an example of the above step, one actual part was subjected to a peak temper¬ ature of 220°C for 30 seconds.
Following the above steps, an integrated circuit chip 11 having solder bumps lie attached to its input/- output pads lib is placed on top of the Fig. 2C structure. Fig. 2D shows the result of this step. To fabricate the solder bumps lie on the chip 11, a stencil is placed on the chips such that openings in the stencil expose just the input/output pads lib; solder paste is pushed through the stencil openings onto the input/output pads lib; the stencil is lifted off of the chip 11; and the solder is heated until it forms a ball due to surface tension. Here, the stencil for the solder paste is aligned to the input/- output pads lib within + or - one mil using a screen printer, such as model AP-20 from MPM corporation. Thereafter, the input/output pads lib on the chip
11 are aligned with the input/output pads 12d of the interconnect member 12 by sliding the chip 11 in random directions until the solder bumps lie drop into the holes of photoresist layer 12e. This alignment step is performed by feel only; no precise visual alignment equipment is involved. When the chip 11 can no longer slide because its solder bumps lie are caught in the holes of the photoresist layer 12e, alignment has been achieved. Following the above alignment step, the solder bumps lie are reflowed in order to physically join the input/output pins lib and 12d. Fig. 2F shows the results of this step. Here again the reflow is achieved by sub- jecting the Fig. 2E structure to a temperature which is high enough to soften the solder for a few seconds.
Turning now to FIG's. 3A-3C, some microphotos of an actual module 10 at various stages of its fabrication will be described. Beginning with Fig. 3A, it shows the interconnect member 12 on which the photoresist layer 12e has been formed with openings over just the input/output pads 12d. This microphoto corresponds to the previously described Fig. 2A.
Next, Fig. 3B shows the interconnect member 12 after the holes in the photoresist layer 12e have been partially filled with solder paste. 12f. This microphoto corresponds to the previously described Fig. 2C.
In the FIG's. 3A and 3B, the photoresist layer 12e is only four mils thick; the holes in layer 12e are only seven mils in diameter; the edge-to-edge spacing between the holes of each row also is only seven mils; and the depth of the holes after they have been partially filled with the solder paste 12f is two mils. These microscopic dimensions, which result in a hole-to-hole pitch of fourteen mils, are evidenced by the scale that is imprinted on the photos.
Lastly, Fig. 3C shows the chip 11 after the solder bumps lie have been formed on the input/output pads lib. In this microphoto, the chip 11 is as shown in the previously described FIG's. 2A and 2D. Also in this micro¬ photo, the solder bumps lie are only three to four mils high. One preferred embodiment of the invention, as well as a preferred process for fabricating that embodi¬ ment, have now been described in detail. In addition, however, various modifications can be made to that embodi- ment without departing from the nature and spirit of the invention. Some of these modifications are illustrated in FIG's. 4-8.
Considering now Fig. 4, it shows the details of a first modification 20 to the integrated circuit module 10. This modified module 20 includes a patterned photo¬ resist layer 21 on the chip 11 (rather than the layer 12e on the interconnect member 12); and it includes solder bumps 22 on the interconnect member 12 (rather than the bumps lie on the chip 11). Layer 21 has respective open- ings over the input/output pads lib of the chip 11, and those openings are partially filled with solder fillets 23. All other parts of the module 20 are the same as the previously described module 10, and like parts are identi¬ fied by like reference numerals. Next, turning to Fig. 5, it shows the details of another modified embodiment 30 of an integrated circuit module. In module 30, a stack 31 of polyimide layers is included on the interconnect member 12; and, the top layer of the stack 31 has through holes over the input/output pads 12d. This top layer of the stack 31 replaces the photoresist layer 12c of the previously described module
10. All other parts of module 30 are the same as in module
10, and they are identified with like reference numerals.
Next, considering Fig. 6, it shows the details of still another modified embodiment 40. This module 40 is identical to the previously described module 10 except that the solder fillets 12f in the photoresist layer 12c are eliminated. Here, the solder bumps lie are made larger than the thickness of the photoresist layer 12e so that the solder bumps lie rest directly on the input/output pads 12d of the interconnect member 12 after alignment has occurred. Here again, like parts between the modules 10 and 40 have the same reference numerals.
Next, referring to Fig. 7, it shows the details of yet another modified embodiment 50. In module 50, a photoresist layer 51 is provided on the interconnect member 12; one or more openings are patterned in the layer 51; and, each opening has a perimeter that matches the perime¬ ter of a group of several solder bumps lie on the chip 11. When an entire group of solder bumps lie drops into an opening in the photoresist layer 51, all of the solder bumps lie in that group are aligned with their correspond¬ ing input/output pads 12d on the interconnect member 12. With this embodiment 50, multiple openings in layer 51 may be provided for each chip 11, or only a single opening may be provided for each chip.
Next, turning to Fig. 8, it shows the details of still another modified embodiment 60. In this module 60, a stack 61 of polyimide layers is provided on the inter¬ connect member 12; several spaced apart openings go through the top layer of the stack 61; and, a layer of photoresist 62 is provided on the chip 11 which is shaped to fit into the openings of the stack 61. When the resist layer 62 is in the opening of stack 61, the input/output pads lib on the chip 11 are aligned with the input/output pads 12d on the interconnect member 12. These openings in the top layer of the stack 61 can have various patterns such as elongated slots by two edges of the chip 11, or one rectan¬ gle by each corner of the chip. As an alternative in the module 60, the top layer in the polyimide stack 61 can have just one respective opening for each chip 11. For example, the opening can be a slot which lies along the entire perimeter of the chip 11. As before, the photoresist layer 62 is patterned to fit into the opening in the top layer of the stack 61. As still another variation to all of the embodi¬ ments of FIG. 1 thru Fig. 8, the patterned photoresist layers can be made of a different insulating material. For exa ple, those layers (part 12e of Fig. 1, part 21 in Fig. 4, part 12e of Fig. 6, part 51 in Fig. 7, and part 62 in Fig. 8) can be made of a polyimide or silicon dioxide or silicon nitride. Likewise, the top layer of polyimide in FIG's. 5 and 8 (the top layer of stack 31 and 61) can be made of other materials such as photoresist or silicon dioxide or silicon nitride.
Similarly, the embodiments of all of the FIG's. 1 thru 8 can be modified by replacing the polyimide stack 12c with additional ceramic layers on the ceramic substrate 12b. With this modification, the input/output pads 12d of the interconnect member would lie on the top ceramic layer. Also, one extra layer of ceramic could be added to the top of the substrate in which alignment holes are patterned which correspond to the holes in layer 12e of FIG's. 1, 2A- 2F, and 3A-3C. Likewise, this extra ceramic layer could have holes which correspond to the holes in the top layer of stack 31 in Fig. 5; or the holes in layer 51 in Fig. 7, or the holes in the top layer of stack 61 in Fig. 8. As still one other variation to all of the embodiments that are described above, the chip 11 can be replaced by a stack of chips which are glued together and have input/output leads on one surface of the stack. Such a chip stack is described, for example, in U.S. Patent 4,959,749 which issued September 25, 1990. Therefore, in this description and the claims which follow, the word "chip" shall mean a single chip or a chip stack.
A structural feature which is generic to all of the embodiments of Fig. 1 thru Fig. 8 and their above described modifications is that the chip 11 and intercon¬ nect member 12 have respective surfaces with input/output pads that must be aligned; and, to accomplish that align¬ ment, one of the surfaces has at least one hole of one-half mil to fifty mils deep and the other surface has a certain number of protrusions of one-half mil to fifty mils high which fit into and catch on the hole sidewalls when the input/output pads on both surfaces are aligned. These protrusions can be extensions of the input/output pads (as in the embodiments of FIG's. 1 thru 7), or they can be separate from the input/output pads (as in the embodiment of Fig. 8). Further, multiple holes can be provided for the protrusions to fit into (as in the embodiments of FIG's. 1 thru 5), or a single hole can be provided (as in the embodiments of FIG's. 7 and 8).
Accordingly, since the present invention can be embodied in many different structures, it is to be under- stood that the present invention is not limited to any particular one of the detailed structures shown in Fig. 1 thru Fig. 8 but is defined by the appended claims.

Claims

WHAT IS CLAIMED:
1. An integrated circuit module, at an intermediate stage of manufacturing, having microscopic self-alignment features, comprising: an integrated circuit chip having a plurality of input/output pads in a pattern on a surface thereof; an interconnect member having a surface which includes input/output pads in a pattern that matches said pattern of pads on said integrated circuit chip; one of said surfaces having an electrical insulating layer with a predetermined number of holes which encompass said pads on said one surface; each of said pads on the other surface having a single solder ball; and, said holes being shaped such that said solder balls fit therein and prevent said surfaces from sliding on each other only when said input/output pads on both of said surfaces are aligned.
2. An integrated circuit module according to claim 1 wherein said one surface has multiple holes and said other surface has a single respective solder ball for each hole.
3. An integrated circuit module according to claim 1 wherein said one surface has multiple holes and said other surface has a respective group of several solder balls for each hole.
4. An integrated circuit module according to claim 1 wherein said one surface has just a single hole and said other surface has multiple solder balls all of which fit into said single hole.
5. An integrated circuit module according to claim 1 wherein said insulating layer with said holes is on said interconnect member, and said solder balls are on said integrated circuit chip.
6. An integrated circuit module according to claim
1 wherein said insulating layer with said holes is on said integrated circuit chip, and said solder balls are is on said interconnect member.
7. An integrated circuit module according to claim
2 wherein said holes in said insulating layer are partially filled with solder.
8. An integrated circuit module according to claim
7 wherein said holes are one-half to fifty mils deep and said solder balls are one-half to fifty mils high.
9. An integrated circuit module according to claim
8 wherein said holes are defined by a patterned layer of material selected from photoresist, polyimide, silicon dioxide, silicon nitride, and ceramic.
PCT/US1993/002602 1992-03-24 1993-03-23 Integrated circuit module having microscopic self-alignment features WO1993019487A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP51677293A JP3215424B2 (en) 1992-03-24 1993-03-23 Integrated circuit module with fine self-alignment characteristics

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US85659292A 1992-03-24 1992-03-24
US07/856,592 1992-03-24

Publications (1)

Publication Number Publication Date
WO1993019487A1 true WO1993019487A1 (en) 1993-09-30

Family

ID=25324019

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1993/002602 WO1993019487A1 (en) 1992-03-24 1993-03-23 Integrated circuit module having microscopic self-alignment features

Country Status (3)

Country Link
US (1) US5341564A (en)
JP (1) JP3215424B2 (en)
WO (1) WO1993019487A1 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0645807A1 (en) * 1993-04-08 1995-03-29 Citizen Watch Co. Ltd. Semiconductor device
US5611013A (en) * 1994-06-14 1997-03-11 Telefonaktiebolaget Lm Ericsson Optical miniature capsule
US8115316B2 (en) 2006-08-30 2012-02-14 Sanyo Electric Co., Ltd. Packaging board, semiconductor module, and portable apparatus
CN107039488A (en) * 2015-10-28 2017-08-11 三星显示有限公司 Display device

Families Citing this family (63)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5611140A (en) * 1989-12-18 1997-03-18 Epoxy Technology, Inc. Method of forming electrically conductive polymer interconnects on electrical substrates
US5338208A (en) * 1992-02-04 1994-08-16 International Business Machines Corporation High density electronic connector and method of assembly
US5496775A (en) * 1992-07-15 1996-03-05 Micron Semiconductor, Inc. Semiconductor device having ball-bonded pads
US5824569A (en) * 1992-07-15 1998-10-20 Micron Technology, Inc. Semiconductor device having ball-bonded pads
US6077725A (en) * 1992-09-03 2000-06-20 Lucent Technologies Inc Method for assembling multichip modules
US5766670A (en) * 1993-11-17 1998-06-16 Ibm Via fill compositions for direct attach of devices and methods for applying same
US6414506B2 (en) 1993-09-03 2002-07-02 Micron Technology, Inc. Interconnect for testing semiconductor dice having raised bond pads
US5700715A (en) * 1994-06-14 1997-12-23 Lsi Logic Corporation Process for mounting a semiconductor device to a circuit substrate
US5578874A (en) * 1994-06-14 1996-11-26 Hughes Aircraft Company Hermetically self-sealing flip chip
US6169328B1 (en) * 1994-09-20 2001-01-02 Tessera, Inc Semiconductor chip assembly
DE29500428U1 (en) * 1995-01-12 1995-03-30 Hewlett Packard Gmbh Connecting component
US5677566A (en) * 1995-05-08 1997-10-14 Micron Technology, Inc. Semiconductor chip package
US5872051A (en) * 1995-08-02 1999-02-16 International Business Machines Corporation Process for transferring material to semiconductor chip conductive pads using a transfer substrate
US5724229A (en) * 1996-03-27 1998-03-03 Unisys Corporation Electromechanical assembly having a lid which protects IC chips and holds contact springs
US6310484B1 (en) * 1996-04-01 2001-10-30 Micron Technology, Inc. Semiconductor test interconnect with variable flexure contacts
US6148512A (en) * 1996-04-22 2000-11-21 Motorola, Inc. Method for attaching an electronic device
US5822856A (en) * 1996-06-28 1998-10-20 International Business Machines Corporation Manufacturing circuit board assemblies having filled vias
US5740605A (en) * 1996-07-25 1998-04-21 Texas Instruments Incorporated Bonded z-axis interface
US6221753B1 (en) * 1997-01-24 2001-04-24 Micron Technology, Inc. Flip chip technique for chip assembly
US6831361B2 (en) 1997-01-24 2004-12-14 Micron Technology, Inc. Flip chip technique for chip assembly
US5891754A (en) * 1997-02-11 1999-04-06 Delco Electronics Corp. Method of inspecting integrated circuit solder joints with x-ray detectable encapsulant
US6045030A (en) * 1997-03-13 2000-04-04 Raytheon Company Sealing electronic packages containing bumped hybrids
US6016060A (en) * 1997-03-25 2000-01-18 Micron Technology, Inc. Method, apparatus and system for testing bumped semiconductor components
US5953623A (en) * 1997-04-10 1999-09-14 International Business Machines Corporation Ball limiting metal mask and tin enrichment of high melting point solder for low temperature interconnection
US6040702A (en) * 1997-07-03 2000-03-21 Micron Technology, Inc. Carrier and system for testing bumped semiconductor components
JP2001510944A (en) * 1997-07-21 2001-08-07 アギラ テクノロジーズ インコーポレイテッド Semiconductor flip chip package and method of manufacturing the same
US6107122A (en) * 1997-08-04 2000-08-22 Micron Technology, Inc. Direct die contact (DDC) semiconductor package
US6072326A (en) * 1997-08-22 2000-06-06 Micron Technology, Inc. System for testing semiconductor components
US6018249A (en) * 1997-12-11 2000-01-25 Micron Technolgoy, Inc. Test system with mechanical alignment for semiconductor chip scale packages and dice
JP3625646B2 (en) 1998-03-23 2005-03-02 東レエンジニアリング株式会社 Flip chip mounting method
US6189208B1 (en) 1998-09-11 2001-02-20 Polymer Flip Chip Corp. Flip chip mounting technique
JP3056192B1 (en) * 1999-01-18 2000-06-26 富山日本電気株式会社 Method of manufacturing mounting board with solder resist layer having bumps formed on electrode pads
US6242935B1 (en) 1999-01-21 2001-06-05 Micron Technology, Inc. Interconnect for testing semiconductor components and method of fabrication
US6190940B1 (en) * 1999-01-21 2001-02-20 Lucent Technologies Inc. Flip chip assembly of semiconductor IC chips
US6819127B1 (en) 1999-02-19 2004-11-16 Micron Technology, Inc. Method for testing semiconductor components using interposer
US6242932B1 (en) 1999-02-19 2001-06-05 Micron Technology, Inc. Interposer for semiconductor components having contact balls
US6222280B1 (en) 1999-03-22 2001-04-24 Micron Technology, Inc. Test interconnect for semiconductor components having bumped and planar contacts
US6410415B1 (en) 1999-03-23 2002-06-25 Polymer Flip Chip Corporation Flip chip mounting technique
US6437591B1 (en) 1999-03-25 2002-08-20 Micron Technology, Inc. Test interconnect for bumped semiconductor components and method of fabrication
US6396291B1 (en) 1999-04-23 2002-05-28 Micron Technology, Inc. Method for testing semiconductor components
US6285203B1 (en) 1999-06-14 2001-09-04 Micron Technology, Inc. Test system having alignment member for aligning semiconductor components
JP3213292B2 (en) * 1999-07-12 2001-10-02 ソニーケミカル株式会社 Multilayer board and module
JP3973340B2 (en) * 1999-10-05 2007-09-12 Ｎｅｃエレクトロニクス株式会社 Semiconductor device, wiring board, and manufacturing method thereof
US6331453B1 (en) 1999-12-16 2001-12-18 Micron Technology, Inc. Method for fabricating semiconductor packages using mold tooling fixture with flash control cavities
CN1383197A (en) * 2001-04-25 2002-12-04 松下电器产业株式会社 Mfg. method of semiconductor device and semiconductor device
JP3835352B2 (en) * 2002-06-03 2006-10-18 株式会社デンソー Bump forming method and bonding method of substrate having bump and other substrate
US6720246B1 (en) * 2003-01-23 2004-04-13 Silicon Integrated Systems Corp. Flip chip assembly process for forming an underfill encapsulant
US20040232562A1 (en) * 2003-05-23 2004-11-25 Texas Instruments Incorporated System and method for increasing bump pad height
US20060068521A1 (en) * 2004-09-29 2006-03-30 Song-Hua Shi Method of fabricating microelectronic package using no-flow underfill technology and microelectronic package formed according to the method
US20060278979A1 (en) * 2005-06-09 2006-12-14 Intel Corporation Die stacking recessed pad wafer design
US7652374B2 (en) * 2006-07-31 2010-01-26 Chi Wah Kok Substrate and process for semiconductor flip chip package
US20080061448A1 (en) * 2006-09-12 2008-03-13 International Business Machines Corporation System and method for thermal expansion pre-compensated package substrate
US7993940B2 (en) * 2007-12-05 2011-08-09 Luminus Devices, Inc. Component attach methods and related device structures
US8424748B2 (en) * 2009-12-21 2013-04-23 Intel Corporation Solder in cavity interconnection technology
US8497575B2 (en) * 2010-02-22 2013-07-30 Stats Chippac Ltd. Semiconductor packaging system with an aligned interconnect and method of manufacture thereof
US8877567B2 (en) * 2010-11-18 2014-11-04 Stats Chippac, Ltd. Semiconductor device and method of forming uniform height insulating layer over interposer frame as standoff for semiconductor die
US10153180B2 (en) 2013-10-02 2018-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor bonding structures and methods
KR101504306B1 (en) * 2014-02-03 2015-03-30 주식회사 루멘스 Light emitting device package, backlight unit, lighting device and its manufacturing method
US10886250B2 (en) * 2015-07-10 2021-01-05 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US10276523B1 (en) * 2017-11-17 2019-04-30 General Electric Company Semiconductor logic device and system and method of embedded packaging of same
US10211141B1 (en) * 2017-11-17 2019-02-19 General Electric Company Semiconductor logic device and system and method of embedded packaging of same
US10566301B2 (en) 2017-11-17 2020-02-18 General Electric Company Semiconductor logic device and system and method of embedded packaging of same
US10396053B2 (en) 2017-11-17 2019-08-27 General Electric Company Semiconductor logic device and system and method of embedded packaging of same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2752438A1 (en) * 1976-12-13 1978-06-15 Ibm ARRANGEMENT FOR PACKING MONOLITHICALLY INTEGRATED SEMI-CONDUCTOR CIRCUITS
EP0329133A2 (en) * 1988-02-19 1989-08-23 Microelectronics and Computer Technology Corporation Flip substrate for chip mount
EP0337686A2 (en) * 1988-04-12 1989-10-18 Hitachi, Ltd. Semiconductor chip module
EP0356300A1 (en) * 1988-08-23 1990-02-28 Bull S.A. High-density integrated-circuit carrier, and method of manufacturing same
FR2646558A1 (en) * 1989-04-26 1990-11-02 Commissariat Energie Atomique METHOD AND MACHINE FOR INTERCONNECTING ELECTRICAL COMPONENTS BY WELDING ELEMENTS

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL292051A (en) * 1962-04-27
US3214827A (en) * 1962-12-10 1965-11-02 Sperry Rand Corp Electrical circuitry fabrication
US3380155A (en) * 1965-05-12 1968-04-30 Sprague Electric Co Production of contact pads for semiconductors
JPS5211862A (en) * 1975-07-18 1977-01-29 Matsushita Electric Ind Co Ltd Semiconductor device
JPS55115344A (en) * 1979-02-28 1980-09-05 Hitachi Ltd Method of forming projected electrode
JPS56148840A (en) * 1980-04-22 1981-11-18 Citizen Watch Co Ltd Mounting structure for ic
JPS57210638A (en) * 1981-06-18 1982-12-24 Mitsubishi Electric Corp Hybrid integrated circuit
JPS593958A (en) * 1982-06-29 1984-01-10 Elna Co Ltd Square-shaped chip parts and mounting device thereof
FR2541044A1 (en) * 1983-02-21 1984-08-17 Ebauchesfabrik Eta Ag Method for mounting a printed-circuit board on a substrate
US4565314A (en) * 1983-09-09 1986-01-21 At&T Bell Laboratories Registration and assembly of integrated circuit packages
JPS6072663A (en) * 1983-09-28 1985-04-24 Fujitsu Ltd Connecting method of low melting metallic ball
US4545610A (en) * 1983-11-25 1985-10-08 International Business Machines Corporation Method for forming elongated solder connections between a semiconductor device and a supporting substrate
US4836435A (en) * 1986-05-12 1989-06-06 International Business Machines Corporation Component self alignment
JPH07112041B2 (en) * 1986-12-03 1995-11-29 シャープ株式会社 Method for manufacturing semiconductor device
DE3735455A1 (en) * 1987-03-18 1988-09-29 Telefonbau & Normalzeit Gmbh ELECTRICAL COMPONENTS
US4912545A (en) * 1987-09-16 1990-03-27 Irvine Sensors Corporation Bonding of aligned conductive bumps on adjacent surfaces
JPH01183841A (en) * 1988-01-18 1989-07-21 Mitsubishi Electric Corp Lead frame
JPH0214536A (en) * 1988-07-01 1990-01-18 Oki Electric Ind Co Ltd Flip-chip mounting structure
JPH0272642A (en) * 1988-09-07 1990-03-12 Nec Corp Structure and method for connecting substrates
JPH03184353A (en) * 1989-12-13 1991-08-12 Sumitomo Metal Mining Co Ltd Film carrier with bump and manufacture thereof
AU645283B2 (en) * 1990-01-23 1994-01-13 Sumitomo Electric Industries, Ltd. Substrate for packaging a semiconductor device
US5007163A (en) * 1990-04-18 1991-04-16 International Business Machines Corporation Non-destructure method of performing electrical burn-in testing of semiconductor chips
JPH0429338A (en) * 1990-05-24 1992-01-31 Nippon Mektron Ltd Method circuit board for mounting ic and its mounting
US5075965A (en) * 1990-11-05 1991-12-31 International Business Machines Low temperature controlled collapse chip attach process

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2752438A1 (en) * 1976-12-13 1978-06-15 Ibm ARRANGEMENT FOR PACKING MONOLITHICALLY INTEGRATED SEMI-CONDUCTOR CIRCUITS
EP0329133A2 (en) * 1988-02-19 1989-08-23 Microelectronics and Computer Technology Corporation Flip substrate for chip mount
EP0337686A2 (en) * 1988-04-12 1989-10-18 Hitachi, Ltd. Semiconductor chip module
EP0356300A1 (en) * 1988-08-23 1990-02-28 Bull S.A. High-density integrated-circuit carrier, and method of manufacturing same
FR2646558A1 (en) * 1989-04-26 1990-11-02 Commissariat Energie Atomique METHOD AND MACHINE FOR INTERCONNECTING ELECTRICAL COMPONENTS BY WELDING ELEMENTS

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0645807A1 (en) * 1993-04-08 1995-03-29 Citizen Watch Co. Ltd. Semiconductor device
EP0645807A4 (en) * 1993-04-08 1997-10-08 Citizen Watch Co Ltd Semiconductor device.
US5611013A (en) * 1994-06-14 1997-03-11 Telefonaktiebolaget Lm Ericsson Optical miniature capsule
US8115316B2 (en) 2006-08-30 2012-02-14 Sanyo Electric Co., Ltd. Packaging board, semiconductor module, and portable apparatus
CN107039488A (en) * 2015-10-28 2017-08-11 三星显示有限公司 Display device
CN107039488B (en) * 2015-10-28 2022-01-18 三星显示有限公司 Display device

Also Published As

Publication number Publication date
US5341564A (en) 1994-08-30
JPH07505501A (en) 1995-06-15
JP3215424B2 (en) 2001-10-09

Similar Documents

Publication Publication Date Title
US5341564A (en) Method of fabricating integrated circuit module
EP0098932B1 (en) Repairable multi-level system for semiconductor device
EP1353374B1 (en) Semiconductor chip assembly and method of making the same
US5504277A (en) Solder ball array
JP4928945B2 (en) Bump-on-lead flip chip interconnect
US5744171A (en) System for fabricating conductive epoxy grid array semiconductor packages
TWI404114B (en) Flip chip interconnection having narrow interconnection sites on the substrate
US7608929B2 (en) Electrical connector structure of circuit board and method for fabricating the same
DE112018003103T5 (en) Pressure sensitive adhesive tape for high density connections
US8373276B2 (en) Printed wiring board and method for manufacturing the same
US5019997A (en) Adaptive lithography accommodation of tolerances in chip positioning in high density interconnection structures
US20080179740A1 (en) Package substrate, method of fabricating the same and chip package
US7151050B2 (en) Method for fabricating electrical connection structure of circuit board
KR100791662B1 (en) Support with solder globule elements and a method for assembly of substrates with globule contacts
DE102008010004A1 (en) Multi-chip package with reduced structure and method of making same
DE112004001678T5 (en) Method and apparatus for a package with two substrates
DE102019117199A1 (en) FAN-OUT PACKAGES AND METHOD FOR THE PRODUCTION THEREOF
US11610827B2 (en) Package and printed circuit board attachment
US6884939B2 (en) Constructing of an electronic assembly having a decoupling capacitor
DE102020100002A1 (en) FAN-OUT PACKAGES AND PROCESS FOR THEIR PRODUCTION
DE102019129870A1 (en) SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD
US20200020603A1 (en) Package and printed circuit board attachment
JP3908610B2 (en) Manufacturing method of multilayer wiring board
TWI708335B (en) Printed circuit board structure and method of fabricating the same
KR102310979B1 (en) Circuit board with constrained solder interconnect pads and manufacturing method thereof

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): JP

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FR GB GR IE IT LU MC NL PT SE

COP Corrected version of pamphlet

Free format text: PAGES 4-7,DESCRIPTION,AND PAGES 1/6 AND 4/6,DRAWINGS,REPLACED BY NEW PAGES BERING THE SAME NUMBER;DUE TO LATE TRANSMITTAL BY THE RECEIVING OFFICE

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
122 Ep: pct application non-entry in european phase