WO1993007629A1 - Integrated deposited vertical resistor in a sequential multilayer substrate - Google Patents

Integrated deposited vertical resistor in a sequential multilayer substrate Download PDF

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Publication number
WO1993007629A1
WO1993007629A1 PCT/US1992/006764 US9206764W WO9307629A1 WO 1993007629 A1 WO1993007629 A1 WO 1993007629A1 US 9206764 W US9206764 W US 9206764W WO 9307629 A1 WO9307629 A1 WO 9307629A1
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WO
WIPO (PCT)
Prior art keywords
resin
resin material
resistive
depositing
opening
Prior art date
Application number
PCT/US1992/006764
Other languages
French (fr)
Inventor
Vernon L. Brown
Original Assignee
Motorola, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola, Inc. filed Critical Motorola, Inc.
Publication of WO1993007629A1 publication Critical patent/WO1993007629A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20—Resistors
    • H01L28/26—Resistors with an active material comprising an organic conducting material, e.g. conducting polymers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
    • H01C17/003—Apparatus or processes specially adapted for manufacturing resistors using lithography, e.g. photolithography
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20—Resistors

Definitions

  • the present invention relates generally to the field of resistor manufacture in an integrated circuit.
  • Resistors are typically used in digital circuits to pull a node in the circuit to a certain voltage or to terminate a transmission line. In order to manufacture these resistors in an integrated circuit, they are formed in the same plane as the interconnecting traces. This requires the use of valuable interconnection area and adds undesirable series inductance to resistor due to the surface traces used to connect to the resistor.
  • a deposited vertical resistor is formed on a substrate material.
  • the resistor is comprised of a first resin, deposited on the substrate material and having an opening to the substrate material over a conductive pad.
  • a second resin is deposited in the opening and is formed into a predetermined shape.
  • a third resin is then deposited on the first and second resins, the third resin forming a predetermined pattern. Finally, a conducting material is coupled to the second resin.
  • FIGs. 1A - F show a cut-away view of the various steps in the process to construct the vertical resistor of the present invention.
  • FIGs. 2A - C show first and second side cut-away views and a top view of the vertical resistor of the present invention.
  • FIGs. 3A and B show a top and side cut-away view of a vertical resistor coupled to a planar resistor.
  • the resistor of the present invention is deposited vertically in sequential, multiple layers, thus requiring little space for the completed coplanar resistor.
  • the process of the present invention for fabricating this resistor is illustrated in FIGs. 1A - IF.
  • the process begins with a substrate material having conductive copper pads in the areas where the resistors are to be formed.
  • the substrate contains the circuit requiring the resistors.
  • the copper pads are located at the nodes to be pulled up to a certain voltage, terminated with a resistor, or otherwise requiring a resistor to be coupled to that point in the circuit. For clarity, only one copper pad will be shown to explain the resistor of the present invention.
  • a first resin (103) is deposited over the substrate (101) and copper pad (102). This resin (103) is hardened and then photo-defined to expose the copper pad (102) as shown in FIG. 1A.
  • a second resin (104) is deposited over the first resin (103) as seen in FIG. IB. This includes filling the vias through the first resin (103) that are over the copper pads
  • FIG. 1C shows the next step of photo-defining the resistive resin (104) to form the resistive element.
  • the resistive element is brought over the top of the dielectric (103) to protect it from the intrusion of resins or metals from later operations.
  • the resistive resin (104) is made resistive by doping the resin with a resistive material such as tin oxide.
  • the resistive material should be compatible with the photo-definition means of the basis resin.
  • the next step coats the above assembly with a dielectric, photo-definable resin (105).
  • This layer is hardened and then photo-defined, as shown in FIG. IE, to provide the openings for the upper circuit pattern linking the upper terminal of the resistor to the proper locations in the lower circuit.
  • the resin layers (103, 104, and 105) are then partially or fully cured. These layers (103, 104, and 105) may also be cured separately after each photo- definition step.
  • the final step illustrated in FIG. IF, entails depositing copper (106) or other conductive material in the openings formed in the previous step. These copper terminals (106) form the upper terminals of the resistor.
  • the copper (106) can be deposited by a number of methods.
  • the preferred embodiment of the above process of the present invention fills the first two resin layers (103 and 104) with a material that is catalytic or can be made catalytic to electroless copper.
  • FIG. 2C shows a top view and FIGs. 2A and 2B show two side cross section views of the completed integrated vertical resistor.
  • a primary advantage of the vertical resistor is that because of its use of the region between two planar circuits very little space is occupied on either of the planar layers thus increasing circuit interconnectivity.
  • Another advantage is that the effective series inductance is very low because of the complete elimination of printed wire terminations.
  • Yet another advantage of the vertical resistor of the present invention is that fairly high resistive material can be used to obtain the low values needed for transmission line tera ⁇ nation. Higher values of resistance can be attained by patterning on the surface of resin (103) using the same photo- definable, resistive resin (104) to provide a combination of vertical and planar resistors.
  • the vertical resistors can be formed together with planar resistors at the same time.
  • planar resistors can be deposited and photo-defined on the first resin (103) in the same step as the defining of the vertical resistors.
  • a planar resistor can be either separate from the vertical resistors or coupled to one or more vertical resistors to form a resistor network.
  • An example of a planar resistor coupled to a vertical resistor is illustrated in FIGs. 3A and 3B.
  • the integrated, deposited resistor of the present invention provides low resistance in a small, vertical area. Because the resistor is short, with a wide cross section, relatively high resistivity material can be used to obtain a low resistance value.

Abstract

A deposited vertical resistor is formed on a substrate material (101) containing a circuit. The resistor is comprised of a first resin (103) deposited on the substrate material (101) and having a photo-defined opening to a copper pad (102) that is coupled to a particular node in the circuit. A resistive resin (104) is deposited in the photo-defined opening and is formed into a predetermined shape around the opening. A third resin (105) is then deposited on the first and the resistive resin (104), the third resin (105) forming a circuit pattern. Finally, a copper material (106) is coupled to the resistive resin (104), thereby forming a terminal pad over the resistive resin (104) and the lower copper pad (102).

Description

INTEG ATED DEPOSITED VERTICAL RESISTOR IN A SEQUENTIAL MULTILAYER SUBSTRATE
F_j_Moft-_e___ventiαn
The present invention relates generally to the field of resistor manufacture in an integrated circuit.
Background of the Invention
Resistors are typically used in digital circuits to pull a node in the circuit to a certain voltage or to terminate a transmission line. In order to manufacture these resistors in an integrated circuit, they are formed in the same plane as the interconnecting traces. This requires the use of valuable interconnection area and adds undesirable series inductance to resistor due to the surface traces used to connect to the resistor.
It is difficult, however, to obtain low value resistances in planar resistors due to the simultaneous need to have a thick enough film for reliability that leads to the need for high resistivity coupled with the need for a short, wide form factor. Discrete resistors are typically used in this case, requiring considerable space when very dense interconnects using conductor widths in the range of 50 microns to 10 microns.
There is a resulting need for an integrated resistor having a low resistance value.
Summary of the Invention
A deposited vertical resistor is formed on a substrate material. The resistor is comprised of a first resin, deposited on the substrate material and having an opening to the substrate material over a conductive pad. A second resin is deposited in the opening and is formed into a predetermined shape. A third resin is then deposited on the first and second resins, the third resin forming a predetermined pattern. Finally, a conducting material is coupled to the second resin.
Brief Description of the Drawings
FIGs. 1A - F show a cut-away view of the various steps in the process to construct the vertical resistor of the present invention.
FIGs. 2A - C show first and second side cut-away views and a top view of the vertical resistor of the present invention. FIGs. 3A and B show a top and side cut-away view of a vertical resistor coupled to a planar resistor.
Det___li_dl_tesc-r-pti( c>f tfaePrefeπ^
The resistor of the present invention is deposited vertically in sequential, multiple layers, thus requiring little space for the completed coplanar resistor. The process of the present invention for fabricating this resistor is illustrated in FIGs. 1A - IF.
The process begins with a substrate material having conductive copper pads in the areas where the resistors are to be formed. The substrate contains the circuit requiring the resistors. The copper pads are located at the nodes to be pulled up to a certain voltage, terminated with a resistor, or otherwise requiring a resistor to be coupled to that point in the circuit. For clarity, only one copper pad will be shown to explain the resistor of the present invention.
A first resin (103) is deposited over the substrate (101) and copper pad (102). This resin (103) is hardened and then photo-defined to expose the copper pad (102) as shown in FIG. 1A.
Next, a second resin (104) is deposited over the first resin (103) as seen in FIG. IB. This includes filling the vias through the first resin (103) that are over the copper pads
(102). This resin (104) is filled to make it resistive. It may also be inherently resistive. The resistive resin (104) is then hardened. FIG. 1C shows the next step of photo-defining the resistive resin (104) to form the resistive element. The resistive element is brought over the top of the dielectric (103) to protect it from the intrusion of resins or metals from later operations.
The resistive resin (104) is made resistive by doping the resin with a resistive material such as tin oxide. The resistive material should be compatible with the photo-definition means of the basis resin.
The next step, illustrated in FIG. ID, coats the above assembly with a dielectric, photo-definable resin (105). This layer is hardened and then photo-defined, as shown in FIG. IE, to provide the openings for the upper circuit pattern linking the upper terminal of the resistor to the proper locations in the lower circuit. The resin layers (103, 104, and 105) are then partially or fully cured. These layers (103, 104, and 105) may also be cured separately after each photo- definition step. The final step, illustrated in FIG. IF, entails depositing copper (106) or other conductive material in the openings formed in the previous step. These copper terminals (106) form the upper terminals of the resistor. The copper (106) can be deposited by a number of methods. These can include full electroless plating, as is done in conventional catalytic means using non-permanent photo-resist and practiced in the printed circuit industry. Another deposition method is by electroless followed by electroplating, followed by etching with non-permanent photo-resist as is used in the printed circuit or integrated circuit industry. The preferred embodiment of the above process of the present invention fills the first two resin layers (103 and 104) with a material that is catalytic or can be made catalytic to electroless copper.
FIG. 2C shows a top view and FIGs. 2A and 2B show two side cross section views of the completed integrated vertical resistor. A primary advantage of the vertical resistor is that because of its use of the region between two planar circuits very little space is occupied on either of the planar layers thus increasing circuit interconnectivity. Another advantage is that the effective series inductance is very low because of the complete elimination of printed wire terminations.
Yet another advantage of the vertical resistor of the present invention is that fairly high resistive material can be used to obtain the low values needed for transmission line teraα nation. Higher values of resistance can be attained by patterning on the surface of resin (103) using the same photo- definable, resistive resin (104) to provide a combination of vertical and planar resistors.
In an alternate embodiment, the vertical resistors can be formed together with planar resistors at the same time.
The planar resistors can be deposited and photo-defined on the first resin (103) in the same step as the defining of the vertical resistors. A planar resistor can be either separate from the vertical resistors or coupled to one or more vertical resistors to form a resistor network. An example of a planar resistor coupled to a vertical resistor is illustrated in FIGs. 3A and 3B.
In summary, the integrated, deposited resistor of the present invention provides low resistance in a small, vertical area. Because the resistor is short, with a wide cross section, relatively high resistivity material can be used to obtain a low resistance value.

Claims

Claims
1. A method for depositing a vertical resistor on a substrate material having a conductive pad, the method comprising the steps of: depositing a first resin material on the substrate material; forming an opening in the first resin to expose the conductive pad; depositing a second resin material on the first resin material and in the opening, thereby coupling the second resin material to the conductive pad; forming the second resin material into a predeteπnined shape; depositing a third resin material on the first and second resin materials; defining a predetermined pattern in the third resin material; and depositing conducting material on the second resin material.
2. The method of claim 1 wherein the second resin material is a resistive material and the predetermined shape is an annular ring.
3. The method of claim 1 and further including the step of curing the second resin before forming.
4. The method of claim 1 wherein the first opening and the second resin are formed by a photo-definition process.
5. A method for depositing a vertical resistor on a substrate material having a conductive pad, the method comprising the steps of: depositing a first resin material on the substrate material; hardening the first resin material; photo-defining an opening in the first resin to expose the conductive pad; depositing a resistive resin material on the first resin material and in the opening, thereby coupling the resistive resin material to the conductive pad; hardening the second resin material; photo-defining the second resin material into a predetermined shape; depositing a third resin material on the first and resistive resin materials; hardening the third resin material; photo-defining the third resin material into a circuit pattern; and depositing conducting material on the first and resistive resin materials, thus forming a terminal pad over the resistive resin material.
6. A deposited vertical resistor formed on a substrate material having a conductive pad, comprising: a first resin, coupled to the substrate material and having a photo-defined opening to the conductive pad; a hardened, resistive resin deposited in the photo- defined opening and forming a seal around the opening; a hardened, third resin coupled to the first and the resistive resin and forming a circuit pattern; and a conductive, terminal pad coupled to the first and the resistive resins.
7. A method for combining vertical and planar resistors on a substrate having at least one conductive pad, the method comprising the steps of: defining a resin material on the substrate such that an opening forms around each conductive pad that is to be coupled to a vertical resistor; defining a resistive material in the openings to form the vertical resistors and on the resin material to form the planar resistors; and coupling a conductive material to the resistors to form terminal pads for the resistors.
8. The method of claim 7 wherein the step of defining the resistive material forms the vertical and planar resistors into a resistor network.
PCT/US1992/006764 1991-10-04 1992-08-13 Integrated deposited vertical resistor in a sequential multilayer substrate WO1993007629A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US77082891A 1991-10-04 1991-10-04
US770,828 1991-10-04

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014134384A2 (en) * 2013-02-28 2014-09-04 Texas Instruments Incorporated Integrated circuit with same level different resistors
GB2586518A (en) * 2019-08-21 2021-02-24 Pragmatic Printing Ltd Resistor Geometry

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3775120A (en) * 1971-04-02 1973-11-27 Motorola Inc Vertical resistor
US4578344A (en) * 1984-12-20 1986-03-25 General Electric Company Photolithographic method using a two-layer photoresist and photobleachable film
US4690728A (en) * 1986-10-23 1987-09-01 Intel Corporation Pattern delineation of vertical load resistor
US4695853A (en) * 1986-12-12 1987-09-22 Hewlett-Packard Company Thin film vertical resistor devices for a thermal ink jet printhead and methods of manufacture
US4816115A (en) * 1987-04-16 1989-03-28 International Business Machines Corp. Process of making via holes in a double-layer insulation
US4828967A (en) * 1984-12-26 1989-05-09 Semiconductor Energy Laboratory Co., Ltd. Electronic device and its manufacturing method
US5030549A (en) * 1988-06-29 1991-07-09 Matsushita Electric Industrial Co., Ltd. Fine pattern forming method

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3775120A (en) * 1971-04-02 1973-11-27 Motorola Inc Vertical resistor
US4578344A (en) * 1984-12-20 1986-03-25 General Electric Company Photolithographic method using a two-layer photoresist and photobleachable film
US4828967A (en) * 1984-12-26 1989-05-09 Semiconductor Energy Laboratory Co., Ltd. Electronic device and its manufacturing method
US4690728A (en) * 1986-10-23 1987-09-01 Intel Corporation Pattern delineation of vertical load resistor
US4695853A (en) * 1986-12-12 1987-09-22 Hewlett-Packard Company Thin film vertical resistor devices for a thermal ink jet printhead and methods of manufacture
US4816115A (en) * 1987-04-16 1989-03-28 International Business Machines Corp. Process of making via holes in a double-layer insulation
US5030549A (en) * 1988-06-29 1991-07-09 Matsushita Electric Industrial Co., Ltd. Fine pattern forming method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014134384A2 (en) * 2013-02-28 2014-09-04 Texas Instruments Incorporated Integrated circuit with same level different resistors
WO2014134384A3 (en) * 2013-02-28 2014-10-23 Texas Instruments Incorporated Integrated circuit with same level different resistors
GB2586518A (en) * 2019-08-21 2021-02-24 Pragmatic Printing Ltd Resistor Geometry
GB2586518B (en) * 2019-08-21 2022-04-20 Pragmatic Printing Ltd Resistor Geometry

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Publication number Publication date
CN1071278A (en) 1993-04-21
MX9205662A (en) 1993-04-01

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