WO1992016929A1

WO1992016929A1 - Display image control system and method of adjusting same

Info

Publication number: WO1992016929A1
Application number: PCT/US1992/001725
Authority: WO
Inventors: William K. Bohannon; Leonid Shapiro
Original assignee: Proxima Corporation
Priority date: 1991-03-12
Filing date: 1992-03-05
Publication date: 1992-10-01
Also published as: AU1573092A

Abstract

A plurality of variable biasing devices (13, 15, 17) for controlling the deselect modes of operation of each stage (22, 24, 26) of the liquid crystal display panel assembly (11) to optimize substantially the contrast between each individual deselect state and corresponding select states. The devices include an isolation device (68) to enable the contrast between the select and deselect modes to be made, independently of the intensity adjustments for the select modes of operation.

Description

DISPLAY IMAGE CONTROL SYSTEM AND METHOD OF ADJUSTING SAME Cross-Reference to Related Applications The present patent application is a continuation-in- part patent application of U.S. patent application Serial No. 07/506,621, filed April 9, 1990, entitled "STACKED DISPLAY PANEL CONSTRUCTION AND METHOD OF MAKING SAME," now U.S. patent , which is a continuation- in-part of U.S. patent application Serial No. 07/506,429 filed April 9, 1990 entitled "STACKED DISPLAY PANEL CONSTRUCTION AND METHOD OF MAKING SAME" which is a continuation-in-part of U.S. patent application Serial No. 07/472,688 filed January 30, 1990, entitled "LIQUID CRYSTAL DISPLAY PANEL SYSTEM AND METHOD OF USING SAME," which is a continuation-in-part of U.S. patent application Serial No. 07/222,144 filed July 21, 1988 entitled "GRAY SCALE SYSTEM FOR VISUAL DISPLAYS." The foregoing patent applications are incorporated herein by reference.

Technical Field

The present invention relates in general to a system for controlling the optical display, and more particularly relates to a full color stacked liquid crystal display panel assembly having improved optical features. Background Art

In the foregoing parent patent application, entitled "STACKED DISPLAY PANEL CONSTRUCTION AND METHOD OF MAKING SAME," now U.S. patent , there is disclosed a stacked liquid crystal display assembly for producing multiple color images in response to a computer, such as a personal computer. In this regard, the assembly is adapted to be driven by such a computer, and is used by placing it on a stage or platform of an overhead projector, whereby the images controlled by the computer are projected from the assembly onto a remote screen for viewing by a group of people.

The assembly includes a plurality of liquid crystal display panels which are stacked in overlying relationships with one another along an optical path. Each one of the liquid crystal display panels is arranged in a matrix array of pixel elements which are selectively energized under the control of the computer. In its select state, the pixels are energized to pass a selected color of light. In its deselect state, the pixel is deenergized to prevent the selected color of light from being passed, and instead passing a non color of light. In such a system, two or three liquid crystal display panels are employed to enable the colors of each one of the panels to be added or subtracted optically. The optical combining of the plurality of colors for a given pixel image achieves a desired color composition. In this regard, should one of the panels pass a color of a substantially brighter intensity as compared to any remaining panels, the resulting color combination may not have the desired optical color effect. Additionally, individual panels may not produce the optimum color intensity. Therefore, the control arrangement and method disclosed in the foregoing mentioned parent patent application, enables the color intensity to be substantially optimized for each stage of the display assembly. Also, the color contrast is balanced between stages to obtain the desired color compositions for each pixel.

While such methods and arrangements disclosed in the foregoing mentioned parent patent application, are designed for the select color states, once the contrast are properly determined and set according to the teachings of the foregoing patent application, the intensity levels of the individual stages of the display assembly may not be substantially optimum during the deselect states. In this regard, it is desirable to have a maximum amount of contrast between the select and deselect states of each stage of the assembly, to enable the viewer to readily perceive the difference between the ON and the OFF states of each stage of the assembly.

Therefore, to have a fully optimized color display system employing stacked liquid crystal display panels, it would be highly desirable to not only balance the intensity for the select states, but at the same time have substantially optimum contrast for each stage of the assembly. It would also be highly desirable to have an arrangement and a method for so controlling the assembly for its deselect states, in an economical manner. Disclosure of Invention

Therefore, the principal object of the present invention is to provide a new and improved method and arrangement for controlling the contrast for stacked liquid crystal display panel assemblies.

Another object of the present invention is to provide such a new and improved method and arrangement, whereby the intensity is not only greatly improved for the select states of each stage of the assembly, but also substantially minimized for the deselect states as well, to provide a substantially improved contrast.

Briefly, the above and further objects of the present invention are realized by providing a plurality of variable biasing devices for controlling the deselect modes of operation of each stage of the liquid crystal display panel assembly to optimize substantially the contrast between each individual deselect state and corresponding select states. The devices include an isolation device to enable the contrast between the select and deselect modes to be made, independently cf the contrast adjustments for the select modes of operation.

Brief Description of Drawings

The above mentioned and other objects and features of this invention and the manner of attaining them will become apparent, and the invention itself will be best understood by reference to the following description of the embodiment of the invention in conjunction with the accompanying drawings, wherein: FIG. 1 is a diagrammatic block diagram of a display system which is constructed in accordance with the present invention;

FIG. 2 is a diagrammatic representation of a column waveform for one of the display panels of FIG. l; FIG. 3 is a diagrammatic representation of a row waveform for one of the display panels of FIG. l;

FIG. 4 is a diagrammatic representation on a greatly enlarged time scale, of a combined waveform for one of the display panels produced from the waveforms of FIGS. 2 and 3; and

FIG. 5 is a greatly enlarged cut away diagrammatic view of the display panel assembly of FIG. l, illustrating the liquid crystal pixel elements in the panel assembly. Best Mode for Carrying Out the Invention

Referring now to the drawings, and more particularly to FIG. 1, there is shown a liquid crystal display system 10. The liquid crystal display system 10 generally comprises a stacked liquid crystal display assembly 11 coupled to a bias network 12 for displaying visual images. The bias network 12 includes a set of deselect bias control circuits 13, 15 and 17 for controlling the deselect bias voltages of the stacked liquid crystal display assembly 11 and a set of gamma curve bias control networks 19, 21 and 23 for controlling the select bias voltages to optimize substantially the transmissivity of the assembly 11. The individual gamma curve correction network 19, 21 and 23 are arranged in a different embodiment than the gamma curve networks more fully described in copending U.S. patent application Serial No. 07/506,621. The gamma curve networks 19, 21 and 23 helps facilitate the transmissivity of the assembly 11 when individual pixel elements are energized to their selected or ON states of operation by adjusting the reference level voltage V₅ for each respective panel 31, 35 and 39. The bias network 12 cooperates with the gamma curve network to further facilitate the transmissivity of the assembly 11 by controlling the bias voltages of the individual panels 31, 35 and 39 when the individual pixel elements are in their deselected state of operation to achieve a maximum amount of contrast between the select and deselect states of each stage of the assembly, as will be described hereinafter in greater detail.

The stacked liquid crystal display assembly 11 includes a group of liquid crystal display units 22, 24 and 26 that are aligned optically with a set of polarizers 28, 33, 37 and 42 for producing a full color image when light from a light source 43 passes through the assembly 11. The display units 22, 24 and 26 include liquid crystal display panels 31, 35 and 39 respectively that are coupled to a set of video drive modules (not shown) .

As best seen in FIG. 5, the display assembly 11 (with the polarizers 28, 33, 37 and 42 not shown for clarify of illustration) is comprised of a plurality of liquid crystal pixel elements, such as pixel elements 31A, 31B, 35A, 35B and 39A (FIG. 5) . The pixel elements, such as 31A, 3IB and 31A, 35A are arranged in columns and rows, such as column C and row R (FIG. 5) , within the structure of the individual panels. Every pixel element, such as pixel element 31A is capable of being in one of two states, either in a select or ON state which allows the maximum amount of transmissivity of a selected color in the visible light spectrum to be passed by the pixel element 31A, or in a deselect or OFF state which enables the pixel element 31A to pass substantially all colors in the visible light spectrum. Every pixel element in each display panel has a corresponding pixel in an adjacent panel such that the pixel elements, such as the pixel element 3IB and the pixel element 35B, are aligned from panel to panel. As the display assembly 11 is more fully described in copending U.S. patent application Serial No. 07/506,429 referenced above it will not be described hereinafter. In operation the deselect bias control circuits 13, 15 and 17 cooperate with the gamma curve bias control networks 19, 21 and 23 to optimize substantially the contrast differences between the select and deselect states of the individual pixel elements in the display assembly 11. In this regard contrast means the ratio between the ON and OFF intensity levels of the individual pixel elements in any given display panel, such as panel 39.

Considering now the bias control circuits 13, 15 and 17 in greater detail with reference to FIG. 1, only one control circuit, control circuit 13, will be described in greater detail as each of the control circuits 13, 15 and 17 are substantially similar to one another.

As best seen in FIGS. 1-4, control circuit 13 produces a set of bias voltages V₁ V_, V₃, V₄, and V₅, for helping to control the select and deselect states of panel 39. In this regard, the select and deselect states of panel 39 are defined by the following equations: Select state in positive frame phases = V_Q - V₅ Select state in negative frame phases = V₅ - V_c Deselect state in positive frame phases - V- - V₅ Deselect state in negative frame phases - V₃ - V₀ In order to adjust the select voltage V_s of panel 39, the control circuit 13 includes a pair of series connected resistors 44 and 57 that are connected in parallel with a bias network 40. The gamma curve network 19 includes a transistor 68 for isolating the reference select bias voltage V₀ from the deselect bias voltage VI through V4. The transistor 68 is connected in series with a group of variable resistors 46, 48, 51, 53 and 55 for enabling the bias voltages V₁ through V₅ to be adjusted relative to the bias voltage V₀. The bias voltages V₀ through V₅ are coupled to the panel 39 to define voltages applied to the rows and columns of pixel elements (not shown) disposed in the panel 39 for producing a visual image. The voltage values of V- through V₅ determine the select and deselect states of the panel 39 between a pair of reference voltage sources V_DD and V_ss (not shown) . Resistor 44 is a variable resistor whose resistance may be adjusted for controlling the value of V₅ between a maximum and minimum voltage value. A capacitor 45 is coupled between the voltage source V_DD and ground for helping to eliminate, if not greatly reduce spurious noise transients on the bias voltage V₀. Capacitor 45 is a 10 μfarad capacitor.

Considering now the bias network 40 in greater detail with reference to FIG. 1, the resistive values of resistors 46, 48, 51, 53 and 55 are selected for optimum operation with the panel 39 and may vary in value depending upon the static bias voltage specification required by different panel manufacturers. Although the values of resistors 46, 48, 51, 53 and 55 may vary between different types of manufacturers of panels, the values of resistors 46, 48, 51, 53 and 55 are calculated theoretically and are adjusted to conform with the following equations:

v, - v₂ = v₃ - v₄

More particularly, the theoretical values of resistors 46, 48, 51, 53 and 55 are selected based upon the duty cycle of panel 39 and the following relational formulas:

Duty cycle = 1/n

where R and j^ are the theoretical R_x = R₂ values of resistors 46, 55 and 48, 53 respectively

R₃~~[(_\/S+l) -4] [J.. which reduces to

where R₂ is R₃= [-/h-3] [R_J the theoretical value of resistor 51

Using the above referenced formulas, the static values for resistors R1-R3 for a Kyocera supertwisted panel model No. KL7248STPB are given as follows: R, = 10.OK ohms R_g = 10.OK ohms R₃ = 100.OK ohms Considering now the bias voltage V,, V₂, V₃, and V₄ in greater detail with reference to FIG. 1, the bias voltages V,, V₂, V₃, and V₄ control the deselect state of panel 39 while the bias voltages V- and V₅ control the select state of panel 39. The deselect bias voltages V,, V₂, V₃ and V₄ are produced by a set of operational amplifier networks 71, 72, 73 and 74 that operate in cooperation with the resistors 46, 48, 51 and 53 respectively as will be explained hereinafter in greater detail.

Considering the bias network 40 in still greater detail with reference to FIG. 1, the reference voltage V_DD is coupled to the positive input of the operational amplifier network 71 through the variable resistor 46. The variable resistor 46 is also connected in series with variable resistor 48 through a common node 59. The opposite terminal of variable resistor 48 is connected to a node 62 coupled to the variable resistor 51 and the positive input of operational amplifier network 72. The opposite terminal of variable resistor 53 is connected by a common node 64 to one terminal of variable resistor 55 and the positive input of operational amplifier network 73. The opposite terminal of variable resistor 55 is connected by a common node 67 to the emitter of transistor 68 and a fixed resistor 75. The collector of transistor 68 is connected to voltage V_ss. For the purpose of isolating the bias voltage V₀, from the bias voltage V, through V₅, the base of transistor 68 is connected to the variable resistor 44. The series connected variable resistors 46, 48, 51, 53 and 55 are connected in parallel with the current limiting resistor 57 for helping to bias the transistor 68.

Considering now the amplifier networks 71, 72, 73 and 74 with reference to FIG. 1, the amplifier networks 71-74 are substantially identical to one another so only amplifier network 71 will be described in greater detail. Referring now to FIG. 1, the amplifier network 71, generally comprises an operational amplifier 80 and a current limiting resistor 81. The positive input of amplifier 80 is connected to node 59, while the output of amplifier 80 is connected to a common node 82 coupled between one terminal of resistor 81 and the negative input of amplifier 80. The other terminal of the current limiting resistor 81 is connected between a filter capacitor 83 and the display panel 39. Capacitor 83 helps to reduce if not substantially eliminate spurious signal noise on voltage V,. The capacitor 83 is a ten microfarad capacitor.

Considering now the waveform of voltages V₀ through V₅ in greater detail with reference to FIGS. 2-4, a combined waveform 90 (FIG. 4) is applied to panel 39 for causing the individual pixel elements disposed within the panel 39 to be switched between their selected state and their deselect state. In this regard, the combined waveform 90 (FIG. 4) is formed by combining a column waveform 92 (FIG. 2) and a row waveform 94 (FIG. 3). For the purpose of charge balancing the panel 39, the individual frame time intervals of the panel 39 are alternated between a series of positive frame time intervals shown generally at 91, 93, 95 and 97 and a series of negative frame time intervals shown generally at 101, 103, 105 and 107.

As best seen in FIG. 2, the column waveform 92 varies between the voltages V₂ and V₃ in the deselect state and the voltages V₀ and V₅ in the select state. In a similar manner, as best seen in FIG. 3, the row waveform 94 varies between the voltages V., and V₄ in the deselect state and the voltages V- and V₅ in the select state. From the foregoing it should be understood that the voltage V₀ controls the select state for the positive frame cycles 91 and 93 in the column waveform 92 and the negative frame cycles 105 and 107 in the row waveform 94. In a like manner, the voltage V₅ controls the select state for the negative frame cycles 101 and 103 in the column waveform 92 and the positive frame cycles 95 and 97 in the row waveform 94. The following tables will further illustrate the operation of the column waveform 92 and the row waveform 94.

Referring now to Table 1, during the positive or high phases 91 and 93 of the column waveform 92, the waveform voltage will be at V₂ volt whenever a pixel element in a given column is in a deselected state (data low) and at V₀ volts whenever a pixel element in a given column is in a select state (data high) . Similarly, during the negative or low frame phases 101 and 103 of the column waveform, the column waveform voltage 92 will be at V₃ volts whenever a pixel element in a given column is in a deselect state (data low) and at V₅ volts whenever a pixel element in a given column is in a select state (data high) .

Referring now to Table II, during the positive or high frame phases 95 and 97, of the row waveform 94, the waveform voltage 94 will be at the V5 voltages whenever a pixel element in a given row is in a select or high state and at V_t volts whenever a pixel element in a given row is in a deselect or low state. Similarly, during the negative or low phases 105 and 107 of the row waveform 94, the row waveform voltage will be at V_A whenever a pixel element in a given row is in a deselect or low state and at V₀ volts whenever a pixel element in a given row is in a select or high state.

Considering now the combined waveform 90 in still greater detail with reference to FIG. 4, during the positive frame phases 91 and 95, the combined waveform 90 varies between a nonselect voltage of V_NS equal to V₀ minus V₁ when the data state is high and V₂ minus V₄ when the data state is low, where V₀ minus V₁ equals V₂ minus V₄. Similarly, the combined waveform 94 also varies between a select voltage of V_s equal to V₀ minus V₅ when the data state is high and V₂ minus V₅ when the data state is low, where V₂ minus V₁ equals V₅ minus V₄.

From the foregoing it should be understood that during the positive phases 91, 95 and 93, 97 the select voltage V_s equal to V₀ minus V₅ will occur whenever a pixel element is to be energized to an ON state so that the column and row are simultaneously selected and a deselect voltage V_NS equal to V₂ minus V₅ will occur whenever the pixel element is to be deenergized to an OFF state so that the row is selected but the column is not. In a like manner, during the negative phases 101, 105 and 103, 107 a select voltage V_s, equal to V₅ minus V₀ will occur whenever a pixel element is to be energized to an ON state so that the column and row are simultaneously selected and a non select voltage V_NS, equal to V₃ minus V_ will occur whenever the pixel element is to be deenergized to an OFF state so that the row is selected but the column is not. In summary then, to substantially optimize the transmissivity of the panel 39 during the positive frame time intervals 91, 95 and 93, 97 the voltage differences between the select and deselect states, V_s and V_NS should be substantially maximized. Similarly, to substantially optimize the transmissivity of the panel 39 during the negative frame time intervals 101, 105 and 103, 107 the voltage differences between the select and deselect states, V_s, and V_NS, should also be substantially maximized.

A typical setting of actual voltages for V₀ through V₅ for one given type of panel manufactured by Kyocera Corporation is shown in Table III if resistors Rl and R2 are set to 6.65 K ohms and reistor R3 is set to 73.2K ohms.

Considering now the procedure for substantially optimizing the contrast level of the individual panels 31, 35 and 39, the adjustment procedure for only panel 39 will be described as the procedure is substantially identical for each of the panels.

As the reference voltages V_DD and V__s are fixed reference levels of +5 volts and -23 volts respectively the gamma curve adjustment for the select state of the panel 39 is established first. In this regard, the user adjusts resistor 44 to fix the voltage value of V₅ to provide the maximum transmissivity level for the panel 39. The user then measures and records the voltage value V₅.

The user then causes the panel 39 to be deenergized to an ON or deselected state and then adjusts variable resistor 48 for setting the voltage value of V₂ to give the darkest possible background. The setting of the voltage value V₂ is achieved by the user visually inspecting the image produced by the entire panel assembly 11.

The user then adjusts the voltage value of V₃ to give a uniform dark image over the entire background and to give a darker background image than was previously observed by adjustment of the voltage value of V₂. In this regard, the user adjusts the setting value of variable resistor 53 to achieve the desired results.

As the above mentioned adjustment steps effects the voltage value of V₅, the user must then readjust the V₅ voltage value. In this regard, the user again causes the panel to be energized to its select or ON state and then adjusts the setting of variable resistor 51 to readjust V₅ to the value previously measured and recorded.

It should be noted in Table III that the voltages values of V_{0 throogh v}5 are set in descending values referenced between the two reference voltages V_DD (+5 volts) and V_ss (-23 volts) .

While particular embodiments of the present invention have been disclosed, it is to be understood that various different modifications are possible and are contemplated within the true spirit and scope of the appended claims. There is no intention, therefore, of limitations to the exact abstract or disclosure herein presented.

Claims

ClaimsWhat is claimed is:

1. A display system characterized by: a display assembly including a plurality of liquid crystal display panels, each one of said display panels having a plurality of electrically operable pixel elements for displaying color images; a variable-voltage select voltage level control circuit for biasing each one of said panels with a biasing voltage to optimize substantially the intensity levels of said panels; a variable-voltage deselect voltage level control circuit for biasing each one of said panels with another biasing voltage to optimize substantially the differences between select and deselect voltage levels to improve the color contrast between the select and deselect states of each one of said panels; and a variable impedance circuit for causing said select and deselect voltage level control means to be adjusted substantially independently of one another.

2. A display system according to claim 1, characterized in that said variable impedance circuit, said select voltage control circuit and said deselect voltage control circuit further include a variable impedance network, said variable impedance network including a large variable impedance device, and said select circuit and said deselect circuit each including a small variable impedance device for enabling the large variable impedance device to cause readjustment of the potential of said biasing voltage substantially independently of the potential of said other biasing voltage.

3. A method for displaying color images, characterized by: using a plurality of liquid crystal display panels, each one of said panels having a plurality of electrically operable pixel elements for displaying color images; interposing each one of said panels between a pair of polarizers that cooperate with said panels for passing a portion of the visible light spectrum to form the color images; using a direct current select voltage level control device for biasing each of said panels with a direct current select voltage; biasing each of said panels with a direct current select voltage to maximize substantially the luminance of pixel images produced by said the pixel elements when fully energized; using a direct current deselect voltage level control device for biasing each one of said panels with a direct current deselect voltage; biasing each of said panels with a direct current deselect voltage to minimize substantially the luminance of pixel images produced by said pixel elements when non-selected; energizing selectively said pixel elements independently of said direct current select voltage level control device and said deselect voltage level control device; adjusting the color contrast of each one of said panels by causing the direct current select voltage potential and the direct current deselect voltage potential for each one of said panels to be adjusted independently of one another to establish a substantial voltage difference between the direct current select voltage potentials and the direct current deselect voltage potentials to substantially optimize the color contrast of each one of said panels.

4. A display system according to claim 1, characterized in that each one of said liquid crystal display panels is a nematic liquid crystal display panel.

5. A display system according to claim 4, characterized in that said nematic liquid crystal display panel is a twisted nematic liquid crystal display panel.

6. A display system according to claim 4, characterized in that said nematic liquid crystal display panel is a highly twisted nematic liquid crystal display panel.

7. A display system according to claim 4, characterized in that said nematic liquid crystal display panel is a supertwisted nematic liquid crystal display panel.

8. A display system according to claim 1, characterized in that said plurality of liquid crystal display panels includes three monochromatic liquid crystal display panels.

9. A display system according to claim 8, characterized in that one of said monochromatic liquid crystal display panels in cooperation with its associated polarizers passes all colors of light and a selected colored light, said selected colored light being substantially in the yellow color spectrum of visible light.

10. A display system according to claim 9, characterized in that another one of said monochromatic liquid crystal display panels in cooperation with its associated polarizers passes all colors of light and another selected colored light, said other selected colored light being substantially in the magenta color spectrum of visible light.

11. A display system according to claim 10, characterized in that still another one of said monochromatic liquid crystal display panels in cooperation with its associated polarizers passes all colors of light and still yet another selected colored light, said still yet another selected colored light being substantially in the cyan color spectrum of visible light.

12. A display system according to claim 8, characterized in that one of said monochromatic liquid crystal display panels in cooperation with its associated polarizers passes all colors of light and a selected colored light, said colors light being substantially in the red color spectrum of visible light.

13. A display system according to claim 12, characterized in that another one of said monochromatic liquid crystal display panels in cooperation with its associated polarizers passes all colors of light and another selected colored light, said other selected colored light being substantially in the green color spectrum of visible light.

14. A display system according to claim 13, characterized in that still yet another one of said monochromatic liquid crystal display panels passes all colors of light and still yet another colored light, said still yet another colored light being substantially in the blue color spectrum of visible light.

15. A display system according to claim 1, characterized in that said liquid crystal panel is an active matrix liquid crystal display panel.

16. A display system according to claim 1, characterized in that said plurality of liquid crystal display panels includes a set of active matrix liquid crystal display panels.

17. A display system according to claim 1, characterized in that said variable-voltage select voltage level control circuit is manually adjustable between a maximum setting for causing the panels to exhibit a substantially maximum amount of relative luminance when energized and a minimum setting for causing the panels to exhibit a substantially minimum amount of relative luminance when said de-energized.

18. A display system according to claim 17, characterized in that each one of said liquid crystal display panels have two controllable modes of operation, at least one of said modes being a non-white mode in response to a video on/off signal.

19. A display system characterized by: a plurality of liquid crystal display panels, each one of said display panels having a plurality of electrically operable pixel elements for displaying color images; each liquid crystal panel being interposed between a pair of polarizers that cooperate with the panel for passing a portion of the visible light spectrum to form said color image; each one of said panels exhibiting substantially different relative luminance levels as a function of an applied direct current select voltage potential; direct current select voltage level control devices for biasing each one of said panels with a direct current select voltage potential to maximum substantially the luminance of said pixels when fully energized; said electrically operable pixel elements being electrically energized independently of said direct current select voltage level control devices; and direct current deselect voltage level control devices for biasing each one of said panels with a direct current deselect voltage potential to maximize the differences between select and deselect voltage potentials to substantially optimize the color contrast between the select and deselect states of each one of said panels.