WO1992013385A1

WO1992013385A1 - High frequency, high density power conversion system

Info

Publication number: WO1992013385A1
Application number: PCT/US1992/000700
Authority: WO
Inventors: Dawari Datubo Dan-Harry
Original assignee: Dan Harry Dawari Datubo
Priority date: 1991-01-29
Filing date: 1992-01-27
Publication date: 1992-08-06
Also published as: IE920290A1; AU1364692A

Abstract

A high-frequency, high-density power conversion system providing lossless power switching with a single or double-ended power converter, the single ended converter including a pair of input terminals (+Vin, -Vin) for receiving dc or rectified ac voltage, a transformer (T1) with its primary across the input terminals, a transistor (Q2) in series between an input terminal (-Vin) and the transformer primary, an inductor (L1) in series between the other input terminal (+Vin) and the other side of the primary, in which the transistor (Q2) is switched to provide a sinusoidal output current pulse to the transformer primary. The parasitic capacitance (Coss) of the transistor (Q2) forms a resonant tank with the inductor (L1), thereby allowing switching in the mega Hz range of frequency without switching losses.

Description

HIGH FREQUENCY, HIGH DENSITY POWER CONVERSION SYSTEM

*************

RELATED APPLICATION

This application is continuation in part of Serial No. 647,065, filed on January 29, 1991.

FIELD OF THE INVENTION

The present invention relates to AC/DC and DC/DC converters and it is directed towards eliminating or minimizing switching losses that occur in a controlled switch of a power converter while increasing the switching frequency to the 1 - 10 mega- Hertz range.

BACKGROUND OF THE INVENTION

Switching power conversion systems have relied on manual switches or electro-mechanical switches in order to configure an input voltage to either a full wave or voltage doubler configuration and where an opto-triac has been used it has not been properly synchronized with the control circuit for proper coordination and control of the entire system. It will be desirable to have a configuration circuit controlled by a controlled circuit. This ensures that the converter will not operate until an adequate line voltage is available. Further this method reduces component count and is cost effective.

Power conversion is generally accomplished by the switching method known as pulse width modulation (PWM). In the PWM method, voltage and current transition overlap, resulting in significant switching losses (up to 50%) in the controlled switching element. The operating frequency of a converter operating by the PWM method is also limited in part by the parasitic elements in the said controlled switching element. Resonance switching methods have been proposed to decrease switching losses by allowing current/voltage transition in the controlled switch to occur as much as possible at zero current or zero voltage. However, the resonance switching require both a resonance inductor (L_r) and a resonance capacitor (C_r) , which allows the energy stored in the parasitic capacitance of the switch to go to waste instead of being utilized for energy conversion.

Presently available power control integrated circuits are not able to modulate and vary frequencies in the mega Hz range, cannot be plugged/unplugged while hot, and are not common to all power conversion systems within a given series without regard to input and output voltage or power output capability. Further, for precise performance of essential housekeeping functions, it is necessary that most housekeeping functions be implemented on a single integrated substrate, unlike the present mixture of discrete and integrated components. Using an integrated substrate will result in uniform manufacturing repeatability and will be cost effective.

SUMMARY OF THE INVENTION

It is the primary object of the present invention to overcome the above problems of the prior art.

A controlled high-speed, high-efficiency electronic switch (transistor), for example a MOSFET switch driven at a very high frequency has a significantly large amount of energy stored in the junction capacitance during each switching cycle. This energy can be properly utilized for conversion and the capacitance can be used as the resonant frequency (F_r) switching component. This will increase switching frequency and improve converter efficiency and power density.

In order to accomplish the above objectives two power MOSFET switches each having an effective junction capacitance (C_QSS) are connected to each order in source-drain configuration with the source-drain node connected in series to an inductor (L_r) and a transformer (T) . The inductor (L_r) forms a series resonance tank with the junction capacitance C_QSS that is parallel loaded.

This arrangement is equivalent to placing the resonant capacitor (C_r) in parallel to the controlled switch which allows the controlled switch voltage to rise slowly at turn-off of switch, and ring back sinusoidally, so that the controlled switch current will rise and fall to zero before the rise of switch voltage to eliminate switching losses.

The second object of the present invention is to provide an integrated control module (USPCM) to handle the following housekeeping functions:

1. Input voltage configuration to either a full-wave or a voltag doubler configuration for any two predetermined ranges of voltage.

2. Provide level shifting and V__s drive current capable of up to two amps.

3. Sensing of DC line input voltage to determine if the voltage level is adequate for a given converter.

4. DC line high input voltage startup regulation.

5. Supply power to the low voltage regulator through the transformer's auxiliary winding for continuous internal power supply to USPCM.

6. Isolated feedback network.

7. Very high frequency modulation.

8. Remote shutdown

9. Soft start operation.

10. Capable of being plugged into or removed from power converter board hot.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig 1 is a block diagram of the preferred embodiment of the power conversion system of this invention;

Fig 2 is a schematic diagram of a preferred embodiment of the input stage of the system of fig 1;

Fig 3 is a schematic diagram of a preferred embodiment of the conversion and output stage of system of fig 1;

Fig 4 is a schematic diagram the diagram of a portion of the conversion stage of fig 3 also illustrating the equivalent circuit;

Fig 5A is a more detailed schematic diagram of the conversion stage of fig 3;

Fig 5B is a timing diagram illustrating the operation of the conversion stage of fig 5A;

Fig 6A is a schematic diagram of an alternative single-ended conversion stage of this invention;

Fig 6B is a timing diagram illustrating the operation of the conversion stage of fig 6A; and

Fig 7 is a schematic block diagram of a functional circuit illustrating the preferred embodiment of the USPCM of the power conversion system of this invention;

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Embodiments of the present invention will be described with reference to the drawings.

The power converter system 10 of this invention is divided into a number portions: input stage 12, conversion stage 14, and output stage 16, and USPCM 20 for easy description and clarity in understanding its operation. Fig 1 is a block diagram showing the entire converter and its inter-connection. Transformer 18 couples power from the conversion stage to the output stage. Input stage 12 can accept an AC or DC input.

Referring to fig 2 there is shown in more detail the input stage 12 of the power conversion system including a pair of input terminals 1 and 2 for connecting the converter to a source of AC/DC power. The input terminals 1 and 2 are connected to a bridge rectifier BR01 having its negative pin connected to a common ground connection and the positive pin connected to the following: positive pin of the charge holding capacitor C03 that is series connected to the charge holding capacitor C04 at node N3, resistor R03 which is in series to a parallel connection of resistor R04 and to a bypass capacitor C01 at node Nl and resistor R05 which is in series to a parallel connection of resistor R04 and bypass capacitor C02 at node N2. Terminal 2 is also connected to pin 4 of the optocoupler triac OPTO01 via resistor R02. Pin 6 of OPTO01 is also connected to node 3 in open or short circuit configuration. Pin 1 of OPTO01 is connected to the positive pin of bridge rectifier BR01 and its pin 2 is connected to the emitter of QOl via a current limiting resistor ROl. The collector of QOl is connected to ground. The base of QOl, the nodes 1, and 2 and the positive pin of bridge rectifier BR01 are connected to pins 7, 6 , 5, and 16 of USPCM respectively. Terminals 3, 4 and 5 are for onward connection to the conversion and output stage. Referring to fig 7 the USPCM 20, Pin 16 is connected to node 4, the DC high voltage line. Looking into pin 16 of USPCM an integral high voltage (450 volts rated) MOSFET Ql that operates in depletion mode is connected to an amplifier circuit 5A referenced at 10 volts in order to implement a linear regulator with an output voltage of 12 volts . This is a startup regulator that provides the initial power to the USPCM. Q2 is a second regulator of the type described above but of low voltage depletion mode MOSFET. 6A is an amplifier circuit referenced at 12 volts but supplied voltage through pin 15 by the low voltage auxiliary winding (not shown in any diagram) of transformer T01 of fig 3. Because the outputs of both regulators feed into one another, the low input regulator, when operational, will shut down the startup voltage regulator.

With power present in the USPCM it senses the voltage level present at terminal 3 through node 1 and if the voltage level is below the magnitude of a pre-set level the source/sink current comparator circuit 4A that is normally sourcing current will sink current thereby biasing the base of QOl negative, and QOl will forward bias the diode of OPTO01 through the current limiting resistor ROl. This will bias the normally high impedance triac of OPTO01 to a low impedance thereby completing a connection between terminal 2 via the low resistive element R02 and node 3, hence a voltage doubler configuration. If terminal 3 is within a preset voltage level, circuit 4A will continue to source current and the above described action will not take place and the input voltage configuration will then be a full-wave configuration.

Circuits 2A and 3A are comparators with normally low outputs. The said comparators compare the voltage level of said DC line at terminal 3 by sensing the voltage present at node 2 to their respective references (2.2v & 3.2v) to determine if it is within a predetermined range. If the said DC line is below range, circuit 2A output goes high causing the normally high inverters U5 and U6 to go low shutting down circuit 8A the voltage controlled oscillator circuit and the nand gates U23 and U24 that drive the gates of the MOSFET P-junction and N-junction totem-pole QA1 and QA2 configuration and QB1 and QB2 configuration respectively.

Referring to figs 3, 4, 5 and, 6 to increase the frequency of the power conversion system to the mega Hertz range and also improve power conversion efficiency, the controlled switch voltage transition must not overlap the current transition. Hence the controlled switch current must rise slowly from zero in time for the turn-on transition, and ring back sinusoidally to zero in time for turn-off transition. To achieve this precise turn-on and turn-off the control circuit driving the controlled switch must terminate the gate drive pulse at a precise time. Further, in order to achieve resonance in the mega Hertz frequency without compromising efficiency, the inherent junction capacitance (C_oss) of a MOSFET switch offers a suitable and adequate solution.

The energy stored in the inherent capacitance C_QSS is given bythe formula:

Energy = oss^{v2 2_1/2}

This represents energy that is lost in known systems employing a discrete capacitor in parallel with the switch.

The resonant frequency of the conversion stage omega is given by the formula:

Omega = (L C)^~1/2

<^Lr ^coss^)"1/2 F_r resonant frequency is:

F_r ^1/2 - ( 2 r¹ ( C_{OS S} L_r ) -^{1 2}

^Fr = ( 4 ² C_ossL_r) ^{~ 1}

^ptank ⁼ <^coss^{v F}max> ^2~

^Coεε ^{= 2p}tank < ^{v F}max>^~ where F_maχ is the switching frequency, and Ptank ^{is total} power present in the resonant tank.

The USPCM 20 fig 7 drives the base of MOSFET devices QOl and Q02, Fig 3 through pin 8 and pin 9 respectively. The totem pole configuration of the USPCM drive circuits comprising of P- channel and N-channel MOSFET QA1 and QA2 of output pinβ and QB1 and QB2 are capable of sourcing short current pulses of more than two amps. Feedback control is through pins 1, 2, 3 and 4. Circuit 1A provides error amplification and isolation is provided by USPCM optocoupler Q3. Q3 collector decreases or increases linearly the voltage supply of circuit 8A thereby causing the period of its oscillation to vary accordingly.

EXPLANATION OF TIME CHARTS FOR DOUBLE ENDED CONFIGURATION

(FIGS 5A and 5B)

1) Assume maximum input of voltage = 200 vdc at terminal 6 (+vin)

2) Switching frequency of each switch = 450 KHz

3) Switch period (T) each switch = 2220 nanoseconds

4) ON period T_QN for each switch = 740 nanoseconds

5) OFF period _QFF for each switch = 1480 nanoseconds

6) Zero wait state period

between each gate switch transition = 370 nonaseconds

Given the above assumptions , at t = 0 _DRVA at the base of Ql is high and V^g-^ is under going transition from V_Dg^ = 200vdc to V_DS:L = Ovdc. The series combination of the dedicated resonant inductor LI and the inherent output capacitance (^c _ossι) of Ql shapes the falling V_DS1 into a sinusoidal wave by gradually discharging the energy stored in them. This action represents the discharg At the instant

flows into the transformer TI through node Nl. At the instant of the sinusoidal

--^{B ec}3^ual ^to 493.3 nanoseconds, and at the end of I^g^ transition t is equal to 740 nanoseconds. At t equal to 740 nonaseconds V_DS1 transition from zero to 200vdc commences which is the charging of the resonant tank due to series combination of C_ossl and LI.

Since there is no overlap of the current pulse with the voltage waveform, there is virtually no switching loss. At t less than or equal to 1110 nonaseconds _DRVB is equal to zero and V_DS2 = lOOvdc. At t = 1110 nonaseconds V_DRVB undergoes a transition from a low state to a high state , while _DS2 undergoes a sinusoidal transition as described for switch Ql but from a V_DS1 of lOOvdc. At t = 1603.3 nonaseconds the transition of V_DS2 from lOOvdc to zero is complete and the transition of the sinusoidal current I_Dg2 from zero to a high state commences. I_Dg flows out of the transformer TI, in opposite direction to the flow of Ipg^_' A zero wait state of t = 370 nonaseconds is inserted between the low transition of V_DRVA and the high transition of V_DRVB and vice versa.

^VDRVA ^{or V}DRVB ^^{s on} ^^{or a} P^er*i°d ^{τ =} ^40 nonaseconds, while it is off for a period T = 1480 nonaseconds. The period (T) for ^VDRVA ^{or V}DRVB ^^{s eo}-^ual ^to 2220 nonaseconds. The off period (T_0FF) for _DRVA and _DRVB varies to in order to provide regulation, but the on period (T_QN) for V_DRVA and _DRVB is constant. The variation T_QFF provides for frequency variation within a pre-set boundary.

From the transition of I_D ^ from zero to the transition of ^IDS2 f^rom zero constitutes one cycle of energy transfer, from primary side transformer TI to the secondary side. The period of this cycle T is equal to 1110 nonaseconds , Frequency F = 1/T = 1/1110 = 900 Khz. This is the resonant Frequency F_r. While the maximum switching frequency of each switch is 450 KHz , the frequency F_r at the input of the transformer TI or at node N2 is twice the switching frequency or F_r = 2 x F_max«

EXPLANATION OF SCHEMATIC DIAGRAM AND TIME CHARTS

FOR SINGLE ENDED CONFIGURATION (FIGS 6A and 6B)

In a single ended configuration, resonant frequency looking into pin P2 of transformer TI is equal to the switching frequency of Ql. The sequence of events described for Q2 in the case of double ended configuration applies applies for Ql for the single ended configuration. By using C_QSS which is parasitic capacitance, to form a resonant tank with a dedicated inductor LI, switching in the mega Hertz range of frequency without switching losses becomes possible, because at very high frequency the value of C_QSS is very significant for both energy storage and shaping V_DS into a sinusoidal wave, which ensures that the fall of V_DS will not overlap the rise of I_DS, thereby producing lossless switching. The high frequency switching allows the efficient transfer of power using an extremely small transformer, providing greater power density, also made possible by the decreased power losses. Further, this arrangement provides for the use of a smaller inductor on the transformer output. According to the description above the present invention (an integrated USPCM) permits input voltage configuration, input under/over voltage sensing, variable frequency modulation, pre- start and operating voltage regulation and high current drive. Further MOSFET junction capacitance provides resonance tank oscillation, increased resonance frequency operation, improved converter efficiency, increased power density and low component count per converter.

Although specific features of the invention are shown i some drawings and not others, this is for convenience only, as the features may be combined as is apparent to those skilled in the art.

Claims

What is claimed is:

1. A high-frequency, double-ended power converter, comprising: three input terminals for receiving voltage input; first and second transistors connected source-to-drain across the two outer input terminals, each said transistor having an inherent parasitic capacitance; a transformer for coupling power to an output, one side of the transformer primary connected to the source-drain node between said transistors; an inductor connected in series between the other side of said transformer primary and the third input terminal, said inductor and the inherent transistor capacitance forming a resonant energy storage tank for shifting the voltage input into a sinusoidal waveform; a capacitor between each outer input terminal and the third input terminal; and means for switching between said transistors to provide a sinusoidal output current pulse to the transformer primary at the transistor switching rate.

2. The high-frequency, double-ended power converter of claim 1 in which said means for switching includes means for providing a switching delay period after each transistor on period for allowing energy to fully transfer through said transformer.

3. The high-frequency , double-ended power converter of claim 1 in which said inductor has an inductance value which, together with the inherent transistor capacitance, produces an output current pulse only when the transistor voltage is zero or below to fully negate switching losses.

4. The high-frequency, double-ended power converter of claim 1 in which the input is dc.

5. The high-frequency, double-ended power converter of claim 4 further including means for rectifying ac input to dc.

6. The high-frequency, double-ended power converter of claim 4 in which the full dc input voltage is applied across the outer input terminals.

7. The high-frequency, double-ended power converter of claim 6 in which the third input terminal has an input voltage of half of the full dc input voltage.

8. The high-frequency, double-ended power converter of claim 1 in which said transistors are MOSFET devices.

9. A high-frequency power converter, comprising: a pair of input terminals for receiving voltage input; a transformer having its primary connected across said input terminals; a transistor in series between an input terminal and one side of the transformer primary, and having inherent capacitance: an inductor in series between the other input terminal and the other side of the transformer primary; and means for switching said transistor to provide a sinusoidal output current pulse to the transformer primary at the transistor switching rate.

10. The high-frequency power converter of claim 9 in which said means for switching includes means for providing a delay period between transistor on periods for allowing energy to fully transfer through said transformer.

11. The high-frequency power converter of claim 9 in which said inductor has inductance value which, together with the inherent transistor capacitance, produces an output current pulse only when the transistor voltage is zero or below to fully negate switching losses.

12. The high-frequency power converter of claim 9 in which the input voltage is dc.

13. The high-frequency power converter of claim 12 further including means for rectifying ac input to dc.

14. The high-frequency power converter of claim 9 in which said transistor is a MOSFET device.