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Publication numberWO1992008188 A1
Publication typeApplication
Application numberPCT/JP1991/001496
Publication date14 May 1992
Filing date1 Nov 1991
Priority date2 Nov 1990
Publication numberPCT/1991/1496, PCT/JP/1991/001496, PCT/JP/1991/01496, PCT/JP/91/001496, PCT/JP/91/01496, PCT/JP1991/001496, PCT/JP1991/01496, PCT/JP1991001496, PCT/JP199101496, PCT/JP91/001496, PCT/JP91/01496, PCT/JP91001496, PCT/JP9101496, WO 1992/008188 A1, WO 1992008188 A1, WO 1992008188A1, WO 9208188 A1, WO 9208188A1, WO-A1-1992008188, WO-A1-9208188, WO1992/008188A1, WO1992008188 A1, WO1992008188A1, WO9208188 A1, WO9208188A1
InventorsHidenori Nagao
ApplicantSeiko Epson Corporation
Export CitationBiBTeX, EndNote, RefMan
External Links: Patentscope, Espacenet
Semiconductor device
WO 1992008188 A1
A semiconductor device capable of easily processing data different in length, and an electronic arrangement incorporating the semiconductor device. The semiconductor device comprises input means for fetching unpacked input data, a register having a flag to be set at the processing of unpacked data, and an ALU capable of processing data, different in length. When the flag is set to the above register and the current instruction indicates the processing of short-length data, the ALU processes data having half the length of the input data and sets a carry signal for high-order bits of the data to a carry flag. For example, even when the ALU has the function to process 16- and 8-bit data, it is able to process 4-bit data when the 8-bit data processing is selected and an unpacking flag is set.
Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
JPS6222144A * Title not available
JPS6462726A * Title not available
JPS6462727A * Title not available
JPS63175927A * Title not available
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US852199422 Dec 201027 Aug 2013Intel CorporationInterleaving corresponding data elements from part of two source registers to destination register in processor operable to perform saturation
US860124627 Jun 20023 Dec 2013Intel CorporationExecution of instruction with element size control bit to interleavingly store half packed data elements of source registers in same size destination register
US863991429 Dec 201228 Jan 2014Intel CorporationPacking signed word elements from two source registers to saturated signed byte elements in destination register
US879347529 Dec 201229 Jul 2014Intel CorporationMethod and apparatus for unpacking and moving packed data
US883894629 Dec 201216 Sep 2014Intel CorporationPacking lower half bits of signed data elements in two source registers in a destination register with saturation
US901545329 Dec 201221 Apr 2015Intel CorporationPacking odd bytes from two source registers of packed data
US911668729 Dec 201225 Aug 2015Intel CorporationPacking in destination register half of each element with saturation from two source packed data registers
US914138729 Dec 201222 Sep 2015Intel CorporationProcessor executing unpack and pack instructions specifying two source packed data operands and saturation
US918298329 Dec 201210 Nov 2015Intel CorporationExecuting unpack instruction and pack instruction with saturation on packed data elements from two source operand registers
US922357229 Dec 201229 Dec 2015Intel CorporationInterleaving half of packed data elements of size specified in instruction and stored in two source registers
US936110029 Dec 20127 Jun 2016Intel CorporationPacking saturated lower 8-bit elements from two source registers of packed 16-bit elements
US938985829 Dec 201212 Jul 2016Intel CorporationOrderly storing of corresponding packed bytes from first and second source registers in result register
International ClassificationG06F7/57
Cooperative ClassificationG06F7/57, G06F2207/3816
European ClassificationG06F7/57
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