WO1992003848A3 - Stacking of integrated circuits - Google Patents

Stacking of integrated circuits Download PDF

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Publication number
WO1992003848A3
WO1992003848A3 PCT/GB1991/001459 GB9101459W WO9203848A3 WO 1992003848 A3 WO1992003848 A3 WO 1992003848A3 GB 9101459 W GB9101459 W GB 9101459W WO 9203848 A3 WO9203848 A3 WO 9203848A3
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuits
stacking
plugs
conductive material
electrically
Prior art date
Application number
PCT/GB1991/001459
Other languages
French (fr)
Other versions
WO1992003848A2 (en
Inventor
Niko Miaoulis
Original Assignee
Lsi Logic Europ
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lsi Logic Europ filed Critical Lsi Logic Europ
Publication of WO1992003848A2 publication Critical patent/WO1992003848A2/en
Publication of WO1992003848A3 publication Critical patent/WO1992003848A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
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    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
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    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
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    • H01L2924/01033—Arsenic [As]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

An integrated circuit wafer (10) is made with a through-going plug (16) of electrically conductive material which protrudes above the wafer surface so that one can stack integrated circuits spaced from each other but interconnected electrically by the plugs (16) which extend therethrough in mutual contact.
PCT/GB1991/001459 1990-08-28 1991-08-28 Stacking of integrated circuits WO1992003848A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB909018766A GB9018766D0 (en) 1990-08-28 1990-08-28 Stacking of integrated circuits
GB9018766.7 1990-08-28

Publications (2)

Publication Number Publication Date
WO1992003848A2 WO1992003848A2 (en) 1992-03-05
WO1992003848A3 true WO1992003848A3 (en) 1992-07-23

Family

ID=10681284

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB1991/001459 WO1992003848A2 (en) 1990-08-28 1991-08-28 Stacking of integrated circuits

Country Status (2)

Country Link
GB (1) GB9018766D0 (en)
WO (1) WO1992003848A2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8907499B2 (en) 1997-04-04 2014-12-09 Glenn J Leedy Three dimensional structure memory

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5354695A (en) * 1992-04-08 1994-10-11 Leedy Glenn J Membrane dielectric isolation IC fabrication
DE4314913C1 (en) * 1993-05-05 1994-08-25 Siemens Ag Method for producing a semiconductor component having a contact structure for vertical contact-making with other semiconductor components
DE4314907C1 (en) * 1993-05-05 1994-08-25 Siemens Ag Method for producing semiconductor components making electrically conducting contact with one another vertically
JPH08279562A (en) * 1994-07-20 1996-10-22 Mitsubishi Electric Corp Semiconductor device and manufacture thereof
US6498074B2 (en) 1996-10-29 2002-12-24 Tru-Si Technologies, Inc. Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners
US6882030B2 (en) 1996-10-29 2005-04-19 Tru-Si Technologies, Inc. Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate
WO1998019337A1 (en) 1996-10-29 1998-05-07 Trusi Technologies, Llc Integrated circuits and methods for their fabrication
EP1503406A3 (en) 1996-10-29 2009-07-08 Tru-Si Technologies, Inc. Back-side contact pads of a semiconductor chip
JPH10189822A (en) * 1996-12-06 1998-07-21 Texas Instr Inc <Ti> Surface-mounting substrate structure and forming method therefor
US6322903B1 (en) 1999-12-06 2001-11-27 Tru-Si Technologies, Inc. Package of integrated circuits and vertical integration
US6780770B2 (en) * 2000-12-13 2004-08-24 Medtronic, Inc. Method for stacking semiconductor die within an implanted medical device
US6717254B2 (en) 2001-02-22 2004-04-06 Tru-Si Technologies, Inc. Devices having substrates with opening passing through the substrates and conductors in the openings, and methods of manufacture
JP2002305282A (en) * 2001-04-06 2002-10-18 Shinko Electric Ind Co Ltd Semiconductor element and structure for connecting the same, and semiconductor device with stacked semiconductor elements
US6753199B2 (en) * 2001-06-29 2004-06-22 Xanoptix, Inc. Topside active optical device apparatus and method
US6848177B2 (en) 2002-03-28 2005-02-01 Intel Corporation Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme
US20080001271A1 (en) * 2006-06-30 2008-01-03 Sony Ericsson Mobile Communications Ab Flipped, stacked-chip IC packaging for high bandwidth data transfer buses

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3233195A1 (en) * 1981-09-08 1983-03-17 Mitsubishi Denki K.K., Tokyo Semiconductor device
EP0314437A1 (en) * 1987-10-28 1989-05-03 Laser Dynamics, Inc. Semiconductor wafer array
US4897708A (en) * 1986-07-17 1990-01-30 Laser Dynamics, Inc. Semiconductor wafer array

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3233195A1 (en) * 1981-09-08 1983-03-17 Mitsubishi Denki K.K., Tokyo Semiconductor device
US4897708A (en) * 1986-07-17 1990-01-30 Laser Dynamics, Inc. Semiconductor wafer array
EP0314437A1 (en) * 1987-10-28 1989-05-03 Laser Dynamics, Inc. Semiconductor wafer array

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8907499B2 (en) 1997-04-04 2014-12-09 Glenn J Leedy Three dimensional structure memory
US8928119B2 (en) 1997-04-04 2015-01-06 Glenn J. Leedy Three dimensional structure memory
US8933570B2 (en) 1997-04-04 2015-01-13 Elm Technology Corp. Three dimensional structure memory
US9401183B2 (en) 1997-04-04 2016-07-26 Glenn J. Leedy Stacked integrated memory device

Also Published As

Publication number Publication date
GB9018766D0 (en) 1990-10-10
WO1992003848A2 (en) 1992-03-05

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