WO1992002959A1

WO1992002959A1 - Solid state electromagnetic radiation detector

Info

Publication number: WO1992002959A1
Application number: PCT/US1991/004260
Authority: WO
Inventors: Nang Tri Tran; Neil W. Loeding; David V. +Di Nins
Original assignee: Minnesota Mining And Manufacturing Company
Priority date: 1990-08-08
Filing date: 1991-06-14
Publication date: 1992-02-20
Also published as: EP0543951B1; JP2979073B2; DE69129032D1; US5235195A; US5182624A; JPH05509204A; EP0543951A1; CA2087092A1; KR930701834A; DE69129032T2

Abstract

The present invention provides a large area, high pixel density solid state radiation detector (10) with a real-time and a non-destructive read-out. The solid state detector (10) comprises a plurality of field effect transistors (11) deposited onto a substrate (12) to form an array. A planarization layer (19) is deposited over the array of transistors (11). An energy sensitive layer (20) is deposited onto the planarization layer (19). Means (21) is provided for electrically connecting the energy sensitive layer (20) with each transistor (11) of the array. A top electrode layer (23) is deposited onto the energy sensitive layer (20). The solid state detector (10) also comprises circuitry means (17, 18) for providing electronic read-out from each field effect transistor (11) of the array.

Description

SOLID STATE ELECTROMAGNETIC RADIATION DETECTOR

TECHNICAL FIELD

The present invention relates to a solid state detector for detecting electromagnetic radiation, and more particularly to a large area, high pixel density solid state detector based on a two dimensional array of field effect transistors and an energy sensitive layer coating the array.

BACKGROUND ART

Solid state electromagnetic radiation detectors have been developed for consumer, commercial, scientific," medical, military and industrial applications. Consumer applications range from video to high density television. Industrial uses include robotic and machine vision; electronics imaging for advertising and communication; integrated text; and images in office work and publishing. Image sensors are also used for medical (mammography, chest x-rays), astronomy, spectroscopy, surveillance, airport luggage inspection, inspection for foreign objects in foodstuffs, non-destructive testing in industry, and many other applications.

Solid state devices used for detecting electromagnetic radiation, such as x-rays, infrared radiation, ultraviolet radiation, and visible light, store the image momentarily and then, after a selected time interval, convert the image to an electrical signal. A variety of solid state detectors are known. One type of solid state detector is the "hybrid" detector. A hybrid detector generally comprises a pyroelectric material that is bonded to a field effect transistor ("FET" ). The FET in such detectors is used as an amplification means to amplify the signal from the detector before the signal is sent to the read-out electronics. Crystalline pyroelectric materials such as strontium barium niobate, lead titanate, and triglycine sulfate ("TGS") are well known in the art. In addition, films of organic polymers such aε polyvinylidene fluoride and polyacrylonitrile have also been used aε pyroelectric materials.

For example, U.S. Pat. No. 3,809,920 teaches the use of a polyvinylidene fluoride film in conjunction with an FET as being an effective and useful infrared radiation detector.

U.S. Pat. No. 4,024,560 discloses an infrared detector which is a combination of a pyroelectric body secured by electrostatic bonding to the gate area of a field effect transistor such that the pyroelectric body is interposed between the semiconductor body and the gate electrode. In this position, the pyroelectric body forms the gate dielectric of the device. A pyroelectric crystal is typically cleaved, or cut, to form the pyroelectric body.

Japanese Kokai (Laid-Open) Publication JP58-182280 discloses a photodetector comprising a thin film FET and a pyroelectric material. The pyroelectric material forms the gate dielectric layer in this device.

Previously known hybrid εtructures suffer from a number of drawbacks. One drawback of hybrid εtructures concerns the pixel size of such devices. Generally, pixel size corresponds to the resolution of a detector.

A smaller pixel size means a higher density of pixels for higher resolution. In previously known hybrid structures, the pyroelectric material haε been positioned as the gate dielectric layer of the FET. As a result of this approach, achieving smaller pixel sizes has been limited by the size of the pyroelectric material.

Because the pyroelectric material of these devices is individually bonded to the field effect transiεtor, it has been difficult to achieve pixel sizes on the order of 1 mm x 1 mm or less.

As another drawback, the active detection area of such devices is, at most, only a few square centimeters in size.

As another drawback, hybrid structures tend to be susceptible to harm caused by events such as radiation induced damage. For example, if too much voltage is applied to such detectors, such voltage can irreparably damage the pyroelectric material, i.e., the gate dielectric layer, of the FET. This kind of damage could impair the performance of, or even destroy, the detector.

As a consequence of these drawbacks, previously known hybrid structures have not been practical for high density, large area applications.

Solid state detector arrays have also been known. One type of solid state detector array iε the charged coupled device ("CCD"). In eεεence, a CCD iε a shift register formed by a string of closely spaced MOS capacitors. A CCD can store and transfer analog-charge signals, either electrons or holes, that may be introduced electrically or optically.

In Japanese Journal of Applied Physicε, vol. 27, no. 12, December 1988, pp. 2404-2408, Hiroshi Tsunami et al. discuss the application of CCD's to take x-ray images of about 8 keV and 1.5 keV for different objects. High resolution CCD sensors which have more than 2 to 4 million pixels have also been reported, for example, in the Proceedings of Electronic Imaging West, Pasadena, California, pp. 210-213 (February 25-28, 1990); and in Electronic, pp. 61-62 (February 29, 1988).

The high cost of the CCD, however, has been a barrier to widespread commercial acceptance of these devices. CCD's, too, require an optical system in order to enlarge the field of view. The use of an optical system, unfortunately, causes a significant reduction in quantum efficiency. This makes it impractical to use the CCD for large area detectors. To date, the largest CCD array reported has been less than one square inch in ^ size.

Amorphous silicon recently has become a material of choice in many solid state detector applications due to its capability for large area deposition and the low cost of amorphous silicon !" detectors. Amorphous silicon-based solid state detectors generally have been in the form of a linear array. Such devices have gained widespread acceptance for use aε monolithic, full page high resolution detectors, due to the following advantages: (1) large area depoεition 5 capability, (2) low temperature depoεition, (3) high photoconductivity, (4) εpectral response in the visible light region and (5) high doping efficiency.

An amorphous silicon linear array is discusεed by Toεhihisa Hamano et al. (Proc. of the 13th Conference 0 on Solid State Devices, Tokyo, 1981, Japanese Journal of Applied Physics, Vol. 21 (1982) supplement 21-1, pp. 245-249). In this structure, metal (Au, Ni , or Cr, thickness of 3,000 angstroms) is used for the bottom electrode and Indium Tin Oxide transparent conducting ^ film is uεed for the top electrode. Glasε plateε (Corning 7059, PYREX) are used for the substrate. Amorphous silicon (a-Si:H) film with a thicknesε of 1 micron is deposited by plasma-enhanced chemical vapor deposition technique onto the subεtrate. 0 For x-ray applications, U.S. Pat. No. 4,675,739 describes a solid state linear array made from photosenεing elements. Each photoεensing element includes back-to-back diodeε: one a photoresponεive diode and the other, a blocking diode. Each of the diodeε has 5 an associated capacitance formed by its electrodes. The magnitude of the charge remaining on a given capacitor is sensed and relates back to the intenεity of the incident radiation impinging upon the photosensitive diode. In this structure, an amplifying means, i.e., a field effect transistor is not used.

Solid state detectors in the form of a linear array, however, must be moved in order to get a two-dimensional image. This introduces a long read-out time, which makes real-time read-out impractical. This drawback prevents the linear array detector from being used in applications where high speed is required, e.g., medical x-ray applications.

U.S. Pat. No. 4,689,487 describeε the use of a large area solid state detector (40 cm x 40 cm). The solid state detector includes pixels in the form of a 2,000 x 2,000 matrix. Each pixel conεiεts of a photodiode conductively connected in parallel to a capacitor. The photodiode and the capacitor are both then conductively connected to the drain of a metal- oxide-semiconductor field effect transistor (MOSFET). The photodiodes are of a polycrystalline or amorphouε material. This diode-MOSFET device has at least four main drawbacks. Firεt, a non-deεtructive read-out cannot be used. Second, the sensitivity of the device is low. Third, the diode haε to operated in the forward mode in order to turn on the tranεiεtor. Fourth, the device requires at least 8 complex microlithography and deposition stepε for fabrication, causing yields to be low.

U.S. Pat. Noε. 4,606,871, 4,615,848, and 4,820,586 disclose a pyroelectric material that is a blend of polyvinylidene fluoride ("PVF-") and at least one polymer miscible therewith at a temperature above the melting point of the PVF.. The film may be polarized to render the PVF₂ blend pyroelectric and isotropically piezoelectric. Example 10 in each of these patents describes the coating of an integrated circuit slice of a single crystal silicon chip with the PVF₂ blend, followed by the sputtering of gold onto the surface of the PVF₂ for poling.

DISCLOSURE OF INVENTION

The present invention provides a large area, high pixel density, solid state detector with a real-time^' and a non-destructive read-out. It is believed that the solid state detector of the present invention is the first practical, large area, high pixel density solid state detector that is based on a two-dimensional array of field effect tranεistors ("FET'ε").

The solid state detector of the present invention comprises a plurality of field effect tranεistors ("FET's") depoεited onto a substrate to form an array. A planarization layer is deposited over the array of FET's. An energy sensitive layer is depoεited onto the planarization layer. Meanε is provided for electrically connecting the energy sensitive layer with each FET of the array. A top electrode layer is deposited onto the energy sensitive layer. The solid state detector also comprises circuitry meanε for providing electronic read-out from each FET of the array.

The preεent invention enjoyε a unique combination of advantageε. Becauεe the energy sensitive layer is coated over the entire array of FET's, patterning or individual placement of the energy sensitive layer onto each FET is not required. This greatly simplifies the fabrication proceεε, especially when the energy εenεitive layer iε relatively thick, i.e., thicker than 10 micronε. Aε a consequence, the solid state detector is amenable to masε production techniques so that large area, solid state detectors can be fabricated in large numbers at relatively low cost. Large area means that the detector may have a radiation detecting area greater in εize than 10 cm x 10 cm. Further, the present invention also differs from previously known FET-containing, solid state detectors in that the energy sensitive layer of the present invention is not positioned as the gate dielectric layer of the FET's. Instead, the energy sensitive layer functions aε an additional capacitance which is, in effect, connected in serieε with the gate capacitance of each FET of the array.

This approach provides at least two advantages. First, this approach provides solid state detectors with higher pixel density than previously known εtructures that are based on the FET. According to the present invention, pixel size is determined by the size of the gate region on each FET of the array. In preferred embodiments of the present invention comprising a plurality of thin film FET's, the gate region of each FET is extremely small. Sizes of from 20 microns x 20 microns to 50 microns x 50 microns are typical. As a result, pixel densitieε aε high aε 250,000 pixels/cm can be achieved.

Second, this approach provides solid state detectors that are less suεceptible to harm cauεed by events such as radiation induced damage. According to the present invention, it iε the energy εenεitive layer that protectε the εolid state radiation detector from such harm. If a high voltage iε applied to the detector, the voltage of preferred embodimentε will tend to drop mainly in the energy sensitive layer, whose capacitance is typically lower than the gate capacitance. In thiε way, damage to the FET's of the array is minimized.

The present invention iε alεo a real-time detector. Read-out times of the detector of from 1 to 4 εecondε are feaεible. Read-out time iε defined as the time elapεing between the time an object is subjected to illumination and the time an image appears on the monitor. The present invention also has a non¬ destructive read-out. Non-destructive read-out means that the charge stored in the energy sensitive layer will discharge gradually over a period of time. This allows several readings to be taken at each exposure. The signal can then be averaged, thereby enhancing the signal to noise ratio.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a cut-away isometric view of the solid state detector of the present invention shown in schematic^"*with parts broken away and shown in section.

FIG. 2 iε an electronic circuit diagram of the solid state detector of the present invention shown in FIG. 1.

FIG. 3a iε a εide section of a substrate useful in the practice of the present invention.

FI.G. 3b iε a side section of a substrate useful in the practice of the present invention.

FIG. 3c is a side section of a substrate useful in the practice of the present invention.

FIG. 3d is a side section of a substrate useful in the practice of the present invention.

FIG. 4 is a side section of a solid state detector of the present invention.

FIG. 5a is a side εection of the εolid .εtate detector shown in FIG. 4, wherein the planarization layer haε a double layer εtructure.

FIG. 5b iε a εide εection of the εolid εtate detector εhown in FIG. 4, wherein the planarization layer has a triple layer structure.

FIG. 5c iε a εide εection of the εolid εtate detector shown in FIG. 4 further compriεing a phoεphor layer. FIG. 5d is a side section of the solid state detector shown in FIG. 4, further comprising an additional insulating layer for charge storage.

FIG. 6 is a side section of an alternative embodiment of the present invention.

FIG. 7 is the equivalent circuitry for one FET of a solid state detector of the present invention.

FIG. 8 shows an apparatuε useful for poling an energy sensitive layer which comprises a PVF₂ blend.

DETAILED DESCRIPTION

A preferred solid state detector 10 of the present invention will now be described with reference to FIG. 1 and FIG. 2. A plurality of thin film, field effect transistors ("FET's") 11 are deposited onto a subεtrate 12 to form an array. Preferably, the FET's 11 are aligned on the substrate 12 in rows and columnε as shown in FIG. 1. However, the FET's 11 may be arranged in other patterns on the εubstrate 12. For example, adjacent FET's 11 may be offset up, down, or diagonal from each other. Each of the FET's 11 haε a source electrode 13, a drain electrode 14, and a gate electrode 15. As seen best in FIG. 2, each FET 11 also haε a gate capacitance, C. .

The εolid state detector 10 comprises circuitry means for providing electronic read-out from each FET 11 of the array. The design requirements for such circuitry are described, for example, in L. Tannas, Jr., ed., Flat Panel Displays and CRT's, pp. 91-137 (1987); and S. Sherr, Electronic Displays, pp. 182-320 (1979). Preferably, the circuitry means compriseε a plurality of source lines 17 linking the source electrodes 13 in each row of FET's 11 and a plurality of drain lines 18 linking the drain electrodes 14 in each column of FET's 11. For example, for an array comprising a 2000 x 2000 matrix of

FET's, there will be 2000 source lines and 2000 drain lines in the solid state detector.

The various source lines 17 and drain lines 18 should not be in electrical contact with one another.

That is, a source line should not contact other source lines or any of the drain lines, and a drain line should not contact other drain lines or any of the source lines.

For this reason, at leaεt one planarization layer 19 iε deposited over the array of FET's 11 in order to electrically isolate the source lines 17 and the drain lines 18.

An energy sensitive layer 20 is deposited onto the planarization layer 19. Means 21 iε provided for electrically connecting the energy sensitive layer 20 with each FET 11 of the array. Preferably, such meanε 21 electrically connectε the energy εenεitive layer 20 with the gate electrode 15 of each FET 11 of the array. As seen best in FIG. 2, using this preferred approach, the energy sensitive layer 20 functions aε an additional capacitance, C , which iε, in effect, electrically connected in serieε with the gate capacitance C_G of each FET 11 in the array.

A top electrode layer 23 is deposited onto the energy senεitive layer 20 in order to complete the solid εtate detector 10. The top electrode layer 23 εhown in FIG. 1 has not been patterned to form a plurality of top electrode elements. However, the top electrode layer 23 optionally may be patterned in a variety of ways, so long as the variouε top electrode elementε are electrically connected together εo aε to form a common top electrode. For example, the top electrode layer 23 may be patterned εuch that there iε one top electrode element for each FET 11 of the array. Aε another example, the top electrode layer 23 may be patterned such that there is one top electrode element for each row or column of FET's 11 in the array. Generally, the solid state detector 10 works as follows. A power source 28 is used to apply a charge to the energy sensitive layer 20. Incident radiation causes a corresponding change in the charge of the energy sensitive layer 20. This change in charge, in turn, causes the gate voltage of the FET's 11 to increase or decrease, depending upon the type of FET used in the array. This change in voltage iε detected aε a difference in the drain-εource current of the FET 11. The difference in current iε then amplified and detected aε an output signal by the read-out electronics. As seen in FIG. 2, one poεεible read-out electronicε εcheme may include operational amplifierε 24 for booεting the analog signal from the FET's 11. This analog signal iε then converted into a digital signal by an A/D converter 25. The digital signal is then stored in the memory of a memory storage device 26. Aε iε alεo εhown in FIG. 2, source lines 17 are coupled to shift register 27.

Preferred substrates useful in the practice of the present invention are shown in FlGs. 3a, 3b, 3c, and 3d. FIG. 3a shows a substrate 29 comprising a flexible base layer 30. Generally, the base layer 30 is planar in shape. Useful materials for forming the flexible base layer 30 include stainless steel and polymers such as polyimide, polysulfone, or polyeεter. If the baεe layer 30 iε formed from a polymeric material, the baεe layer 30 εhould be εubjected to a conventional outgaεεing treatment before any other layers are deposited onto the base layer. Preferably, the base layer 30 has a thickness of about 50 microns.

When the base layer 30 is formed from a polymeric material, it is preferred that the baεe layer 30 iε firεt coated on both sides with top and bottom layers 31 and 32 of stainlesε steel aε described in assignee's copending application United States Serial No. 07/471,670 filed January 24, 1990, which is a continuation of United States Serial No. 07/163,520 filed March 2, 1988, now abandoned. Each of the stainleεε steel layers 31 and 32 preferably has a thickneεε of about 200 angstroms. The stainlesε steel is used to prevent or suppresε the outgasεing of low mass residual contaminants from the base layer 30.

Next, an insulating layer 33 is coated onto the top εtainleεs steel layer 31. The insulating layer 33 iε used to electronically' isolate the base layer 30 from the field effect transistorε subsequently deposited onto the subεtrate 29. The insulating layer 33 also helps prevent impurities in the base layer 30 from diffusing into the field effect transistorε. The inεulating layer 33 may be prepared from any suitable material such aε SiO_χ , SiN_χ , εilicon oxide nitride, or combinationε thereof. Preferably, the inεulating layer 33 has a thickneεs of about 1 micron. Optionally, an additional insulating layer 34 may be coated onto the bottom layer 32 of stainleεε steel as is shown in FIG. 3b for the εubεtrate 29'.

Another embodiment of a εubεtrate 35 uεeful in the practice of the preεent invention iε shown in FIG. 3c. In FIG. 3c, the subεtrate 35 compriεes a rigid, nonpolymeric base layer 36. Useful materials for forming the rigid base layer 36 include silicon, glass, quartz, alumina, or metal. In this embodiment, an insulating layer 37 may be preferably deposited directly onto the top surface of the base layer 36 as needed in order to prevent impurities from migrating from the base layer 36 into the FET's and/or to electronically isolate the FET's from the base layer 36. Optionally, as εhown in FIG. 3d, an additional insulating layer 38 may be depoεited onto the.bottom εurface of the baεe layer 36 of the subεtrate 35'.

FIG. 4 iε a croεs-section of a portion of a preferred solid state radiation detector 40 of the present invention, in which two thin film, metal-oxide- semiconductor field effect transistors ("MOSFET's") 41 of the array are shown. For purposes of clarity, source lines and drain lines are not shown in FIG. 4. As iε known to those skilled in the art, each thin film MOSFET 41 generally compriseε a channel layer 42; a gate dielectric layer 43, i.e., oxide layer; insulating shoulders 44; source and drain regions 45 and 46; source and drain electrodes 47 and 48; a polysilicon gate 49; and a gate electrode 50; each of which will be described in more detail below. In FIG. 4, the vertical dimensions of the various layers are greatly exaggerated for purposes of illustration. In actual practice, the total thicknesε of the solid state radiation detector 40 is from about 3 to about 600 microns.

Aε shown in FIG. 4, a channel layer 42 of an undoped semiconducting material is formed on the substrate 51 for each thin film transiεtor of the array. The channel layer 42 can be formed in a variety of ways. For example, a layer of the undoped semiconducting material can be deposited onto the substrate 51 and then etched or laser scribed to form the channel layer 42 for each MOSFET 41. Alternatively, a mask can be uεed to deposit the discrete islands of undoped semiconducting material onto the subεtrate 51 to directly form the channel layer 42.

The channel layer 42 may be formed from any undoped semiconducting material suitable for large area applications. Examples of εuch materialε include hydrogenated amorphouε silicon, cadmium selenide, single- crystal silicon, and polysilicon. Single-cryεtal εilicon-based FET's are well known in the art and are described, for example, in S.M. Sze, Physicε of Semiconductor Devices, 2d edition, pp. 431-510 (1981). When forming the channel layer 42 from hydrogenated amorphous silicon, the hydrogenated amorphous silicon may be deposited using plasma-enhanced chemical vapor deposition at 200°C to 350°C from a gaseous mixture of SiH₄ and hydrogen. Cadmium selenide may be deposited onto the substrate 51 by deposition techniques well known in the art. For example, by using a cadmium selenide source, thermal evaporation or sputtering techniques may be uεed to deposit the cadmium selenide. Alternatively, a cadmium layer and a selenium layer may be deposited onto the εubεtrate 51 and then heat treated at 100°C to 400°C in an atmosphere comprising hydrogen selenide and argon in order to form the cadmium selenide layer. The cadmium and selenide layers may be deposited using electroplating or sputtering techniques.

Preferably, the channel layer 42 iε formed from polysilicon. When forming the channel layer 42 from polysilicon, polysilicon can be deposited onto the substrate 51 using a variety of techniques, including:

(i) low presεure chemical vapor depoεition at a temperature from 620°C to 650°C;

(ii) depoεition of amorphouε εilicon by low pressure chemical vapor depoεition at a temperature from 520°C to 540°C, followed either by annealing at 620°C to 1000°C for 2 to 24 hourε in a nitrogen atmoεphere to form polysilicon, or by rapid thermal annealing at 620°C for 1 to 4 minutes in a nitrogen atmosphere to form polysilicon;

(iii) deposition of amorphouε εilicon at 200°C to 300°C via plasma-enhanced chemical vapor deposition, followed by furnace annealing, laser annealing, or rapid thermal annealing;

(iv) high temperature chemical vapor deposition of polysilicon at 620°C, conversion of the polysilicon to amorphous silicon via ion implantation with silicon ions, followed by annealing at 620°C for 4 to 24 hourε to form polysilicon.

Typically, the channel layer 42 of undoped polysilicon haε a thickneεε of from about 1000 to 3000 angstroms. Because polyεilicon iε depoεited onto the substrate 51 at relatively high temperatures, the baεe layer of the substrate 51 for the polysilicon-based MOSFET's should comprise a material that does not degrade at such temperatures, e.g., quartz, silicon, alumina, or glass.

An oxide, i.e., gate dielectric, layer 43 and insulating shoulders 44 are formed on the channel layer 42. To accomplish this, a layer of an insulating material, such as SiO SiN silicon oxide nitride, or combinations thereof, iε grown by thermal oxidation on the channel layer 42. The layer of insulating material is then etched, or laser scribed, to form the insulating shoulders 44 and the gate dielectric layer 43. This procesε also uncovers two spaced-apart surfaces on the channel layer 42 for the subsequent formation of source and drain electrodes 47 and 48, respectively.

A polysilicon gate 49 iε depoεited onto the gate dielectric layer 43. Typically, the polyεilicon gate 49 haε a thickneεε of about 500 to about 3500 angstroms. Preferably, the polysilicon gate 49 is deposited onto the layer of insulating material before the layer is etched, or laser scribed, to form the insulating shoulders 44 and the gate dielectric layer 43. Using the polysilicon gate 49 and insulating shoulderε 44 aε a maεk, the source and drain regions 45 and 46 are formed by using conventional ion implantation techniques to dope the source and drain regions 45 and 46 with either boron ions (p-type) or phosphorous ions (n-type). The ion concentration will vary with the particular electrical characteristics and sensitivity of the desired detector. As an example, ion concentrations of IxlO¹⁴ ions/cm² to 9xl0¹⁵ ionε/cm² are typical.

Ion implantation to form the εource and drain regionε 45 and 46 can occur either before or after the layer of inεulating material iε etched, or laεer scribed, to form the insulating shoulders 44 and the gate dielectric layer 43. If ion implantation occurs before such etching or laser scribing, then the polyεilicon gate 49 should be relatively thick in order to stop the ions from entering the channel region 52 beneath the polysilicon gate 49. Preferably, ion implantation occurs after such etching or laser scribing. One advantage of this preferred approach is that the polysilicon gate 49 may be relatively thinner, since less ion implantation energy is used to form the drain and source regions 45 and 46. As another advantage of the preferred approach, plasma hydrogenation treatment of the FET^rε 41 iε easier when the polysilicon gate 49 is relatively thinner. Such treatment is uεed to pasεivate the grain boundaries of the channel layer 42.

The source and drain regions 45 and 46 may or may not be of the same conductivity type. For example, both the source and drain regions 45 and 46 may comprise either p-type ions or n-type ionε. Alternatively, one of the regionε may compriεe p-type ionε, and the other region may comprise n-type ionε.

When forming the drain and εource regionε 45 and 46, uεe of the polyεilicon gate 49 aε a mask provides accurately defined source and drain regions 45 and 46. Even when the size of the FET's 41 iε extremely small, i.e., 10 to 20 μm, ion implantation will occur in the source and drain regions 45 and 46, but not in the channel region 52 between the source and drain regions.

The various source electrodes 47, source lines (not shown in FIG. 4), drain electrodes 48, and gate electrodes 50 are simultaneously formed. Each source electrode 47 and drain electrode 48 iε in ohmic contact with the εource region 45 and drain region 46, reεpectively. Each gate electrode 50 iε positioned in intimate contact with the polysilicon gate 49. The various source electrodes 47, source lines, drain electrodes 48, and gate electrodes 50 may be formed by first growing a masking layer over the array. Portions of the masking layer corresponding to the positions of the source electrodes, source lines, drain electrodes, and gate electrodes are then selectively removed. The electrodes and source lines are then formed by vapor or sputter deposition of a suitable contact metal over the entire surface of the masking layer. Thereafter, unwanted metal iε εelectively removed from the masking layer by standard photolithographic and etching techniqueε.

Suitable contact metalε for forming the electrodes and the source lines include the common contact metals, such as molybdenum, chromium, aluminum, silicon-doped aluminum, nickel, silver, tin, indium, palladium, titanium, copper, platinum, and the like. Typically, the electrodes and source lines have a thickness of from about 1000 to about 10,000 angstroms, and more commonly from about 1500 to about 5000 angstroms.

The array of FET's 41 thus formed iε then annealed in a forming gaε of nitrogen and hydrogen at about 400°C for 30 minutes. Annealing enhances the quality of ohmic contact between the source electrode 47 and the source region 45 and between the drain electrode 48 and the drain region 46. Annealing is followed by a plasma hydrogenation treatment at about 300°C for 10-60 minutes. This treatment passivateε the grain boundarieε of the channel layer 42 with hydrogen, thereby reducing the amount of leakage current from the FET's 41 of the array.

A planarization layer 53 iε coated over the array of FET'ε 41. The planarization layer 53 iε formed from an insulating -* material such as SiOX , SiNX , silicon oxide nitride, or combinationε thereof. The planarization may also be formed from a polyimide such as Probimide 408 commercially available from Ciba-Geigy Corporation. Typically, the planarization layer 53 haε a thicknesε of about 1 to 2 micronε. In some cases, as shown in FIG. 5a for the solid state detector 40a, the planarization layer may be a double layer comprising a first layer 53a of SiN_χ having a thicknesε of about 3000 angstroms and a second ^• layer 53b of SiO having a thicknesε of about 3000 angstroms. Alternatively, as shown in FIG. 5b for the solid state detector 40b, the planarization layer may be a triple layer compriεing a firεt layer 53c of SiN_χ having a thickneεε of 2000 angεtromε, a second layer 53d of SiO having a thickness of 2000 angstromε, and a third layer 53e of SiN having a thicknesε of 2000 angstroms.

Preferably, the planarization layer 53 haε a "planarized", i.e., smooth, upper surface. The planarization layer 53 may be planarized by coating the planarization layer with a 2 to 3 microns thick layer of a photoresist material. After forming the layer of photoresist material, the layer of photoresist material is etched down to the planarization layer to provide a smooth upper surface. Etching may be accomplished using reactive ion etching techniques in a gaseous mixture of CF₄ and 0₂. The photoresist material should be selected so that the photoresist material haε the εame etch rate aε the planarization layer 53. Exampleε of εuch photoresist materials found to be suitable in the practice of the present invention are, for example, Shipley AZ 5209 and Shipley AZ 5214. Aε another example, a planarized εurface may be obtained when uεing Probimide 408 by first coating the material over the array of FET's to a thickneεε of 3 to 5 micronε. After thiε, the Probimide 408 is etched until a εmooth-εurfaced layer having a thickneεε of about 1 to 2 micronε iε achieved. Such etching may be accompliεhed using a reactive ion etching technique in 0₂ plaεma. In thoεe caseε where the energy sensitive layer 54 is relatively thick, i.e., thicker than about 10 microns, it is not necessary to planarize the planarization layer 53.

An energy sensitive layer 54 is deposited onto the planarization layer 53 to further coat the array of thin film transistors 41. Preferably, the energy sensitive layer 54 is deposited as a continuous layer over the entire planarization layer 53 without the need for any patterning steps. Advantageously, this feature of the invention significantly simplifies the fabrication process, especially when the energy sensitive layer 54 is relatively thick, e.g., having a thickness of from about 10 to about 500 microns.

The energy sensitive layer 54 compriseε a material for which incident radiation causes a corresponding change in the charge of the material. Many such materials are known and include amorphous εelenium; cadmium telluride; cadmium εelenide; cadmium sulfide; mercury cadmium telluride; selenium-based alloys; telluride-baεed alloys; selenium-tellurium; hydrogenated amorphouε silicon and alloys thereof; polyvinylidene fluoride ("PVF₂" ); a blend of PVF₂ and at least one polymer which iε miscible with PVF₂ at a temperature above the melting point of PVF₂ ; vinyl fluoride; vinyl chloride; vinylidene chloride; chlorofluorovinylidene; trifluoroethylene; poly-N-vinyl-carbazole; trinitro- fluorenone; lithium niobate; lithium tantalate; Sr_{l χ}Ba₂O_χ; pyrargyrite; Tl.AεSe. ; PbO; ZnO; organic photoconductive materialε; and the like.

The various materials useful for forming the energy sensitive layer 54 may be εenεitive to x-ray, ultraviolet, infrared, and/or visible electromagnetic radiation. For example, x-ray senεitive materialε include amorphouε εelenium; cadmium selenide; cadmium telluride; mercury cadmium telluride; cadmium sulfide selenium-based alloys; tellurium-based alloys; selenium- tellurium; hydrogenated amorphous silicon and alloys thereof; PbO; ZnO; or combinations thereof. Ultraviolet sensitive materials include PVF₂ ; hydrogenated amorphouε silicon and alloys thereof such aε εilicon carbide.

Visible light sensitive materials include hydrogenated amorphous silicon and alloys thereof; amorphous selenium; cadmium selenide; cadmium telluride; cadmium sulfide selenium-based alloys; telluride-based alloys; εelenium- tellurium; mercury cadmium telluride; and organic photoconductive materials. Infrared, i.e., pyroelectric materials, include PVF₂ ; vinyl fluoride; vinylidene chloride;^' chlorofluorovinylidene; trifluoroethylene; lithium niobate; ' lithium tantalate;' Sr1, - xBa.2Ox ;' pyrargyrite; and Tl.AsSe..

When using hydrogenated amorphous silicon and alloys thereof to form the energy senεitive layer 54, the amorphous silicon generally is doped to obtain a high resistivity,- i.e 10 13 ..-cm, and a high photoconductivity, i.e., photocurrent to dark current ratio of 10³ to 10 . To provide an energy sensitive layer with such properties, the amorphous silicon may be doped with about 1 to 100 pp of both boron and oxygen atoms. Alternatively, the amorphous εilicon may be doped with about 1 to 100 ppm of chemical elementε from Group VI of the Periodic Table, εuch aε εelenium or εulfur. Such doping techniqueε are well known in the art and are described, for example, in U.S. Pat. No. 4,265,991; Shimizu, Semiconductors and Semimetalε, vol. 21, part D, Academic Press, pp. 55 to 73 (1984); and Shimizu, Journal of Non-Crystalline Solids, volε. 77 and 78, pp. 1363 to 1372 (1985).

After forming the planarization layer 53, drain leadε 60, drain li.neε (not εhown in FIG. 4), and meanε for electrically connecting the energy εenεitive layer 54 with each FET 41 of the array are formed. Preferably, εuch means iε formed such that the additional capacitance of the energy sensitive layer 54 is effectively connected in series with the gate capacitance, i.e., gate dielectric layer 43, of each FET 41 of the array. Such means preferably comprises a contact plug 55 and a bottom electrode 56.

The drain lead 60, drain line, contact plug 55, and bottom electrode 56 may be formed by first using standard etching or lift-off techniques to uncover the drain electrode 48 and gate electrode 50. After this, the drain lead 60, drain line, contact plug 55, and bottom electrode 56 are formed from a εuitable contact metal, such as those metals described above with respect to the various electrodes and the source lineε. For infrared applicationε, the top electrode layer 57 may comprise a conductive, radiation absorbing material for which incident radiation causes the temperature of the material to change. Examples of such materials include metals such as nickel, aluminum, gold, tin, indium, palladium, titanium, copper, and base metals thereof. Of these materials, gold and aluminum are more preferred.

For other applications, the top electrode layer 57 may comprise a transparent, conductive material which allows incident radiation to pasε through and be abεorbed by the energy sensitive layer and which functions as an antireflection layer to maximize the amount of light photons that reach the energy sensitive layer. Examples of such materials include transparent conducting oxide ("TCO") materials, such as indium tin oxide, tin oxide, cadmium tin oxide, and zinc oxide. Stacked εtructures, such as a TCO/Ag/TCO structure or a TC0/(Ag/TC0)_n structure where n is preferably an integer from 1 to 3, may also be used. Stacked structures are described, for example, in assignee'ε copending application, United Stateε Serial No. 280,838 filed December 7, 1988. The top electrode layer 57 can be formed by depositing the top electrode material over the entire energy sensitive layer 54. Optionally, the top electrode layer 57 may be patterned to form a plurality of diεcrete top electrode elements, wherein all of the discrete elements are electrically connected to form a common top electrode. Patterning may be accomplished by removing unwanted material in between the FET's 41 using standard etching techniques. Alternatively, using thermal evaporation or sputtering techniques, the common, top electrode elements can be deposited onto the energy sensitive layer 54 through, a mask to directly form the discrete electrode elements without the requirement of a patterning step. Typically, the top electrode layer 57 has a thickness of from about 500 angstromε to 6000 angstroms for transparent conducting materials, and from 5000 angstroms to 3 microns for radiation abεorbing materials. The lesεer thickneεεeε are more responεive to incident radiation.

Aε shown in FIG. 5c for the εolid state detector 40c, a phoεphor layer 58 optionally may be depoεited, or phyεically placed, onto the top electrode layer 57 to make a εolid εtate detector for detecting x-rayε. For placing the phoεphor layer 58 onto the top electrode layer, an optically matched glue iε preferably used to maximize the number of photons that reach the energy εensitive layer 54. The phosphor layer 58 comprises a material that converts x-rays into light. Examples of such materialε include Gd₂0₂S:Tb; BaFBr:Eu; Sr₅Si0₄ ; SrS0₄ ; RbBr:Tl; and ZnS:Cu:Pb. Such materials are deεcribed, for example, in U.S. Pat. No. 4,011,454 and European Patent Application No. 0175578-A3.

Aε shown in FIG. 5d for the εolid εtate detector 40d, at leaεt one additional, inεulating layer 59 may be interpoεed between the planarization layer 53 and the energy εensitive layer 54. The additional insulating layer 59 is used as a capacitance for additional charge storage and may comprise insulating materials such as SiN X ,' SiOX ,' and the like.

FIG. 6 shows another preferred solid state radiation detector 60 of the present invention in which the field effect transistorε 61 are hydrogenated amorphous silicon-based MOSFET's. In FIG. 6, the materials and thicknesses of each layer are the same aε the corresponding layers described with reference to FIG. 4, unless otherwise noted. In FIG. 6, εource and drain electrodeε 62 and 63 are depoεited onto the subεtrate 64. As one option, the εubεtrate 64 may contain a base layer that is formed from a material such as quartz, glass, silicon, or metal. Yet, because hydrogenated amorphous silicon may be deposited onto the subεtrate 64 at relatively low temperatureε, the baεe layer of the εubεtrate 64 may alεo be formed from a flexible, polymeric material, e.g., polyimide, polyester, or polysulfone. Using conventional maεking techniques, a 500 angεtrom thick layer of n-type hydrogenated amorphous εilicon is depoεited by plasma-enhanced chemical vapor deposition onto each source and drain electrode 62 and 63 to form the source and drain regionε 65 and 66, reεpectively.

A channel layer 67 of hydrogenated amorphous εilicon iε deposited over the source and drain regions 65 and 66. Typically, the channel layer 67 of hydrogenated amorphous silicon has a thickness of about 1000 to 10,000 angstroms, and more preferably of about 5000 angstroms. A gate dielectric layer 68 iε depoεited onto the channel layer 67. The gate dielectric layer 68 has a thickneεs of from 1000 to 5000 angstroms. A gate electrode 69 (3000 to 5000 angεtroms) compriεing aluminum, chromium, or any other εuitable electrode material, iε then depoεited onto the gate dielectric layer 68. Drain lead 63a iε formed to provide ohmic contact between the drain region 66 and the corresponding drain line (not shown in FIG. 6). An array of thin film, hydrogenated amorphouε silicon-based MOSFET's 61 supported upon the substrate 64 is thereby formed. A planarization layer 70 is then deposited over the array of FET's 61 in order to electrically isolate the drain and source lines (not shown in FIG. 6). An energy sensitive layer 71 is deposited onto the planarization layer 71'. A contact plug 72 and bottom electrode 73 electrically connect the energy εensitive layer 71 with the gate electrode 69 of each FET 61 of the array. A top electrode layer 74 is deposited onto the energy sensitive layer 70.

The invention will be further described with reference to the following examples.

EXAMPLE 1 A polyεilicon-baεed solid state detector for detecting x-rays was made aε followε:

First, an array of polysilicon-based MOSFETε supported on a εubstrate was prepared aε followε. An insulating layer of SiO_χ was grown by thermal oxidation in dry oxygen at 1050°C for 3 hours on a silicon wafer base layer. Next, a layer of undoped amorphous εilicon having a thickneεε of 1500 angεtromε waε depoεited onto the insulating layer at 560°C and 180 millitorr by pyrolytic decomposition of silane uεing the low preεεure chemical vapor deposition ("LPCVD") technique. The amorphous silicon was then annealed in a nitrogen atmosphere (1.5 Torr) at 620°C for 24 hourε to form a polyεilicon layer, i.e., "LPCVD polyεilicon". The LPCVD polyεilicon layer waε then patterned into iεlandε uεing microlithography techniqueε to form a channel layer for each transistor of the array. Next, a 1000 angstrom layer of SiO_χ was deposited over the polysilicon channel layers by thermal oxidation of the LPCVD polysilicon layer at 1150°C in dry oxygen for 30 minutes. Uεing the techniqueε deεcribed above, a gate layer of LPCVD polyεilicon waε formed at 620°C over the gate oxide layer. For each MOSFET, the polysilicon gate layer was etched to form the polysilicon gate.

In order to obtain a device having n-type characteristicε, 3.7 x 10¹⁵/cm² phoεphorous was implanted to dope the source, the drain, and the polysilicon gate. The energy of the ion implanter was 175 keV. The dopantε were activated during a 30 minute nitrogen anneal at 1050°C. Th<= SiO_χ layer waε then etched to open the drain and source region for electrode contact.

Next, a firεt layer of an aluminum alloy (1.0% Si, 0.4 % Cu, 1000 angεtromε) and a εecond layer of chromium (2000 angεtromε) were sputtered onto the gate region, source region, and drain region to form the gate electrode, the source electrode, and the drain electrode, respectively. Source lines were also deposited at this time. Sputtering took place at a chamber pressure of 9 x 10^" Torr. Argon gas presεure was 7 millitorr, and the sputtering apparatus was operated at 500 W. The sputtering time for the aluminum alloy layer was 7 minutes, and the sputtering time for the chromium layer was 11 minutes.

The resulting array of thin film, field effect tranεiεtors waε annealed in a forming gas (85% N₂ , 15%

H, ) at 400°C for 30 minutes in order to enhance the adheεion and the contact of the electrodeε to the source, drain, and gate regionε. After thiε, the array of thin film, field effect tranεistors was subjected to a plasma hydrogenation treatment in order to reduce the dangling bonds at the grain boundarieε of the polysilicon channel layer. This treatment took place at 300°C and 0.55 Torr for 1.5 hourε in an atmosphere of 50% H₂ and 50% N₂. The flow rates of the hydrogen and nitrogen were each 70 seem, and power density was 1.36 W/cm². The equipment used for the treatment was operated with an electrode distance of .875 inches and a radio frequency of 13.56 MHz. Suitable equipment for performing the plasma hydrogenation treatment is commercially available, for example, from Plasma Technology, Concord, Massachusetts, or Glaεε TechSolar, Boulder, Colorado. A planarization layer waε depoεited over the array of thin film, field effect tranεiεtorε as follows. A firεt layer of SiN having a thickneεε of 3000 angεtromε waε depoεited over the array at 300°C uεing the plasma-enhanced chemical vapor technique. This waε followed by depoεiting a second layer of SiO_χ having a thickneεε of 2000 angεtromε alεo at 300°C using the plasma-enhanced chemical vapor technique. This was followed by depositing a third layer of SiN_χ having a thickness of- 2000 angstroms using the same plasma- enhanced chemical vapor deposition technique. Depoεition conditions for SiNx were a flow rate of SiH4. of 17.3 seem, a flow rate of NH 3 of 10.8 seem, and a power density of 0.4 W/cm .2. Depoεition conditionε for SiOx were a flow rate of SiH 4, of 4.71 εccm,' a flow rate of N,2 of 60 εccm, a flow rate of N₂0 of 17.1 εccm, and a power denεity of 0.06 W/cm².

Holeε expoεing the gate electrode of each field effect transistor of the array were formed in the planarization layer by uεing the gate electrode aε a maεk for the reactive ion etching of the planarization layer. Reactive ion etching waε accompliεhed with 40 εccm CF₄ and 0.84 0₂ at 250 W for 16 minutes. After forming the holeε, the holeε were filled with plugε of chromium having a thickness, of 6000 angstromε. Next, a 3000 angstrom thick chromium layer was depoεited over the planarization layer. Thiε layer waε then patterned to form a diεcrete, bottom electrode for each transistor of the array. The size of the bottom electrode for each FET determined the gate size of the FET, and therefore, the pixel size of the resulting solid state detector. Drain lines were also deposited at this time.

Next, a layer of SiN_χ having a thickness of 3000 angstroms was deposited over the array using plasma-enhanced chemical vapor deposition techniques. The purpose of this layer was to provide additional capacitance for charge storage. An energy εenεitive layer of hydrogenated amorphouε εilicon having a thickness of 1 micron was deposited over the entire array and was not patterned.

Next, a layer of indium tin oxide ("ITO") having a thickness of 6000 angstroms was deposited onto the energy sensitive layer at 100°C and 200 W in 100 millitorr of argon gas using the sputtering technique. The ITO was then patterned to form common top electrode elements, each element covering the FET's in a column of the array.

A phosphor layer of Gd₂0₂S:Tb, commercially available as Trimax 12B from Minneεota Mining And Manufacturing Company, was phyεically laid on top of the detector. Thiε layer was used to convert incident x-rays into visible light having a wavelength of 545 nm.

Optionally, the phosphor layer may be omitted. In such a case, the resulting solid state detector could be used for detecting visible light rather than for detecting x-ray radiation.

Operation of the solid state detector in which the phosphor layer was deposited onto the top of the detector was as followε. A uniform charge waε formed on the surface of the energy sensitive layer by applying a DC voltage as high as 10-20 volts between the drain electrode and the source electrode of each FET of the array. The voltage between the common, top electrode elements and each source electrode of the array, i.e., the gate voltage, was adjusted for optimum sensitivity between -5V and 15V. The energy sensitive layer of amorphous hydrogenated silicon acted as a capacitor (C_{s t} ) which was effectively connected in series with the gate capacitor (floating gate, C_G ) . An equivalent circuitry of of the solid εtate detector, depicting a single FET of the array, is shown in FIG. 7. In this circuitry, C_{s i} , C_s , C_d and C are the capacitance of the energy εenεitive layer, the εource, the drain and the gate, respectively.

The solid state detector was exposed to x-ray illumination (90 kVp, 200 mA, 100 microsecondε, 20 mm aluminum filter). The incident radiation waε converted into green light (wavelength of 545 nm) by the phoεphor layer which was then absorbed by the energy εenεitive layer. This caused the charge in the energy sensitive layer to decrease, cauεing a drop in the gate voltage. Thiε, in turn, cauεed a drop in the drain-εource current. The change in the drain-εource current waε converted into a voltage by a reεistor, R, and waε detected as an output voltage signal. This signal was amplified, converted into digital by an A/D converter, and then stored in a memory.

EXAMPLE 2

A polysilicon-based solid εtate detector for directly detecting x-rays without requiring a phosphor layer would be prepared as follows. The procedure for making such a detector would be the same aε the procedure deεcribed in Example 1, except that an energy εensitive layer of amorphous selenium having a thickness of 300 to 500 microns is εubεtituted for the energy εenεitive layer of hydrogenated amorphouε silicon. The amorphouε εelenium iε depoεited at room temperature, uεing the thermal evaporation technique. It should be noted that εelenium can undergo a phaεe change from the amorphouε phase to a polycrystalline phase at temperatures as low as 50-60°C. Thus, the deposition of amorphouε εeleniura should be done in several steps to avoid this phase change.

EXAMPLE 3

A polysilicon-based εolid state detector for detecting infrared radiation was prepared as follows. The procedure for making such a detector was the same as the procedure described in Example 1, except that an energy sensitive layer containing PVF₂ waε subεtituted for the energy sensitive layer of hydrogenated amorphous silicon. The energy εenεitive layer containing the PVF₂ waε a blend of polyvinylidene fluoride ("PVF₂") and dimethylmethacrylate ("PMMA") aε deεcribed in U.S. Pat. Noε. 4,606,871; 4,615,848; and 4,820,586. The blend was poled to eεtabliεh pyroelectric propertieε. Preferred thicknesε of the energy sensitive layer ranged from about 3 to about 7 microns. Deposition and poling of the energy sensitive layer was as follows:

24 grams of PMMA were disεolved in 36 grams of methyl ethyl ketone ("MEK") and mixed thoroughly. 36 gramε of PVF₂ and 304 grams of dimethylformamide ("DMF") were added to the PMMA εolution, and the εolution waε thoroughly mixed again.

The reεulting εolution was coated over the array of thin film transistors by spin coating. Alternatively, the resulting solution may also be coated over the array by immerεing the array in a container containing the PVF₂ blend and then withdrawing the array from the container at a rate of about 1.2 cm/minute. Thiε would reεult in a coating thickneεε of about 5 micronε. The coated array was then air dried at about room temperature in a dust-free environment until the coating became white, which was indicative of drynesε. After this, the coated array waε heated in an oven for about 10 minuteε at 60°C to drive off the MEK. Then, the the temperature waε raised to 140°C and maintained at 140°C for about 10 minutes in order to 5 drive off the DMF. The temperature waε increaεed again to 200°C and maintained at 200°C for about 5 minuteε. The array was then cooled to room temperature, allowing the beta state of the PVF₂ to set.

Poling of the PVF₂ blend was accomplished by

10 placing the coated array in an electric field of suitable strength to set the dipole moment of the PVF₂. The apparatuε 75 of Fig. 8 iε uεeful to accompliεh the poling function. The coated array 76 waε supported on a conductive support plate 77 which was placed in an oven 15 78. A corona generating array 79, comprising a conductive screen 80 and a pattern of conductive needles 81 was supported in, and electrically isolated from, the oven chamber by insulating support members 82. A corona power supply 83 (for example, CORONATROL™ , manufactured by Monroe Electronics, Inc., Lyndonville, NY) was

- connected to support plate 77 and the corona array 79 by leads 84 and 85. The needles 81 were diεpoεed in a two-dimensional geometrical pattern with separation between adjacent needles of about 12 mm. A distance of

?³ •*, about 50 mm was maintained between the tips of needles 81 and the top surface of coated array 76. Poling waε then achieved by inεerting the coated array 76 into the oven

78, generating a corona diεcharge on the PVF₂ surface of

900 volts, gradually increasing the oven temperature to

30 about 105°C while maintaining said surface charge, and allowing the oven temperature to decline back to room temperature while εtill maintaining εaid εurface charge. Finally, the common, top electrode elementε of aluminum were depoεited over the gate region of each 5 transistor of the array. In this structure, the common, top electrode elementε abεorbed and were heated by infrared radiation. The increase in temperature caused a corresponding increase in temperature of pyroelectric layer 29, which in turn caused a change in the gate voltage, and therefore a change in the drain-εource current of the polysilicon-based thin film transiεtors.

EXAMPLE 4 A hydrogenated amorphous εilicon-baεed εolid εtate detector for detecting infrared radiation waε prepared aε followε. A layer of Si0₂ having a thickneεε of 1 micron was deposited onto a 3 inch x 3 inch single crystal silicon wafer by thermal oxidation in dry oxygen. Next, a layer of chromium having a thickneεε of 3000 angεtroms waε depoεited onto the layer of SiO.. This waε followed by using plasma-enhanced chemical depoεition techniqueε to depoεit a layer of n-type hydrogenated amorphouε silicon (500 angstromε) onto the chromium layer. The n-type hydrogenated amorphouε εilicon waε deposited using a procesε temperature of 250°C, a flow rate of SiH₄ of 21.2 seem, a flow rate of 1% PH. diluted in hydrogen of 5.5 seem, a flow rate of hydrogen of 76.4 seem, and a power density of 0.043 W/cm². The chromium layer and the layer of n-type hydrogenated amorphous silicon were then etched to form the drain and source electrodes and the drain and source regionε, respectively, for each FET of the array.

The entire array was then coated with a layer of intrinsic a-Si:H using the plaεma-enhanced chemical vapor deposition technique. The layer of intrinsic a-Si:H was then patterned to form the channel layer for each thin film transiεtor of the array. A dielectric layer of SiN_χ (3000 angstroms) was then deposited onto the channel layer of each transistor, followed by the deposition of a gate electrode onto each dielectric layer. An energy senεitive layer of a PVF₂ blend and common, aluminum top electrode elements were coated over the array, and the PVF₂ blend waε then poled aε deεcribed in Example 3 to complete the detector. Other embodiments of this invention will be apparent to those skilled in the art from a consideration of this specification or from practice of the invention disclosed herein. Various omissionε, modificationε, and changes to the principles described herein may be made by one skilled in the art without departing from the true scope and spirit from the invention which is indicated by the following claims.

Claims

What is claimed is:

1. A solid state detector for detecting electromagnetic radiation, comprising: (a) a substrate;

(b) a plurality of field effect transistors deposited onto the substrate to form an array;

(c) a planarization layer deposited over the array of field effect transistors; (d) an energy sensitive layer deposited onto the planarization layer;

(e) means for electrically connecting the energy senεitive layer with each field effect tranεiεtor of the array; (f) a top electrode layer deposited onto the energy sensitive layer; and

(g) circuitry means for providing electronic read-out from each field effect transistor of the array.

2. The solid state detector of claim 1, further comprising a phosphor layer depoεited onto the top of the solid εtate detector.

3. The εolid εtate detector of claim 1, further comprising an insulating layer for additional charge storage interposed between the planarization layer and the energy senεitive layer.

4. A εolid εtate detector for detecting electromagnetic radiation, compriεing:

(a) a substrate;

(b) a plurality of thin film, field effect transistorε depoεited onto the εubεtrate and arranged in rowε and columnε to form an array, wherein each transistor has a source electrode, a drain electrode, a gate electrode, and a gate dielectric layer having a gate capacitance;

(c) a plurality of εource lines for linking the source electrodes in each row of transistorε; (d) a plurality of drain lineε for linking the drain electrodes in each column of transistors;

(e) a planarization layer deposited over the array for electrically isolating the source lines from the drain lines;

(f) an energy sensitive layer deposited over the planarization layer, wherein the energy sensitive layer haε an additional capacitance;

(g) meanε for electrically connecting the gate electrode of each field effect tranεiεtor of the array with the energy senεitive layer εuch that the additional capacitance of the energy εenεitive layer iε effectively connected in series with the gate capacitance of each transiεtor of the array; and (h) a top electrode layer depoεited onto the energy εenεitive layer.

5. The εolid εtate detector of claim 4, further comprising an insulating layer for additional charge storage interposed between the planarization layer and the energy sensitive layer.

6. A method of making a solid state detector for detecting electromagnetic energy, comprising the steps of:

(a) depositing a plurality of field effect transistors onto a subεtrate to form an array, wherein each of the field effect tranεiεtorε haε a gate electrode and haε a gate dielectic layer having a gate capacitance;

(b) depoεiting a planarization layer over the array of field effect tranεiεtorε;

(c) depoεiting an energy εenεitive layer onto the .planarization layer, wherein the energy senεitive layer haε an additional capacitance; (d) depoεiting means for electrically connecting the gate electrode of each field effect tranεistor to the energy senεitive layer εuch that the additional capacitance of the energy senεitive layer iε effectively connected in series with the gate capacitance; (e) depositing a top electrode layer onto the energy sensitive layer; and

(f) depositing circuitry means for providing electronic read-out from each field effect transistor of the array.