WO1992001985A1 - Device and method for evaluating exponentials - Google Patents
Device and method for evaluating exponentials Download PDFInfo
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- WO1992001985A1 WO1992001985A1 PCT/US1991/004443 US9104443W WO9201985A1 WO 1992001985 A1 WO1992001985 A1 WO 1992001985A1 US 9104443 W US9104443 W US 9104443W WO 9201985 A1 WO9201985 A1 WO 9201985A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/02—Digital function generators
- G06F1/03—Digital function generators working, at least partly, by table look-up
- G06F1/0307—Logarithmic or exponential functions
Definitions
- This invention is concerned with transcendental function evaluation (TFE). More particularly, this invention is concerned with a method and device for efficient evaluation of exponential functions.
- Volder's utilization of the CORDIC technique sets forth two computing modes, rotation and vectoring, for trigonometric relationship determinations, depending on whether the coordinate components and angular argument of an original vector are given. Using a prescribed tequence of conditional additions or
- Voider implements a CORDIC arithmetic unit to obtain a programmed solution of trigonometric relationships.
- Walther utilizes a hardware fixed point processor to
- Chen's method of computing exponentials essentially cuts the Taylor series to one term and utilizes that term for a series expansion.
- Chen's hardware implementation was formulated to remove multiplication operations and replace them with a single shift-add operation.
- Chen's algorithms require algorithmic iterations to provide an initial approximation to a function, requiring special purpose hardware for efficient implementation. Further improvement in efficiently determining exponential values is needed.
- a method and device for processing an input value to provide an output exponential value of a desired base raised to a power of the input value comprises adjusting the input value to obtain a first scaled value represented by at least one electrical signal, modifying the first scaled value to obtain an approximation value represented by at least one electrical signal, utilizing the
- predetermined base is represented by at least one electrical signal
- second scaled value and the approximation value to generate an error value represented by at least one electrical signal
- a device in accordance with the invention utilizes a first adjuster to adjust the input value to obtain a first scaled value, a modifier to modify the first scaled value to obtain an
- the first function generator includes at least a memory device to determine a first exponential value of the approximation value that has a predetermined base.
- the device further includes an error adjuster to utilize the first scaled value and the approximation value to generate an error value, and to scale the error value relative to a predetermined setting of the memory device, thereby obtaining an adjusted error value.
- the device includes a correction generator to utilize the adjusted error value and a predetermined number of terms of a predetermined mathematical series to determine a correction value, and a combiner to combine the first exponential value of the
- Fig. 1A is a block diagram of a computer hardware
- FIG. 1B and 1C are further detailed block diagrams of certain block diagram components of Fig. 1A.
- Fig. 2A is a general flow chart of an implementation of a method of the invention
- Fig 2B is a further detailed block diagram of one step of Fig. 2A.
- Fig. 3 is a flow chart of an implementation of the method of the invention utilizing natural base logarithms for scaling.
- Fig. 1A illustrates one embodiment (100) of a computer hardware implementation of the invention utilizing a power series correction factor to provide an output exponential value having a desired base raised to a power of an input.
- An input value is provided to a first adjuster (102).
- the first adjuster (102) set forth in more particularity in Fig. 1B (numeral 125), utilizes a second function generator (103) to determine a first logarithm value of the desired base of the output exponential value.
- the first adjuster (102) further utilizes a third function generator (105) to determine a second logarithm value of a predetermined base of a first exponential value, the base of the second logarithm value substantially being the same as the base of the first logarithm value.
- the first adjuster (102) utilizes a first divider (107) to determine a first quotient of the first logarithm value and the second logarithm value, and utilizes a first multiplier (109) to determine a first product value of the input value and the first quotient, such that the first product value is substantially a first scaled value (102).
- a modifier (104) determines an approximation value, utilizing a predetermined set of values that include at least a group of values predetermined by selected rounding algorithms.
- a first function generator (108) utilizes at least a memory device to determine a first exponential value having a predetermined base raised to a power of the approximation value.
- the first function generator scales the approximation value by an implementation dependent constant to obtain a first integral valued index for a memory device.
- the memory device utilizes the first integral valued index to determine a first exponential value having a predetermined base raised to the power of the approximation value. It will be obvious to one skilled in the art that numerous memory devices may be used to determine the first exponential value.
- a typical hardware implementation may directly manipulate bit patterns of the approximation value to obtain a second integral valued index.
- a memory device utilizes the second integral valued index to determine a first exponential value having a predetermined base raised to the power of the approximation value. It will be obvious to one skilled in the art that the first integral valued index obtained from a software implementation may differ from the second integral valued index created in a hardware implementation.
- Fig. 1 C (numeral 150), utilizes a first subtracter (111) to obtain a first difference value of the first scaled value and the
- the error adjuster (106) further utilizes a fourth function generator (113) to determine a third logarithm value, base e, of the predetermined base of the first exponential value.
- the error adjuster (106) further utilizes a second multiplier (115) to determine a second product value of the first difference value and the third logarithm value, the second product value substantially being the adjusted error value.
- predetermined base of the first exponential value is a natural base e, thereby simplifying the determination of the error adjuster (106) by eliminating scaling the error value since the scaling factor of the error adjuster becomes one, and also by simplifying determination of the first scaled value by eliminating
- a base e is selected as the desired base of the output exponential value and as the
- the invention is further simplified by the elimination of the determination of the first seal value since the first quotient becomes one, and by elimination of multiplication by the third logarithm value since the natural base logarithm of the predetermined base of the first exponential value is one.
- the correction generator (110) substantially obtains a correction value by implementing a determiner to utilize the error value together with a predetermined number of terms of a
- predetermined mathematical series for substantially evaluating a predetermined number or terms, and for substantially summing the evaluated predetermined number of terms obtained thereby, obtaining an intermediate sum, the intermediate sum being substantially the correction value.
- mathematical series is a subset of terms from the predetermined mathematical series wherein the number of terms in the subset is greater than or equal to a second quotient of a desired number of h its of accuracy of the output exponential value divided by a
- umber of bits of accuracy of the first function generator means is represented by at least one electrical signal.
- the predetermined mathematical series is
- the determiner substantially sums the evaluated
- a combiner (112) utilizes at least a third multiplier to determine a third product of the first exponential value and the correction value, the third product substantially being the output exponential value of the desired base raised to a power of the input value.
- any base may be selected for the initial determination of logarithms of the desired base and of the
- the predetermined base of the first exponential value for use in the first adjuster (102).
- the invention may be a software program utilizing a memory device, typically a ROM, as a first function generator.
- a high performance digital processing unit (DPU) for a high performance digital processing unit for a high performance digital processing unit (DPU) for a high performance digital processing unit (DPU) for a high performance digital processing unit (DPU) for a high performance digital processing unit (DPU) for a high performance digital processing unit (DPU) for a high performance digital processing unit (DPU) for a high performance digital processing unit (DPU) for
- Fig. 2A generally depicted by the numeral 200, illustrates one embodiment of a method utilizing the present invention.
- An input value is provided, being represented by at least one electrical signal (202).
- a predetermined base (PB) of a first exponential value (FEV) and a predetermined desired base (DB) of an output exponential value (OEV) are preselected as desired.
- predetermined base of the first exponential value is that value selected for a ROM, look-up table, or other memory device utilized for a particular system of implementation of this invention.
- a logarithm value of the predetermined base (PB) of the first exponential value (FEV) (203) and a logarithm value of the desired base (DB) of the output exponential value (OEV) (201) are determined (204), both logarithms being selected to have a same base. Selection of the natural base for both logarithms is a best mode, thereby providing a natural base logarithm of the predetermined base of the first exponential value for utilization in scaling the error value (212).
- the input value is scaled by
- the predetermined set of values is at least a group of values predetermined by selected rounding algorithms (206).
- a memory device is utilized to obtain the exponential value of the predetermined base raised to the power of the approximation value (FEV), thereby determining the first exponential value, that value being represented by at least one electrical signal (208).
- a ROM or a similar memory device is utilized. It is clear that since the FEV is substantially the predetermined base raised to the power of the approximation value, its degree of accuracy (degree to which it represents an exponential value of a desired base raised to a power of the input value) is smaller than a degree of precision of the input value. However, the degree of precision of the FEV (degree of refinement to which the exponential value is computed) must be at least as precise as the desired degree of accuracy of the output exponential value of the desired base.
- an error value being a difference between the first scaled value and the approximation value
- the EV is scaled by the natural logarithm of the predetermined base of the first exponential value, implemented by multiplication of the difference by that natural logarithm, thereby determining an adjusted error value (AEV), represented by at least one electrical signal (212).
- the AEV is utilized in the PMS, and the SV number of the predetermined number of terms of that PMS are summed to substantially obtain a correction value
- CV represented by at least one electrical signal (214):
- the output exponential value (OEV) of the desired base raised to the power of the input value, being represented by at least one electrical signal, is obtained by obtaining a product of FEV and CV (216).
- Fig. 3 generally depicted by the numeral 300, illustrates one implementation of the method of the invention utilizing natural base logarithms for scaling.
- An input value x is provided, being represented by at least one electrical signal (302).
- predetermined base, y of a first exponential value and a predetermined desired base, m, of an output exponential value are preselected as desired.
- a logarithm of the predetermined base cthe first exponential value and a logarithm of the desired base of the output exponential value are determined (304), both logarithms being selected to have a same base. Selection of a natural base for both logarithms is a best mode, thereby also providing a natural base logarithm of the desired base of the output exponential value for utilization in scaling an error value (312).
- An approximation, a, of the first scaled value, mod(x), being represented by at least one electrical signal, is determined by utilizing a selection from a predetermined set of values, wherein the predetermined set of values is at I st a group of values predetermined by selected rounding algorithms (306).
- a memory device is utilized to obtain the first exponential value of the predetermined base raised to the power of the
- y a is represented by at least one electrical signal (308).
- a ROM or a similar memory device is utilized.
- d (mod(x) - a ⁇ (310), and the difference is scaled by the natural logarithm of the predetermined base of the first exponential value, implemented by multiplication of the difference by that natural logarithm, thereby determining an adjusted error value, c, such that
- c (d)(In y), and c is represented by at least one electrical signal (312).
- the adjusted error value, c is utilized in the PMS, and the predetermined number of terms of that PMS are evaluated and summed to substantially obtain a correction value
- the output exponential value being substantially m x , of the desired base raised to the power of the input value, being
- the present invention may be implemented entirely in software. It is further clear to one skilled in the art that the order of the steps may be modified. For example, the EV may be determined prior to obtaining the FEV.
Abstract
There is provided a method and apparatus for processing an input value to provide an output exponential value of a desired base raised to the power of the input value. It comprises a first adjuster (102) for adjusting the input value, a predetermined base of a first exponential value, and the desired base of the output exponential value to obtain a first scaled value, a modifier (104) for modifying to obtain an approximation value, a first function generator for determining the first exponential value of the approximation value, an error adjuster (106) for generating an adjusted error value, the approximation value, and a logarithm of the predetermined base of the first exponential value, a correction generator (110) for determining a correction value for the first exponential value, and a combiner (112) combining the first exponential value with the correction value.
Description
DEVICE AND METHOD FOR EVALUATING EXPONENTIALS
Field of the Invention
This invention is concerned with transcendental function evaluation (TFE). More particularly, this invention is concerned with a method and device for efficient evaluation of exponential functions.
Background of the Invention
The need for efficient TFE arises especially in generating efficient math libraries for RISC (Reduced Instruction Set
Computers) chips, CISC (Complex Instruction Set Computers) chips, digital signal processors (DSPs), and compilers. Present TFE systems typically utilize CORDIC (Coordinate Rotation Digital Computer) computing techniques substantially as set forth by JackE. Voider in The CORDIC Trigonometric Computing Technique. IRE Transactions on Electronic Computers, September, 1959, in A
Unified Algorithm For Elementary Functions, by J.C. Walther, Spring Joint Computer Conference, 1971 , or in Tien Chi Chen's techniques of U.S. Patent No. 3,631,230 (1971).
Volder's utilization of the CORDIC technique sets forth two computing modes, rotation and vectoring, for trigonometric relationship determinations, depending on whether the coordinate components and angular argument of an original vector are given. Using a prescribed tequence of conditional additions or
subtractions, Voider implements a CORDIC arithmetic unit to obtain a programmed solution of trigonometric relationships.
Walther suggests that similar algorithms may be implemented for solution of exponentials by computing hyperbolic sine and
hyperbolic cosine in the CORDIC rotation mode.
Walther utilizes a hardware fixed point processor to
implement unifying algorithms containing CORDIC schemes. While the Walter unifying algorithms have been implemented since 1971 , such algorithms are hampered by a low rate of convergence. Chen's method of computing exponentials essentially cuts the Taylor series to one term and utilizes that term for a series expansion. Chen's hardware implementation was formulated to remove multiplication operations and replace them with a single shift-add
operation. Chen's algorithms require algorithmic iterations to provide an initial approximation to a function, requiring special purpose hardware for efficient implementation. Further improvement in efficiently determining exponential values is needed.
Summary of the Invention
Thus, there is provided a method and device for processing an input value to provide an output exponential value of a desired base raised to a power of the input value. A method in accordance with the invention comprises adjusting the input value to obtain a first scaled value represented by at least one electrical signal, modifying the first scaled value to obtain an approximation value represented by at least one electrical signal, utilizing the
approximation value and a memory device to determine a first exponential value of the approximation value that has a
predetermined base and is represented by at least one electrical signal, and utilizing the first scaled value and the approximation value to generate an error value represented by at least one electrical signal.
It is further characterized by a second scaling, the error value being scaled relative to a predetermined setting of the memory device, to obtain an adjusted error value represented by at least one electrical signal, utilizing the adjusted error value and a predetermined number of terms of a predetermined mathematical series to determine a correction value represented by at least one electrical signal, and combining the first exponential value of the approximation value with the correction value to obtain the output exponential value having the desired base raised to the power of the input and represented by at least one electrical signal.
A device in accordance with the invention utilizes a first adjuster to adjust the input value to obtain a first scaled value, a modifier to modify the first scaled value to obtain an
approximation value and a first function generator to utilize the approximation value. The first function generator includes at least a memory device to determine a first exponential value of the approximation value that has a predetermined base. The device further includes an error adjuster to utilize the first scaled value
and the approximation value to generate an error value, and to scale the error value relative to a predetermined setting of the memory device, thereby obtaining an adjusted error value. Additionally, the device includes a correction generator to utilize the adjusted error value and a predetermined number of terms of a predetermined mathematical series to determine a correction value, and a combiner to combine the first exponential value of the
approximation value with the correction value to obtain the output exponential value having the desired base raised to the power of the input.
Brief Description of the Drawings
Fig. 1A is a block diagram of a computer hardware
implementation of the invention; Fig. 1B and 1C are further detailed block diagrams of certain block diagram components of Fig. 1A.
Fig. 2A is a general flow chart of an implementation of a method of the invention; Fig 2B is a further detailed block diagram of one step of Fig. 2A.
Fig. 3 is a flow chart of an implementation of the method of the invention utilizing natural base logarithms for scaling.
Best Mode For Carrying Out The Invention
Fig. 1A illustrates one embodiment (100) of a computer hardware implementation of the invention utilizing a power series correction factor to provide an output exponential value having a desired base raised to a power of an input. An input value is provided to a first adjuster (102). The first adjuster (102), set forth in more particularity in Fig. 1B (numeral 125), utilizes a second function generator (103) to determine a first logarithm value of the desired base of the output exponential value. The first adjuster (102) further utilizes a third function generator (105) to determine a second logarithm value of a predetermined base of a first exponential value, the base of the second logarithm value substantially being the same as the base of the first logarithm value. Additionally, the first adjuster (102) utilizes a first divider (107) to determine a first quotient of the first logarithm value and the second logarithm value, and utilizes a first multiplier (109) to determine a first product value of the input value and the first
quotient, such that the first product value is substantially a first scaled value (102).
A modifier (104) determines an approximation value, utilizing a predetermined set of values that include at least a group of values predetermined by selected rounding algorithms. A first function generator (108) utilizes at least a memory device to determine a first exponential value having a predetermined base raised to a power of the approximation value. Typically in a software implementation the first function generator scales the approximation value by an implementation dependent constant to obtain a first integral valued index for a memory device. The memory device utilizes the first integral valued index to determine a first exponential value having a predetermined base raised to the power of the approximation value. It will be obvious to one skilled in the art that numerous memory devices may be used to determine the first exponential value.
A typical hardware implementation may directly manipulate bit patterns of the approximation value to obtain a second integral valued index. A memory device utilizes the second integral valued index to determine a first exponential value having a predetermined base raised to the power of the approximation value. It will be obvious to one skilled in the art that the first integral valued index obtained from a software implementation may differ from the second integral valued index created in a hardware implementation.
An error adjuster (106), set forth in more particularity in
Fig. 1 C (numeral 150), utilizes a first subtracter (111) to obtain a first difference value of the first scaled value and the
approximation value. The error adjuster (106) further utilizes a fourth function generator (113) to determine a third logarithm value, base e, of the predetermined base of the first exponential value. The error adjuster (106) further utilizes a second multiplier (115) to determine a second product value of the first difference value and the third logarithm value, the second product value substantially being the adjusted error value.
In one embodiment of the present invention, the
predetermined base of the first exponential value is a natural base e, thereby simplifying the determination of the error adjuster (106) by eliminating scaling the error value since the scaling
factor of the error adjuster becomes one, and also by simplifying determination of the first scaled value by eliminating
determination of a quotient scaling value and simply scaling the input value by multiplication of the input value by the natural base logarithm of the desired output exponential value.
In another embodiment, where a base e is selected as the desired base of the output exponential value and as the
predetermined base of the first exponential value, the invention is further simplified by the elimination of the determination of the first seal value since the first quotient becomes one, and by elimination of multiplication by the third logarithm value since the natural base logarithm of the predetermined base of the first exponential value is one.
The correction generator (110) substantially obtains a correction value by implementing a determiner to utilize the error value together with a predetermined number of terms of a
predetermined mathematical series for substantially evaluating a predetermined number or terms, and for substantially summing the evaluated predetermined number of terms obtained thereby, obtaining an intermediate sum, the intermediate sum being substantially the correction value. The number of the
predetermined number of terms, SV, of the predetermined
mathematical series is a subset of terms from the predetermined mathematical series wherein the number of terms in the subset is greater than or equal to a second quotient of a desired number of h its of accuracy of the output exponential value divided by a
umber of bits of accuracy of the first function generator means and is represented by at least one electrical signal. For example, where 24 bits of accuracy are desired and the first function generator (108) determines a first exponential value of the input value x to eight bits of accuracy, 24/8 = 3, and SV is typically selected as 3. The predetermined mathematical series is
substantially a power series of the form, where c - the adjusted error value.
The determiner substantially sums the evaluated
predetermined number of terms of the predetermined mathematical
series to yield a first sum, substantially being the correction where c = the adjusted error value and SV = the
number of the predetermined number of terms.
A combiner (112) utilizes at least a third multiplier to determine a third product of the first exponential value and the correction value, the third product substantially being the output exponential value of the desired base raised to a power of the input value.
In the best mode of implementing the present invention, it is desirable to select a natural base first logarithm, being the first logarithm value, and being the logarithm of the desired base of the output exponential value, such that the second logarithm value is also determined having a natural base. This procedure provides the natural base logarithm of the predetermined base of the first exponential value such that said value may be utilized in
determining the adjusted error value. It will be obvious to one skilled in the art that any base may be selected for the initial determination of logarithms of the desired base and of the
predetermined base of the first exponential value for use in the first adjuster (102). However, it is more efficient to determine a natural base logarithm of both of the above cited logarithms, such that the natural base logarithm of the predetermined base of the first exponential value determined thereby may be further utilized in determining the adjusted error value.
In one embodiment, the invention may be a software program utilizing a memory device, typically a ROM, as a first function generator.
A high performance digital processing unit (DPU) for
determining an output exponential value of a desired base raised to a power of an input value is described, in the manner of the abovedescribed device, utilizing the computer hardware described above, wherein the combiner is substantially a multiplier for multiplying the first exponential value and the correction value, thereby substantially obtaining the output exponential value having the desired base raised to the power of the input value.
Fig. 2A, generally depicted by the numeral 200, illustrates one embodiment of a method utilizing the present invention. An input value is provided, being represented by at least one electrical signal (202). A predetermined base (PB) of a first exponential value (FEV) and a predetermined desired base (DB) of an output exponential value (OEV) are preselected as desired. The
predetermined base of the first exponential value is that value selected for a ROM, look-up table, or other memory device utilized for a particular system of implementation of this invention.
As set forth more particularly in Fig. 2B (numeral 225) and shown generally in Fig. 2A, a logarithm value of the predetermined base (PB) of the first exponential value (FEV) (203) and a logarithm value of the desired base (DB) of the output exponential value (OEV) (201) are determined (204), both logarithms being selected to have a same base. Selection of the natural base for both logarithms is a best mode, thereby providing a natural base logarithm of the predetermined base of the first exponential value for utilization in scaling the error value (212). The input value is scaled by
multiplying (207) the input value times the quotient (205) of the logarithm of the desired base of the output exponential value divided by the logarithm of the predetermined base of the first exponential value to substantially provide a first scaled value {mod(x)} that is represented by at least one electrical signal (204).
An approximation of the first scaled value, a, being
represented by at least one electrical signal, is determined by utilizing a selection from a predetermined set of values, wherein the predetermined set of values is at least a group of values predetermined by selected rounding algorithms (206).
A memory device is utilized to obtain the exponential value of the predetermined base raised to the power of the approximation value (FEV), thereby determining the first exponential value, that value being represented by at least one electrical signal (208).
Typically, a ROM or a similar memory device is utilized. It is clear that since the FEV is substantially the predetermined base raised to the power of the approximation value, its degree of accuracy (degree to which it represents an exponential value of a desired base raised to a power of the input value) is smaller than a degree of precision of the input value. However, the degree of precision of
the FEV (degree of refinement to which the exponential value is computed) must be at least as precise as the desired degree of accuracy of the output exponential value of the desired base.
Upon determining the first scaled value and an approximation value, an error value (EV), being a difference between the first scaled value and the approximation value, is determined (210), and the EV is scaled by the natural logarithm of the predetermined base of the first exponential value, implemented by multiplication of the difference by that natural logarithm, thereby determining an adjusted error value (AEV), represented by at least one electrical signal (212).
A selected value (SV), being a number of a predetermined number of terms of a predetermined mathematical series (PMS) of a form: where c = the adjusted error value,
is determined by obtaining a quotient of a desired number of bits of accuracy of the output exponential value and a number of bits of accuracy of the first exponential value, and utilizing a selected value greater than or equal to that quotient. The AEV is utilized in the PMS, and the SV number of the predetermined number of terms of that PMS are summed to substantially obtain a correction value,
CV, represented by at least one electrical signal (214):
, where c = the adjusted error value and SV = the predetermined number of terms.
The output exponential value (OEV) of the desired base raised to the power of the input value, being represented by at least one electrical signal, is obtained by obtaining a product of FEV and CV (216).
Fig. 3, generally depicted by the numeral 300, illustrates one implementation of the method of the invention utilizing natural base logarithms for scaling. An input value x is provided, being represented by at least one electrical signal (302). A
predetermined base, y, of a first exponential value and a
predetermined desired base, m, of an output exponential value are preselected as desired. A logarithm of the predetermined base cthe first exponential value and a logarithm of the desired base of the output exponential value are determined (304), both logarithms being selected to have a same base. Selection of a natural base for both logarithms is a best mode, thereby also providing a natural base logarithm of the desired base of the output exponential value for utilization in scaling an error value (312). The input value is scaled by multiplying the input value times a quotient of the logarithm of the desired base of the output exponential value divided by the logarithm of the predetermined base of the first exponential value to substantially provide a first scaled value, x(In m/In y) = mod(x), that is represented by at least one electrical signal (304).
An approximation, a, of the first scaled value, mod(x), being represented by at least one electrical signal, is determined by utilizing a selection from a predetermined set of values, wherein the predetermined set of values is at I st a group of values predetermined by selected rounding algorithms (306).
A memory device is utilized to obtain the first exponential value of the predetermined base raised to the power of the
approximation value, ya, such that ya is represented by at least one electrical signal (308). Typically, a ROM or a similar memory device is utilized.
Upon determining the first scaled value and an approximation value, a difference between the first scaled value and the
approximation value is determined, d = (mod(x) - a} (310), and the difference is scaled by the natural logarithm of the predetermined base of the first exponential value, implemented by multiplication of the difference by that natural logarithm, thereby determining an adjusted error value, c, such that
c = (d)(In y), and c is represented by at least one electrical signal (312).
A selected value (SV), being a number of a predetermined number of terms of a predetermined mathematical series (PMS) of a form:
where c = the adjusted error value,
is determined by obtaining a quotient of a desired number of bits of accuracy of the output exponential value and a number of bits of accuracy of the first exponential value, and utilizing a selected value greater than or equal to that quotient. The adjusted error value, c, is utilized in the PMS, and the predetermined number of terms of that PMS are evaluated and summed to substantially obtain a correction value,
where c = the adjusted error value and SV = number of
predetermined number of terms, the correction value being
represented by at least one electrical signal (314).
The output exponential value, being substantially mx, of the desired base raised to the power of the input value, being
represented by at least one electrical signal, is obtained by determining a product of ya and CV (316). It is clear that for the special case of m=y=e, mod(x) = x, c = x - a, and mx = ex, allowing elimination of the steps of adjusting the input value to obtain a first scaled value and of scaling the error value to obtain an adjusted error value.
It is clear that, in a selected embodiment, the present invention may be implemented entirely in software. It is further clear to one skilled in the art that the order of the steps may be modified. For example, the EV may be determined prior to obtaining the FEV.
I claim:
Claims
1. A device for processing an input value to provide an output exponential value of a desired base raised to a power of the input value, comprising:
A) first adjusting means responsive to the input value, a predetermined base of a first exponential value, and the desired base for substantially obtaining a first scaled value;
B) modification means responsive to the first scaled value for generating an approximation value, the approximation value being selected from a predetermined set of values that is at least a group of values predetermined by selected rounding algorithms;
C) first function generator means responsive to the modification means for determining the first exponential value having the predetermined base, the first function generator means utilizing at least one memory device to determine a first
exponential value having a predetermined base raised to a power -of the approximation value;
D) error adjuster means responsive to the first adjusting means and the modification means for generating an adjusted error value;
E) correction generator means responsive to the error adjuster means for determining a correction value; and
F) combining means responsive to the first function generator means and the correction generator means for
substantially obtaining the output exponential value such that the desired base is raised to the power of the input value at least determines a third product, the third product being substantially the output exponential value o; the desired base raised to a power of the input value.
2. The device of claim 1 , wherein the first adjusting means includes at least:
A) second function generator means responsive to the desired base of the output exponential value for determining a first logarithm value, substantially being a logarithm of the desired base of the output exponential value;
B) third function generator means responsive to the first function generator means for determining a second logarithm value, being substantially a logarithm of the predetermined base of the first exponential value wherein the base of the second logarithm value is substantially the same as the base of the first logarithm value;
C) first division means responsive to the second function generator means and the third function generator means for determining a first quotient of the first logarithm value and the second logarithm value; and
D) first multiplication means responsive to the input value and the first division means for determining a first product value of the input value and the first quotient, such that the first product value is substantially the first scaled value.
3. The device of claim 1 , wherein the error adjuster means further includes at least:
A) first subtraction means responsive to the first
adjusting means and the modification means for obtaining a first difference value of the first scaled value and the approximation value;
B) fourth function generator means responsive to the predetermined base of the first exponential value for determining a third logarithm value, the logarithm value being substantially a natural base logarithm of the predetermined base of the first exponential value; and
C) second multiplication means responsive to the first subtraction means and the fourth function generator means for determining a second product value of the first difference value and the third logarithm value, the second product value
substantially being the adjusted error value.
4. The device of claim 1 , wherein the correction generator means further includes: determining means, responsive to the error adjuster means for utilizing the error value together with a predetermined number of terms of a predetermined mathematical series to
substantially evaluate a predetermined number of terms, and for substantially summing the evaluated predetermined number of terms obtained thereby, obtaining an intermediate sum, the intermediate sum being substantially the correction value, wherein the predetermined number of terms is a subset of terms from the predetermined mathematical series and wherein the number of terms in the subset is greater than or equal to a second quotient of a desired number of bits of accuracy of the output exponential value divided by a number of bits of accuracy of the first function generator means and is represented by at least one electrical signal, and the predetermined mathematical series is substantially a power series substantially of a form: 
where c - the adjusted error value.
5. A high performance digital processing unit (DPU) for determining an output exponential value of a desired base raised to a power of an input value, comprising:
A) first adjusting means responsive to the input value, a predetermined base of a first exponential value, and the desired base for substantially obtaining a first scaled value;
B) modification means responsive to the first scaled value for generating an approximation value, wherein the approximation value is selected from a predetermined set of values that is at least a group of values predetermined by selected rounding algorithms;
C) first function generator means responsive to the modification means for determining a first exponential value having a predetermined base, wherein the first function generator means utilizes at least one memory device to determine a first exponential value having a predetermined base raised to a power of the approximation value;
D) error adjuster means responsive to the first adjusting means and the modification means for generating an adjusted error value, wherein the error adjuster means includes at least:
1) first subtraction means responsive to the first adjusting means and the modification means for obtaining a first difference value of the first scaled value and the approximation value;
2) fourth function generator means responsive to the predetermined base of the first exponential value for determining a third logarithm value, the logarithm value being substantially a natural base logarithm, of the predetermined base of the first exponential value; and
3) second multiplication means responsive to the first subtraction means and the fourth function generator means for determining a second product value of the first difference value and the third logarithm value, the second product value
substantially being the adjusted error value;
E) correction generator means responsive to the error adjuster means for determining a correction value;
F) combining means including multiplication means responsive to the first function generator means and the correction generator means for substantially obtaining a first product of the first exponential value and the correction value, thereby
substantially obtaining the output exponential value such that the desired base is raised to the power of the input value.
6. The DPU of claim 5, wherein the first adjusting means includes at least:
A) second function generator means responsive to the desired base of the output exponential value for determining a first logarithm value, substantially being a logarithm of the desired base of the output exponential value;
B) third function generator means responsive to the first function generator means for determining a second logarithm value, being substantially a logarithm of the predetermined base of the first exponential value, wherein the base of the second
logarithm value is substantially the same as the base of the first logarithm value;
C) first division means responsive to the second function generator means and the third function generator means for determining a first quotient of the first logarithm value and the second logarithm value; and
D) first multiplication means responsive to the input value and the first division means for determining a first product value of the input value and the first quotient, such that the first product value is substantially the first scaled value.
7. The DPU of claim 5, wherein the correction generator means further includes:
determining means, responsive to the error adjuster means for utilizing the error value together with a predetermined number of terms of a predetermined mathematical series to
substantially evaluate a predetermined number of terms, and for substantially summing the evaluated predetermined number of terms obtained thereby, obtaining an intermediate sum, the
intermediate sum being substantially the correction value, wherein the predetermined number of terms of the predetermined
mathematical series is a subset of terms from the predetermined mathematical series and wherein the number of terms in the subset is equal to a second quotient of a desired number of bits of
accuracy of the output exponential value divided by a number of bits of accuracy of the first function generator means and is represented by at least one electrical signal and the predetermined mathematical series is substantially a power series that is substantially of a form: J 
where c - the adjusted error value.
8. A device for processing an input value, x, to provide an output exponential value, mx, of a desired base, m, raised to a power of the input value and having the desired degree of accuracy,
comprising:
A) first adjusting means responsive to the input value, a predetermined base of a first exponential value, and the desired base for substantially obtaining a first scaled value, wherein the first adjusting means includes at least:
1 ) second function generator means responsive to the desired base of the output exponential value for determining a first natural logarithm value of the desired base of the output exponential value, substantially In m ;
2) third function generator means responsive to the first function generator means for determining a second natural logarithm value of the predetermined base, of the first exponentialvalue, substantially In y;
3) first division means responsive to the second function generator means and the third function generator means for determining a first quotient of the first natural logarithm value and the second natural logarithm value, substantially
(In m)/(In y); and
4) first multiplication means responsive to the input value and the first division means for determining a first product value of the input value and the first quotient, such that the first product value is substantially the first scaled value, substantially mod(x) = {(x)(In m)/(In y)};
B) modification means responsive to the first scaled value, x', for generating an approximation value, a, wherein the approximation value is selected from a predetermined set of values that is at least group of values predetermined by selected rounding algorithm values;
C) first function generator means responsive to the modification means for utilizing at least one memory device to determine a first exponential value, ya, having a predetermined base, y, raised to a power of the approximation value, a, and substantially having a predetermined degree of accuracy and a predetermined degree of precision, and wherein the predetermined degree of precision is greater than or equal to the desired degree of accuracy of the output exponential value and the predetermined degree accuracy is less than the desired degree of accuracy of the output exponential ;
D) error adjuster means responsive to the first adjusting means and the modification means for generating an adjusted error value, c, wherein the error adjuster means includes at least:
1) first subtraction means responsive to the first adjusting means and the modification means for obtaining a first difference value of the first scaled value and the approximation value, substantially {mod(x) - a}; and
2) second multiplication means responsive to the first subtraction means and the first function generator means for determining a second product value, the second value substantially being the adjusted error value, substantially
c = {mod(x) - a}{In y};
E) correction generator means responsive to the error generator means for determining a correction value; and
F) combining means responsive to the first function generator means and the correction generator means for obtaining the output exponential value, substantially mx, such that the desired base, m, is raised to the power of the input value, x, and has the desired degree of accuracy.
9. The device of claim 8, wherein the correction generator means further includes:
determining means, responsive to the error adjuster means for utilizing the error value together with a predetermined number of terms of a predetermined mathematical series to
substantially evaluate a predetermined number of terms, and for substantially summing the evaluated predetermined number of terms obtained thereby, obtaining an intermediate sum, the intermediate sum being substantially the correction value and wherein the predetermined number of terms of the predetermined mathematical series is a subset of terms from the predetermined mathematical series and wherein the number of terms in the subset is greater than or equal to a second quotient of a desired number of bits of accuracy of the output exponential value divided by a number of bits of accuracy of the first function generator meansand is represented by at least one electrical signal, such that the predetermined mathematical series is substantially of a form: 
where c = the adjusted error value.
10. The device of claim 8, wherein the determining means includes at least evaluation means for evaluating the
predetermined number of terms of the predetermined mathematical series such that the number of the predetermined number of terms is SV, and first addition means for substantially summing the evaluated predetermined number of terms of the predetermined mathematical series to obtain a first sum, the first sum where c = 
the adjusted error value and SV = number of the predetermined number of terms and wherein the combining means further includes at least:
multiplication means responsive to the first function
generator means and the correction generator means for
substantially obtaining a first product of the first exponential value and the correction value, thereby substantially obtaining the output exponential value, mx, such that the desired base is raised to the power of the input value.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP91513622A JPH05508724A (en) | 1990-07-19 | 1991-06-24 | Apparatus and method for calculating exponential functions |
| KR93700172A KR970002393B1 (en) | 1990-07-19 | 1993-01-19 | Device for evaluating exponentials |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US555,325 | 1990-07-19 | ||
| US07/555,325 US5177702A (en) | 1990-07-19 | 1990-07-19 | Device and method for evaluating exponentials |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO1992001985A1 true WO1992001985A1 (en) | 1992-02-06 |
Family
ID=24216841
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US1991/004443 WO1992001985A1 (en) | 1990-07-19 | 1991-06-24 | Device and method for evaluating exponentials |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US5177702A (en) |
| JP (1) | JPH05508724A (en) |
| KR (1) | KR970002393B1 (en) |
| CA (1) | CA2085228A1 (en) |
| WO (1) | WO1992001985A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19681213T1 (en) * | 1995-03-10 | 1998-02-26 | Motorola Inc | Exponentiation circuit using a shifter and method for using it |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6049343A (en) * | 1997-01-20 | 2000-04-11 | Hitachi, Ltd. | Graphics processing unit and graphics processing system |
| JPH10283340A (en) * | 1997-04-10 | 1998-10-23 | Mitsubishi Electric Corp | Arithmetic processor |
| US5912830A (en) * | 1997-04-30 | 1999-06-15 | Hewlett-Packard Co. | System and method for conditionally calculating exponential values in a geometry accelerator |
| US5926406A (en) * | 1997-04-30 | 1999-07-20 | Hewlett-Packard, Co. | System and method for calculating floating point exponential values in a geometry accelerator |
| US5935200A (en) * | 1997-11-21 | 1999-08-10 | Unisys Corporation | Exponential functional relationship generator method and system for implementation in digital logic |
| US6304890B1 (en) * | 1998-02-04 | 2001-10-16 | Matsushita Electric Industrial Co., Ltd. | Exponential calculation device and decoding device |
| US6304889B1 (en) * | 1998-11-18 | 2001-10-16 | International Business Machines Corporation | Exponential optimization |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4158889A (en) * | 1977-02-08 | 1979-06-19 | Nippon Electric Co., Ltd. | Calculator for calculating ax with the base a of any positive number by calculating common logarithm of a |
| US4225933A (en) * | 1977-11-19 | 1980-09-30 | Nippon Electric Co., Ltd. | Exponential function computing apparatus |
| US4410956A (en) * | 1980-04-15 | 1983-10-18 | Casio Computer Co., Ltd. | Exponential operation device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3631230A (en) * | 1970-09-24 | 1971-12-28 | Ibm | Binary arithmetic unit implementing a multiplicative steration for the exponential, logarithm, quotient and square root functions |
-
1990
- 1990-07-19 US US07/555,325 patent/US5177702A/en not_active Expired - Fee Related
-
1991
- 1991-06-24 JP JP91513622A patent/JPH05508724A/en active Pending
- 1991-06-24 WO PCT/US1991/004443 patent/WO1992001985A1/en active Application Filing
- 1991-06-24 CA CA002085228A patent/CA2085228A1/en not_active Abandoned
-
1993
- 1993-01-19 KR KR93700172A patent/KR970002393B1/en not_active IP Right Cessation
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4158889A (en) * | 1977-02-08 | 1979-06-19 | Nippon Electric Co., Ltd. | Calculator for calculating ax with the base a of any positive number by calculating common logarithm of a |
| US4225933A (en) * | 1977-11-19 | 1980-09-30 | Nippon Electric Co., Ltd. | Exponential function computing apparatus |
| US4410956A (en) * | 1980-04-15 | 1983-10-18 | Casio Computer Co., Ltd. | Exponential operation device |
Non-Patent Citations (1)
| Title |
|---|
| IBM TECHNICAL DISCLOSURE BULLETIN, Volume 14, Number 1, Published June 1971, T.C. CHEN, "Efficient Arithmetic Apparatus and Method", pages 328-330. * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19681213T1 (en) * | 1995-03-10 | 1998-02-26 | Motorola Inc | Exponentiation circuit using a shifter and method for using it |
Also Published As
| Publication number | Publication date |
|---|---|
| CA2085228A1 (en) | 1992-01-20 |
| JPH05508724A (en) | 1993-12-02 |
| KR970002393B1 (en) | 1997-03-05 |
| US5177702A (en) | 1993-01-05 |
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