WO1991015874A1 - Cold cathode field emission device having integral control or controlled non-fed devices - Google Patents

Cold cathode field emission device having integral control or controlled non-fed devices Download PDF

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Publication number
WO1991015874A1
WO1991015874A1 PCT/US1991/002025 US9102025W WO9115874A1 WO 1991015874 A1 WO1991015874 A1 WO 1991015874A1 US 9102025 W US9102025 W US 9102025W WO 9115874 A1 WO9115874 A1 WO 9115874A1
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WIPO (PCT)
Prior art keywords
fed
gate
bipolar transistor
fet
emitter
Prior art date
Application number
PCT/US1991/002025
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French (fr)
Inventor
Robert C. Kane
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Motorola, Inc.
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Publication of WO1991015874A1 publication Critical patent/WO1991015874A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors

Definitions

  • This invention relates generally to cold cathode field emission devices.
  • Solid state cold cathode field emission devices are known. In such devices, electron emission occurs in conjunction with a cold cathode. There are significant anticipated advantages to this technology. The prior art also teaches that such cold cathode field emission devices can be configured in an integral array with one another to support, for example, anticipated current carrying capacity requirements. A number of problems remain in deriving successful use of such devices. According to one such problem, non-integral control of the FEDs must be provided, and/or the FEDs must control non-integral controlled devices.
  • an electronic device can be provided that is comprised of a cold cathode field emission device and a non-field emission active device that is formed integrally with the cold cathode field emission device, such that the cold cathode field emission device and the non-field emission active device are operably coupled to one another.
  • the non-field emission active device can be a bipolar transistor.
  • the non-field emission active device can be a field effect transistor.
  • the FED can be configured to control the non-FED.
  • the FED can be configured to be controlled by the non-FED.
  • the non- FED can be formed in varying layers that comprise the FED, including the substrate wafer itself.
  • Various embodiments of FEDs can be configured in conjunction with such non-FEDs, including planar structures (wherein the various electrodes that comprise the FED are disposed substantially planar to one another), non- planar FEDs (wherein, for example, the electrodes that comprise the FED are disposed in a substantially non- planar manner to one another, and where the emitter often assumes the form of a cone), and inverted FED structures (where, for example, the emitter is not formed on the substrate wafer itself).
  • the teachings of this invention are applicable in a wide variety of applications, including stand alone devices, integrated device arrays, and flat screen displays, to name a few.
  • at least certain layers of the FED can be comprised of amorphous or polysilicon semiconductor materials, and the non-FED device can be formed therein. Such materials can also be utilized to serve as an electrode within the FED itself.
  • the benefits afforded by the various embodiments of this invention include onboard low power control of an array of current sources, low power high speed parallel switching of devices, devices that are comprised of merged technologies wherein the attributes of each technology can be exploited as appropriate to a particular application, and onboard matrix addressing of fiat panel displays.
  • Fig. 1A comprises a schematic representation of a bipolar transistor configured to control the gate of an FED
  • Figs. 1 B-I comprise side elevational sectioned views of alternative embodiments of realizing the circuit depicted in Fig. 1 A;
  • Fig. 2A comprises a schematic representation of a field effect transistor configured to control the gate of an FED
  • Figs. 2B-H comprise side elevational sectioned views of alternative embodiments of realizing the circuit depicted in Fig. 2A;
  • Fig. 3A comprises a schematic representation of a bipolar transistor coupled to the emitter of an FED;
  • Figs. 3B-D comprise side elevational sectioned views of alternative embodiments of realizing the circuit depicted in Fig. 3A;
  • Fig. 4A comprises a schematic representation of a field effect transistor coupled to the emitter of an FED;
  • Figs. 4B-D comprise side elevational sectioned views of alternative embodiments of realizing the circuit depicted in Fig. 4A;
  • Fig. 5 comprises a schematic representation of a plurality of bipolar transistors configured to control a plurality of FEDs;
  • Fig. 6 comprises a schematic representation of a plurality of field effect transistors configured to control a plurality of FEDs
  • Fig. 7A comprises a schematic representation of an FED coupled to the base of a bipolar transistor
  • Figs. 7B-D comprise side elevational sectioned views of alternative embodiments of realizing the circuit depicted in Fig. 7A;
  • Fig. 8A comprises a schematic representation of an FED coupled to the emitter of a bipolar transistor
  • Figs. 8B-C comprise side elevational sectioned views of alternative embodiments of realizing the circuit depicted in Fig. 8A;
  • Fig. 9A comprises a schematic representation of an FED coupled to the gate of a field effect transistor
  • Figs. 9B-C comprise side elevational sectioned views of alternative embodiments of realizing the circuit depicted in Fig. 9A;
  • Fig. 10A comprises a schematic representation of an FED coupled to the source of a field effect transistor
  • Figs. 10B-D comprise side elevational sectioned views of alternative embodiments of realizing the circuit depicted in Fig. 10A;
  • Fig. 11A comprises a schematic depiction of an FED coupled to the bases of a plurality of bipolar transistors ;
  • Fig. 11 B comprises a schematic depiction of an FED coupled to the emitters of a plurality of bipolar transistors ;
  • Fig. 12A comprises a schematic depiction of an
  • FED coupled to the gates of a plurality of field effect transistors ;
  • Fig. 12B comprises a schematic depiction of an FED coupled to the sources of a plurality of field effect transistors. Best Mode For Carrying Out The Invention
  • Fig. 1A presents a schematic depiction (100) of a bipolar transistor (101 ) that couples, via its collector (102) to the gate (103) of a field emission device (104).
  • Other leads depicted can be coupled as appropriate to accommodate a particular application.
  • the collector (102) could also couple to an appropriate source (106) in accordance with well understood methodology. So configured, the bipolar transistor (101 ) can effectively control the gate modulation of the FED (104).
  • Fig. 1 B depicts a first embodiment (100 1 ) for realizing the schematic representation depicted in Fig. 1A.
  • the FED (104) comprises a non-planar structure having a cone emitter (107) formed on (and/or in) a semiconductor substrate (108), such as, for example, a silicon wafer. Deposited atop subsequent insulating layers (109) is the gate (103). Both the emitter (107) and the gate (103) may be comprised of metal or semiconductor material. The details of forming such a device are understood in the art, and hence will not be presented here. Also, though not depicted in this figure for the sake of simplicity, the FED (104) may also include an anode electrode as well.
  • the bipolar transistor (101) has been formed in the substrate material (108).
  • the bipolar transistor (101 ) includes a collector (102), a base (111 ), and an emitter (112).
  • the collector (102) couples to the gate (103) of the FED (104) via the formed conductive path (113).
  • other metallization depositions (114 and 116) can be deposited to provide appropriate conductive paths to and from the emitter (112) and the base (111). So configured, the bipolar transistor (101) and the FED (104) are integrally formed in and on the same substrate (108) using known semiconductor material processing methodologies.
  • Fig. 1 C depicts a second embodiment (100 2 ) of a bipolar transistor having a collector that couples to the gate of an FED.
  • the bipolar transistor (101) is formed within a semiconductor wafer (108) and includes a collector (102), a base (111 ), and an emitter (112).
  • Metal depositions (114 and 116) provide conductive access to the emitter and base (112 and 116, respectively).
  • the FED (104) has a substantially planar geometry, such as that proposed in U.S. Patent No. 4,827,177 to Lee et al. and in U.S. Serial No. 07/330,050, filed on March 29, 1989, to Kane et al., both of which references are incorporated herein.
  • the particular specific configuration for the FED (104) is not critical, provided, that the gate includes a conductive path (1 17) that conductively couples the gate (103) to the collector (102) of the bipolar transistor (101).
  • the FED (104) includes generally a gate (103) that functions to modulate electron emission from the emitter (118), the latter being formed atop an insulating layer (119).
  • the device would also likely include an anode, which Fig. 1 C does not depict for purposes of simplicity.
  • Fig. 1 D depicts a third embodiment (100 3 ) of this bipolar-to-FED configuration.
  • the FED (104) comprises an anode metallization layer (122) formed on a support substrate (121) that may, or may not, comprise a semiconductor material.
  • An insulating layer (123) separates the anode (122) from the gate (103).
  • the gate (103) can be comprised of a semiconductor material in order to support construction of the bipolar transistor (101), as described below in more detail.
  • Another layer of insulation (124) separates the gate layer (103) from the emitter (126).
  • the FED (104) would typically be encapsulated in order to ensure vacuum conditions most supportive of the desired electron emission activity.
  • the gate layer (103) itself functions as the collector (102) for the bipolar transistor (101). Hence, the collector (102) and the gate (103) are integrally combined.
  • Fig. 1 E depicts a fourth embodiment (100 4 ) of this bipolar collector to FED gate configuration.
  • the bipolar transistor (101 ) is again formed within the gate layer (103) as described above with respect to Fig. 1 D, such that the collector (102) of the bipolar transistor (101 ) and the gate (103) of the FED (104) are again comprised of shared material.
  • the FED (104) comprises a non- planar FED having a cone shaped emitter (127), as versus the inverted structure depicted in Fig. 1 D.
  • the cone shaped emitter (127) resides on either a metallization layer (not shown) which resides on the substrate layer (121) or may reside directly on the substrate layer (121) as depicted.
  • An insulating layer (128) separates the gate (103) from the metallization layer (132) or substrate layer (121).
  • a second insulation layer (129) then separates the gate (103) and the emitter (127) from the anode (131). Additional details regarding the construction of an
  • FED having such a cone shaped emitter can be found in, for example, U.S. Patent No. 4,721 ,885 to Brodie and in
  • Fig. 1 F depicts a fifth embodiment (100 5 ) of a bipolar collector to FED gate configuration.
  • the FED (104) has a non-planar configuration as described above in Fig. 1 E, with the exception that, in this depiction, the anode has not been shown for purposes of simplicity.
  • the bipolar transistor (101 ) has been formed in a layer of amorphous silicon (or polysilicon) semiconductor material (134) that itself has been deposited atop a bifurcated layer that includes the FED gate (103) and an insulating material (133).
  • the amorphous silicon (134) comprises the collector (102) of the bipolar transistor (101).
  • This amorphous silicon layer (134) contacts the gate layer (103) of the FED (104). Therefore, again, the collector (102) of the bipolar transistor (101) integrally couples to the gate (103) of the FED (104).
  • Fig. 1 G depicts a sixth embodiment (100 6 ) of the bipolar collector to FED gate configuration.
  • the FED (104) has the same architecture as the FED depicted in Fig. 1 F.
  • the gate layer (103) is comprised of amorphous silicon (or polysilicon) semiconductor material.
  • the bipolar transistor (101) is otherwise constructed as described above, with the collector (102) of the bipolar transistor (101) again sharing common material with the gate (103) of the FED (104).
  • Fig. 1 H depicts a seventh embodiment (100 7 ) of the bipolar collector to FED gate configuration.
  • the FED (104) comprises an inverted emitter structure such as that described above with respect to Fig. 1 D.
  • the bipolar transistor (101) has been formed in a layer of amorphous silicon (or polysilicon) semiconductor material (134) that has been deposited substantially coplanar to the emitter (126) of the FED (104).
  • An appropriate metallization deposition (136) couples the amorphous material (134), and hence the collector (102) of the bipolar transistor (101) to the gate (103) of the FED (104).
  • This particular embodiment has the advantage of presenting the electrodes (114 and 116) of the bipolar transistor (101 ) substantially external to at least preceding layers. This may facilitate coupling to these electrodes (114 and 116) pursuant to a particular application.
  • Fig. 11 depicts an eighth embodiment (100 8 ) of a bipolar collector to FED gate configuration.
  • the FED (104) comprises a non- planar FED having a cone shaped emitter as described above with respect to Fig. 1 E.
  • the bipolar transistor (101) can be comprised as described above with respect to Fig. 1 H, such that the collector (102) of the bipolar transistor (101 ) couples through an appropriate metallization layer (136) to the gate (103) of the FED (104).
  • Fig. 2A provides a schematic representation (200) of a field effect transistor (FET) (201 ) that couples via one of its electrodes (202) to the gate (103) of an FED (104).
  • the FET electrode (202) may be either the source or the drain, as described below in more detail.
  • This configuration provides the same control capabilities as described above with respect to Fig. 1A, albeit through use of FET technology as versus bipolar technology.
  • Fig. 2B depicts a first embodiment (200 1 ) of an FET electrode to FED gate configuration.
  • the FED (104) can be configured as described above with reference to Fig. 1 B.
  • the semiconductor substrate (108) has formed therein, through known methodologies, an FET drain
  • An FET gate (204) can be formed through deposition of metallic material (205) atop an insulator (206) in known manner.
  • a metallic conductor (207) can be deposited atop the source (203), and successive metallic depositions (208) can link the drain
  • Fig. 2C depicts a second embodiment (200 2 ) of the FET electrode to FED gate configuration.
  • the FED (104) comprises a substantially planar structure as described above in Fig. 1 C.
  • the semiconductor substrate (108) has formed therein the drain (202) and source
  • An appropriate gate (204) can be formed by deposition of an insulating layer (206) and contact (205) metallization.
  • the drain (202) and FED gate (103) are coupled to one another via an extension (117) of the gate (103).
  • Fig. 2D depicts a third embodiment (200 3 ) of the FET electrode to FED gate configuration.
  • the FED (104) may be configured as an inverted structure as described above with respect to Fig. 1 D.
  • the gate layer (103) for the FED (104) has been bifurcated, to include a semiconductor layer (209), within which the source (203) and drain (202) of the FET (201) can be formed.
  • the FET gate (204) can be realized by a conductor (205) deposited atop the insulating layer (206) as before; in a similar manner, the source (203) can have a metallization layer (207) deposited thereon to provide a conductive path thereto.
  • Fig. 2E depicts a fourth embodiment (200 4 ) of the FET electrode to FED gate configuration.
  • the FED (104) may be a substantially non- planar device having a cone shaped emitter (127) as described above with reference to Fig. 1 E (in this embodiment, a metallization layer (132) is depicted).
  • the FET (201) can be as described above with reference to Fig. 2D, such that the drain (202) of the FET (201) couples to the FED gate (103) via an appropriate conductive path (208).
  • Fig. 2F depicts a fifth embodiment (200 5 ) of the FET electrode to FED gate configuration.
  • the FED (104) may be as described above with reference to Fig. 1 F.
  • the FET (201 ) may be formed in a layer of amorphous or polysilicon semiconductor material (134), also as described above in Fig. 1 F.
  • the drain (202) couples to the FED gate (103) by direct contact.
  • Fig. 2G depicts a sixth embodiment (200 6 ) of realizing the FET electrode to FED gate configuration.
  • the FED (104) can be configured as described above with reference to Fig. 1 F.
  • the FET (201) can be configured as described above with reference to Fig. 2E, with the exception that the source (203) and drain (202) are formed in a layer of amorphous silicon (or polysilicon) semiconductor material (211 ).
  • Fig. 2H depicts a seventh embodiment (200 7 ) for the FET electrode to FED gate configuration.
  • the FED (104) may be an inverted structure as described above with reference to Fig. 1 H.
  • the FET (201) is formed in an amorphous silicon (or polysilicon) semiconductor material layer (134) as described above with reference again to Fig. 1 H.
  • Both the source (203) and the drain (202) are formed in the amorphous layer (134).
  • the drain (202) couples to the gate (103) of the FED (104) via an appropriate metallization path (136).
  • Fig. 3A depicts a schematic representation (300) of an FED (104) and a bipolar transistor (101) coupled together such that the collector (102) of the bipolar transistor (101 ) connects to the emitter (301 ) of the FED (104).
  • the emitter 301
  • Fig. 3B depicts a first embodiment (300 1 ) for realizing this bipolar collector to FED emitter configuration.
  • the FED (104) comprises a non-planar structure having a cone shaped emitter (301) substantially as described above with respect to Fig. 1 B.
  • the bipolar transistor (101) may also be substantially as described above with respect to Fig. 1 B, with the exception that the collector region (102) of the bipolar transistor (101) underlies and electrically contacts the emitter (301) of the FED (104). So coupled, the bipolar collector directly connects to the FED emitter (301) in a common integral structure.
  • Fig. 3C depicts a second embodiment (300 2 ) of the bipolar collector to FED emitter configuration.
  • the FED (104) comprises a substantially planar structure as substantially described in Fig. 1 C above, with the exception that the gate (103) does not include the previously described extension that would otherwise contact the bipolar collector (102).
  • the bipolar transistor (101) may also be as substantially described above with respect to Fig. 1 C.
  • a metallization deposit (302) couples the transistor collector (102) to the FED emitter (301 ) to realize the desired configuration.
  • Fig. 3D depicts a third embodiment of the bipolar collector to FED emitter configuration.
  • the FED (104) comprises an inverted structure substantially as described above with respect to Fig. 1 D, with the exception that the gate (103) need not be comprised of a semiconductor material, but rather can be formed through use of metal deposition.
  • the bipolar transistor (101 ) can be formed in the manner as described above with respect to Fig. 1 D, albeit in a semiconductor layer (303) that has been deposited in proximity to the FED emitter (301). This semiconductor layer may be comprised of standard silicon materials, or amorphous (or polysilicon) semiconductor material.
  • This layer of material (303) functions as a collector (102) for the resultant bipolar transistor (101 ), and electrically contacts the FED emitter (301 ), thus realizing the desired configuration.
  • Fig. 4A provides a schematic depiction (400) of an FET (201) having an electrode (202) that couples to the emitter (401) of an FED (104).
  • the FED emitter (401 ) can also couple to an appropriate current source (402).
  • Fig. 4B depicts a first embodiment (400 1 ) of the FET electrode to FED emitter configuration.
  • the FED (104) may be a non-planar structure having a cone shaped emitter (401 ) substantially as described above with reference to Fig. 2B; similarly, the FET may be formed in the supporting substrate (108) substantially as described above in Fig.
  • the drain (202) of the FET (201) underlies, at least partially, the FED emitter (401 ) to thereby establish electrical contact therebetween.
  • This realizes the integral coupling between the FED electrode (in this case the drain (202)) and the emitter (401) of the FED (104).
  • Fig. 4C depicts a second embodiment (400 2 ) of the FET electrode to FED emitter configuration.
  • the FED (104) can be configured as described above with reference to Fig. 3C, inclusive of the metallization layer (302) that couples the emitter (401) of the FED (104) to a structure in a previous layer.
  • the FET (101) can be formed as described above with reference to Fig. 2C, with the exception that in this embodiment, the drain (202) at least partially underlies the metallization layer (302) that itself couples to the FED emitter (401), thereby realizing the desired configuration.
  • Fig. 4D depicts a third embodiment (400 3 ) of the FET electrode to FED emitter configuration.
  • the FED (104) comprises an inverted structure substantially as described above with reference to Fig. 2H, with the notable exception that the gate layer (103) does not electrically couple to the FET (201).
  • the FET (201 ) can be formed in a layer (134) of amorphous silicon or polysilicon semiconductor material, also as described above with reference to Fig. 2H.
  • a metal deposition (403) couples the drain (202) of the FET (201) to the metallization layer that comprises the FED emitter (401 ).
  • An alternative embodiment would provide for intimate contact between the FET drain (202) and the FED emitter (401) thereby eliminating the need for drain metallization (403).
  • Fig. 5 depicts an embodiment combining a plurality of the bipolar collector to FED gate embodiments (100) and the bipolar collector to FED emitter (300) embodiments.
  • three bipolar transistors (102) are coupled in this embodiment to the gates of three corresponding FEDs (104).
  • a single bipolar transistor (101) has its collector (102) coupled to the emitters (301) of each of the FEDs (104).
  • Fig. 6 depicts a plurality of FEDs (104) wherein the gate (103) of each FED couples to the drain (202) of a single FET (201 ) as described above with respect to Fig. 2A (and the various physical embodiments associated therewith).
  • the emitter (401) of each FED (104) couples to the drain (202) of a corresponding FET (201) as generally described above with respect to Fig. 4A (and the physical embodiments detailed in association therewith).
  • various of the physical embodiments described above to realize these FET to FED couplings could be utilized in correspondence to the necessities of the particular application at hand.
  • Fig. 7A provides a schematic depiction (700) of an FED (104) having its collector (704) coupled to the base (701) of a bipolar transistor (101).
  • the base (701) of the bipolar transistor (101) can additionally be coupled to a biasing source (703), and/or the collector (102) of the bipolar transistor (101 ) can be coupled to an appropriate current source and/or bias point (702).
  • Fig. 7B depicts a first embodiment (700 1 ) for the FED collector to bipolar transistor base configuration.
  • the FED (104) comprises a planar device as described above with reference to Fig. 1 C, with the exception that in this embodiment, the planar device has been depicted in a reversed orientation, and the anode (704) has also been depicted in this figure.
  • the gate (103) of the FED (104) does not include the extension described in Fig. 1 C to provide coupling to the bipolar transistor collector (102).
  • the bipolar transistor (101 ) may be formed as described above with reference to Fig. 1 C, with the exception that a metal deposition (706) has been provided to couple between the FED anode (704) and the bipolar transistor base (701 ). Also, a metal deposition (707) has been provided to allow subsequent coupling to the collector (102).
  • Fig. 7C depicts a second embodiment (700 2 ) of the FED anode to bipolar transistor base configuration.
  • the FED (104) comprises a non-planar structure having a cone shaped emitter substantially as described above with reference to Fig. 1 B (with the exception that in this embodiment, the FED anode (704) is shown as well, and is disposed outwardly from the FED gate (103).
  • the bipolar transistor (101 ) can be formed as described above with respect to Fig. 1 B, with the exception that in this embodiment, a metallization layer (708) is provided to electrically couple between the bipolar transistor base (701 ) and the FED anode (704) to realize the desired configuration.
  • Fig. 7D depicts a third embodiment (700 3 ) of the FED anode to bipolar transistor base configuration.
  • the bipolar transistor (101 ) can be formed in an appropriate semiconductor substrate (108) substantially as described above in various embodiments.
  • the FED (104) can be comprised of a non- planar structure having a cone shaped emitter in accordance with various of the embodiments described above.
  • the emitter can be encapsulated by the FED anode (704), which anode (704) can be provided with an electrical conductive path (709 and 711 ) through the various layers that comprise the combined devices to allow electrical coupling with the base (701 ) of the bipolar transistor (101 ).
  • Fig. 8A provides a schematic representation (800) of an FED (104) having a collector (704) that couples to the emitter (801) of a bipolar transistor (101). As may be appropriate to a particular application, the emitter (801) of the bipolar transistor (101 ) can also couple to an appropriate current source or bias point.
  • Fig. 8B depicts a first embodiment (800 1 ) of the
  • both the FED (104) and the bipolar transistor (101) may be constructed in the same manner as described above with reference to Fig. 7C, with the exception that in this embodiment, the bipolar transistor is oriented such that a conductive layer (803) couples the emitter (801) of the bipolar transistor (101 ) to the anode (704) of the FED (104).
  • Fig. 8C depicts a second embodiment (800 2 ) of the FED anode to bipolar transistor emitter configuration.
  • both the FED (104) and the bipolar transistor (101 ) are formed substantially in accordance with the embodiment depicted in Fig. 7D above, with the exception that the bipolar transistor (101 ) is positioned such that the bipolar transistor emitter (801 ) can be suitably electrically connected (803 and 709) to the FED anode (704) as depicted.
  • Fig. 9A depicts a schematic representation (900) wherein an FED anode (902) couples directly to the gate (901) of an FET (201). As may be appropriate to a particular application, the FET gate (901 ) can also be coupled to an appropriate bias point or current source (903).
  • Fig. 9B depicts a first embodiment (900 1 ) for the
  • the FED (104) can be configured as previously depicted in Fig. 8B.
  • the FET (201) may be configured as described above with respect to Fig. 2B, with the exception that the source does not couple to the anode (902) of the FED (104). Instead, the anode (902) extends sufficiently in distance to be electrically coupled to the gate metallization (901 ) of the FET (201).
  • Fig. 9C depicts a second embodiment (900 2 ) for the FED anode to FET gate configuration.
  • the FED (104) may be as described above with reference to Fig. 8C.
  • the FET (201) may be as described above with respect to Fig. 2B.
  • the FET gate metallization (901 ) is directly electrically coupled to the FED anode (902).
  • Fig. 10A provides a schematic representation
  • Fig. 10B depicts a first embodiment (1000 1 ) of an FED anode to FET source configuration.
  • the FED (104) comprises a planar structure substantially as described above with reference to Fig. 7B.
  • the FET (201) can be formed as described above with reference to Fig. 4C.
  • the source (202) of the FET (201 ) is positioned to electrically contact the anode (902) of the FED (104).
  • Fig. 10C depicts a second embodiment (1000 2 ) for the FED anode to FET source configuration.
  • the FED (104) may be configured as described above with respect to Fig. 7C.
  • the FET (201) may be configured as described above with reference to Fig. 2B, with the exception that in this embodiment, the FET source (202) is electrically coupled (906) to the FED anode (902).
  • Fig. 10D depicts a third embodiment (1000 3 ) of the FED anode to FET source configuration.
  • the FED may be configured as described above with respect to Fig. 7D.
  • the FET (201) may be configured as described above with reference to Fig. 10C, such that the FET source (202) is electrically coupled (906) to the FED anode (902).
  • Fig. 11A depicts a fourth embodiment (700 4 ) of the FED anode to bipolar transistor base configuration.
  • the FED anode (704) couples to the bases (701) of a plurality of bipolar transistors (101 ).
  • Such a circuit could be physically implemented in an integral package through appropriate selection of various of the above described physical embodiments.
  • Fig. 11 B depicts a fourth embodiment (800 4 ) of the FED anode to bipolar transistor emitter configuration.
  • the FED anode (704) couples to the emitter (801 ) of a plurality of bipolar transistors (101 ).
  • Such a circuit could be physically implemented in an integral package through appropriate selection of various of the above described physical embodiments.
  • Fig. 12A depicts a third embodiment (900 3 ) of the FED anode to FET gate configuration'.
  • the FED anode (902) couples to a plurality of FET gates metallization (901).
  • Such a circuit could be physically implemented in an integral package through appropriate selection of various of the above described physical embodiments.
  • Fig. 12B provides a fourth embodiment (1000 4 ) of the FED anode to FET source configuration.
  • the FED anode (902) couples to a plurality of FET sources (202).
  • Such a circuit could be physically implemented in an integral package through appropriate selection of various of the above described physical embodiments.

Abstract

A variety of integrally combined field emission devices (104) and non-field emission control and/or controlled devices (101), such as field effect transistors (201) and bipolar transistors (101). Various embodiments of field emission devices (104) are accommodated, including those having substantially planar oriented electrodes, non-planar structures having cone shaped emitters (107), and inverted emitter structures.

Description

COLD CATHODE FIELD EMISSION DEVICE HAVING INTEGRAL CONTROL OR CONTROLLED NON-FED DEVICES
Technical Field
This invention relates generally to cold cathode field emission devices.
Background of the Invention
Solid state cold cathode field emission devices (FEDs) are known. In such devices, electron emission occurs in conjunction with a cold cathode. There are significant anticipated advantages to this technology. The prior art also teaches that such cold cathode field emission devices can be configured in an integral array with one another to support, for example, anticipated current carrying capacity requirements. A number of problems remain in deriving successful use of such devices. According to one such problem, non-integral control of the FEDs must be provided, and/or the FEDs must control non-integral controlled devices. (By use of the term "integral," the Applicant intends to refer to an onboard relationship between an FED and other structures in a single integrated structure, such as that formed pursuant to the deposition and diffusion processes utilized to construct some integrated circuits.) Further, known prior art techniques being utilized to fabricate FEDs, such as dry etching processes and deposition processes that are used with non-semiconductor materials, are not particularly conducive to supporting simultaneous manufacture of integrated control or controlled devices.
Accordingly, a need exists for a methodology of forming integral control and/or controlled active devices in conjunction with FEDs, and for the resultant devices themselves.
Summary of the Invention
These needs and others are substantially met through provision of the methodology and devices disclosed herein. Pursuant to this invention, an electronic device can be provided that is comprised of a cold cathode field emission device and a non-field emission active device that is formed integrally with the cold cathode field emission device, such that the cold cathode field emission device and the non-field emission active device are operably coupled to one another. Pursuant to one embodiment of the invention, the non-field emission active device can be a bipolar transistor. In another embodiment of the invention, the non-field emission active device can be a field effect transistor. In one embodiment of the invention, the FED can be configured to control the non-FED. In an alternative embodiment of the invention, the FED can be configured to be controlled by the non-FED.
In varying embodiments of the invention, the non- FED can be formed in varying layers that comprise the FED, including the substrate wafer itself. Various embodiments of FEDs can be configured in conjunction with such non-FEDs, including planar structures (wherein the various electrodes that comprise the FED are disposed substantially planar to one another), non- planar FEDs (wherein, for example, the electrodes that comprise the FED are disposed in a substantially non- planar manner to one another, and where the emitter often assumes the form of a cone), and inverted FED structures (where, for example, the emitter is not formed on the substrate wafer itself). The teachings of this invention are applicable in a wide variety of applications, including stand alone devices, integrated device arrays, and flat screen displays, to name a few. In another embodiment of this invention, at least certain layers of the FED can be comprised of amorphous or polysilicon semiconductor materials, and the non-FED device can be formed therein. Such materials can also be utilized to serve as an electrode within the FED itself. The benefits afforded by the various embodiments of this invention include onboard low power control of an array of current sources, low power high speed parallel switching of devices, devices that are comprised of merged technologies wherein the attributes of each technology can be exploited as appropriate to a particular application, and onboard matrix addressing of fiat panel displays. Brief Description of the Drawings
Fig. 1A comprises a schematic representation of a bipolar transistor configured to control the gate of an FED;
Figs. 1 B-I comprise side elevational sectioned views of alternative embodiments of realizing the circuit depicted in Fig. 1 A;
Fig. 2A comprises a schematic representation of a field effect transistor configured to control the gate of an FED;
Figs. 2B-H comprise side elevational sectioned views of alternative embodiments of realizing the circuit depicted in Fig. 2A; Fig. 3A comprises a schematic representation of a bipolar transistor coupled to the emitter of an FED;
Figs. 3B-D comprise side elevational sectioned views of alternative embodiments of realizing the circuit depicted in Fig. 3A; Fig. 4A comprises a schematic representation of a field effect transistor coupled to the emitter of an FED;
Figs. 4B-D comprise side elevational sectioned views of alternative embodiments of realizing the circuit depicted in Fig. 4A; Fig. 5 comprises a schematic representation of a plurality of bipolar transistors configured to control a plurality of FEDs;
Fig. 6 comprises a schematic representation of a plurality of field effect transistors configured to control a plurality of FEDs;
Fig. 7A comprises a schematic representation of an FED coupled to the base of a bipolar transistor; Figs. 7B-D comprise side elevational sectioned views of alternative embodiments of realizing the circuit depicted in Fig. 7A;
Fig. 8A comprises a schematic representation of an FED coupled to the emitter of a bipolar transistor;
Figs. 8B-C comprise side elevational sectioned views of alternative embodiments of realizing the circuit depicted in Fig. 8A;
Fig. 9A comprises a schematic representation of an FED coupled to the gate of a field effect transistor;
Figs. 9B-C comprise side elevational sectioned views of alternative embodiments of realizing the circuit depicted in Fig. 9A;
Fig. 10A comprises a schematic representation of an FED coupled to the source of a field effect transistor;
Figs. 10B-D comprise side elevational sectioned views of alternative embodiments of realizing the circuit depicted in Fig. 10A;
Fig. 11A comprises a schematic depiction of an FED coupled to the bases of a plurality of bipolar transistors ;
Fig. 11 B comprises a schematic depiction of an FED coupled to the emitters of a plurality of bipolar transistors ; Fig. 12A comprises a schematic depiction of an
FED coupled to the gates of a plurality of field effect transistors ;
Fig. 12B comprises a schematic depiction of an FED coupled to the sources of a plurality of field effect transistors. Best Mode For Carrying Out The Invention
BIPOLAR TRANSISTOR TO FED GATE CONFIGURATION
Fig. 1A presents a schematic depiction (100) of a bipolar transistor (101 ) that couples, via its collector (102) to the gate (103) of a field emission device (104). Other leads depicted can be coupled as appropriate to accommodate a particular application. For example, the collector (102) could also couple to an appropriate source (106) in accordance with well understood methodology. So configured, the bipolar transistor (101 ) can effectively control the gate modulation of the FED (104). Fig. 1 B depicts a first embodiment (1001 ) for realizing the schematic representation depicted in Fig. 1A. In this embodiment (1001 ), the FED (104) comprises a non-planar structure having a cone emitter (107) formed on (and/or in) a semiconductor substrate (108), such as, for example, a silicon wafer. Deposited atop subsequent insulating layers (109) is the gate (103). Both the emitter (107) and the gate (103) may be comprised of metal or semiconductor material. The details of forming such a device are understood in the art, and hence will not be presented here. Also, though not depicted in this figure for the sake of simplicity, the FED (104) may also include an anode electrode as well.
In this embodiment (1001), the bipolar transistor (101) has been formed in the substrate material (108). In particular, through use of known deposition, etching, doping, and diffusion techniques, the bipolar transistor (101 ) includes a collector (102), a base (111 ), and an emitter (112). Through appropriate metallization deposition, the collector (102) couples to the gate (103) of the FED (104) via the formed conductive path (113). In addition, other metallization depositions (114 and 116) can be deposited to provide appropriate conductive paths to and from the emitter (112) and the base (111). So configured, the bipolar transistor (101) and the FED (104) are integrally formed in and on the same substrate (108) using known semiconductor material processing methodologies.
Fig. 1 C depicts a second embodiment (1002) of a bipolar transistor having a collector that couples to the gate of an FED. In this embodiment again, the bipolar transistor (101) is formed within a semiconductor wafer (108) and includes a collector (102), a base (111 ), and an emitter (112). Metal depositions (114 and 116) provide conductive access to the emitter and base (112 and 116, respectively).
In this embodiment (1002), however, the FED (104) has a substantially planar geometry, such as that proposed in U.S. Patent No. 4,827,177 to Lee et al. and in U.S. Serial No. 07/330,050, filed on March 29, 1989, to Kane et al., both of which references are incorporated herein. The particular specific configuration for the FED (104) is not critical, provided, that the gate includes a conductive path (1 17) that conductively couples the gate (103) to the collector (102) of the bipolar transistor (101). The FED (104) includes generally a gate (103) that functions to modulate electron emission from the emitter (118), the latter being formed atop an insulating layer (119). The device would also likely include an anode, which Fig. 1 C does not depict for purposes of simplicity.
Fig. 1 D depicts a third embodiment (1003) of this bipolar-to-FED configuration. In this embodiment, the FED (104) comprises an anode metallization layer (122) formed on a support substrate (121) that may, or may not, comprise a semiconductor material. An insulating layer (123) separates the anode (122) from the gate (103). In this embodiment, the gate (103) can be comprised of a semiconductor material in order to support construction of the bipolar transistor (101), as described below in more detail. Another layer of insulation (124) separates the gate layer (103) from the emitter (126). In an appropriate application, of course, the FED (104) would typically be encapsulated in order to ensure vacuum conditions most supportive of the desired electron emission activity. (Additional details regarding the structure and construction of an inverted FED can be found in U.S. Serial No. 07/414,836, filed on September 29, 1989, for a Flat Panel Display Using Field Emission Devices by Kane, which reference is incorporated herein.)
The gate layer (103), being comprised of a semiconductor material, supports construction of the bipolar transistor (101) in the manner described above. In this embodiment (1003), the gate layer (103) itself functions as the collector (102) for the bipolar transistor (101). Hence, the collector (102) and the gate (103) are integrally combined.
Fig. 1 E depicts a fourth embodiment (1004) of this bipolar collector to FED gate configuration. In this embodiment, the bipolar transistor (101 ) is again formed within the gate layer (103) as described above with respect to Fig. 1 D, such that the collector (102) of the bipolar transistor (101 ) and the gate (103) of the FED (104) are again comprised of shared material. In this embodiment, however, the FED (104) comprises a non- planar FED having a cone shaped emitter (127), as versus the inverted structure depicted in Fig. 1 D. The cone shaped emitter (127) resides on either a metallization layer (not shown) which resides on the substrate layer (121) or may reside directly on the substrate layer (121) as depicted. An insulating layer (128) separates the gate (103) from the metallization layer (132) or substrate layer (121). A second insulation layer (129) then separates the gate (103) and the emitter (127) from the anode (131). Additional details regarding the construction of an
FED having such a cone shaped emitter can be found in, for example, U.S. Patent No. 4,721 ,885 to Brodie and in
U.S. Serial No. , filed on February 9,
1990, for a Non-Planar Field Emission Device Having an Emitter Formed With a Substantially Normal Vapor Deposition Process by Goronkin et al., both of which references are incorporated herein.
Fig. 1 F depicts a fifth embodiment (1005) of a bipolar collector to FED gate configuration. In this embodiment, the FED (104) has a non-planar configuration as described above in Fig. 1 E, with the exception that, in this depiction, the anode has not been shown for purposes of simplicity.
In this embodiment, the bipolar transistor (101 ) has been formed in a layer of amorphous silicon (or polysilicon) semiconductor material (134) that itself has been deposited atop a bifurcated layer that includes the FED gate (103) and an insulating material (133). The amorphous silicon (134) comprises the collector (102) of the bipolar transistor (101). This amorphous silicon layer (134) contacts the gate layer (103) of the FED (104). Therefore, again, the collector (102) of the bipolar transistor (101) integrally couples to the gate (103) of the FED (104).
Fig. 1 G depicts a sixth embodiment (1006) of the bipolar collector to FED gate configuration. In this embodiment, the FED (104) has the same architecture as the FED depicted in Fig. 1 F. In this embodiment, however, the gate layer (103) is comprised of amorphous silicon (or polysilicon) semiconductor material. The bipolar transistor (101) is otherwise constructed as described above, with the collector (102) of the bipolar transistor (101) again sharing common material with the gate (103) of the FED (104).
Fig. 1 H depicts a seventh embodiment (1007) of the bipolar collector to FED gate configuration. In this embodiment, the FED (104) comprises an inverted emitter structure such as that described above with respect to Fig. 1 D. In this embodiment, however, the bipolar transistor (101) has been formed in a layer of amorphous silicon (or polysilicon) semiconductor material (134) that has been deposited substantially coplanar to the emitter (126) of the FED (104). An appropriate metallization deposition (136) couples the amorphous material (134), and hence the collector (102) of the bipolar transistor (101) to the gate (103) of the FED (104). This particular embodiment has the advantage of presenting the electrodes (114 and 116) of the bipolar transistor (101 ) substantially external to at least preceding layers. This may facilitate coupling to these electrodes (114 and 116) pursuant to a particular application.
Fig. 11 depicts an eighth embodiment (1008) of a bipolar collector to FED gate configuration. In this embodiment (1008), the FED (104) comprises a non- planar FED having a cone shaped emitter as described above with respect to Fig. 1 E. Also in this embodiment, the bipolar transistor (101) can be comprised as described above with respect to Fig. 1 H, such that the collector (102) of the bipolar transistor (101 ) couples through an appropriate metallization layer (136) to the gate (103) of the FED (104).
FIELD EFFECT TRANSISTOR TO FED GATE CONFIGURATION
Fig. 2A provides a schematic representation (200) of a field effect transistor (FET) (201 ) that couples via one of its electrodes (202) to the gate (103) of an FED (104). The FET electrode (202) may be either the source or the drain, as described below in more detail. This configuration provides the same control capabilities as described above with respect to Fig. 1A, albeit through use of FET technology as versus bipolar technology. Fig. 2B depicts a first embodiment (2001) of an FET electrode to FED gate configuration. In this embodiment (2001 ), the FED (104) can be configured as described above with reference to Fig. 1 B. In this embodiment, however, the semiconductor substrate (108) has formed therein, through known methodologies, an FET drain
(202) and source (203). An FET gate (204) can be formed through deposition of metallic material (205) atop an insulator (206) in known manner. A metallic conductor (207) can be deposited atop the source (203), and successive metallic depositions (208) can link the drain
(202) of the FET transistor (201) to the gate (103) of the FED (104).
Fig. 2C depicts a second embodiment (2002) of the FET electrode to FED gate configuration. In this embodiment, the FED (104) comprises a substantially planar structure as described above in Fig. 1 C. In this embodiment, however, the semiconductor substrate (108) has formed therein the drain (202) and source
(203) of the FET (201). An appropriate gate (204) can be formed by deposition of an insulating layer (206) and contact (205) metallization. The drain (202) and FED gate (103) are coupled to one another via an extension (117) of the gate (103).
Fig. 2D depicts a third embodiment (2003) of the FET electrode to FED gate configuration. In this embodiment, the FED (104) may be configured as an inverted structure as described above with respect to Fig. 1 D. In this embodiment, however, the gate layer (103) for the FED (104) has been bifurcated, to include a semiconductor layer (209), within which the source (203) and drain (202) of the FET (201) can be formed. The FET gate (204) can be realized by a conductor (205) deposited atop the insulating layer (206) as before; in a similar manner, the source (203) can have a metallization layer (207) deposited thereon to provide a conductive path thereto. Finally, the drain (202) has an appropriate conductive path (208) formed between itself and the FED gate (103). Fig. 2E depicts a fourth embodiment (2004) of the FET electrode to FED gate configuration. In this embodiment, the FED (104) may be a substantially non- planar device having a cone shaped emitter (127) as described above with reference to Fig. 1 E (in this embodiment, a metallization layer (132) is depicted). The FET (201) can be as described above with reference to Fig. 2D, such that the drain (202) of the FET (201) couples to the FED gate (103) via an appropriate conductive path (208).
Fig. 2F depicts a fifth embodiment (2005) of the FET electrode to FED gate configuration. In this embodiment (2005), the FED (104) may be as described above with reference to Fig. 1 F. The FET (201 ) may be formed in a layer of amorphous or polysilicon semiconductor material (134), also as described above in Fig. 1 F. In this embodiment, the drain (202) couples to the FED gate (103) by direct contact.
Fig. 2G depicts a sixth embodiment (2006) of realizing the FET electrode to FED gate configuration. In this embodiment, the FED (104) can be configured as described above with reference to Fig. 1 F. The FET (201) can be configured as described above with reference to Fig. 2E, with the exception that the source (203) and drain (202) are formed in a layer of amorphous silicon (or polysilicon) semiconductor material (211 ).
Fig. 2H depicts a seventh embodiment (2007) for the FET electrode to FED gate configuration. In this embodiment, the FED (104) may be an inverted structure as described above with reference to Fig. 1 H. The FET (201) is formed in an amorphous silicon (or polysilicon) semiconductor material layer (134) as described above with reference again to Fig. 1 H. Both the source (203) and the drain (202) are formed in the amorphous layer (134). The drain (202) couples to the gate (103) of the FED (104) via an appropriate metallization path (136).
BIPOLAR COLLECTOR TO FED EMITTER CONFIGURATION
Fig. 3A depicts a schematic representation (300) of an FED (104) and a bipolar transistor (101) coupled together such that the collector (102) of the bipolar transistor (101 ) connects to the emitter (301 ) of the FED (104). In an appropriate application, the emitter
(301) can also couple to an appropriate current source
(302) to support a desired mode of operation. Fig. 3B depicts a first embodiment (3001 ) for realizing this bipolar collector to FED emitter configuration. The FED (104) comprises a non-planar structure having a cone shaped emitter (301) substantially as described above with respect to Fig. 1 B. The bipolar transistor (101) may also be substantially as described above with respect to Fig. 1 B, with the exception that the collector region (102) of the bipolar transistor (101) underlies and electrically contacts the emitter (301) of the FED (104). So coupled, the bipolar collector directly connects to the FED emitter (301) in a common integral structure.
Fig. 3C depicts a second embodiment (3002) of the bipolar collector to FED emitter configuration. In this embodiment, the FED (104) comprises a substantially planar structure as substantially described in Fig. 1 C above, with the exception that the gate (103) does not include the previously described extension that would otherwise contact the bipolar collector (102). The bipolar transistor (101) may also be as substantially described above with respect to Fig. 1 C. In this embodiment, a metallization deposit (302) couples the transistor collector (102) to the FED emitter (301 ) to realize the desired configuration.
Fig. 3D depicts a third embodiment of the bipolar collector to FED emitter configuration. In this embodiment (3003), the FED (104) comprises an inverted structure substantially as described above with respect to Fig. 1 D, with the exception that the gate (103) need not be comprised of a semiconductor material, but rather can be formed through use of metal deposition. Further, the bipolar transistor (101 ) can be formed in the manner as described above with respect to Fig. 1 D, albeit in a semiconductor layer (303) that has been deposited in proximity to the FED emitter (301). This semiconductor layer may be comprised of standard silicon materials, or amorphous (or polysilicon) semiconductor material. This layer of material (303) functions as a collector (102) for the resultant bipolar transistor (101 ), and electrically contacts the FED emitter (301 ), thus realizing the desired configuration.
FET ELECTRODE TO FED EMITTER CONFIGURATION
Fig. 4A provides a schematic depiction (400) of an FET (201) having an electrode (202) that couples to the emitter (401) of an FED (104). As may be appropriate to a particular application, the FED emitter (401 ) can also couple to an appropriate current source (402). Fig. 4B depicts a first embodiment (4001) of the FET electrode to FED emitter configuration. In this embodiment, the FED (104) may be a non-planar structure having a cone shaped emitter (401 ) substantially as described above with reference to Fig. 2B; similarly, the FET may be formed in the supporting substrate (108) substantially as described above in Fig. 2B, with the exception that the drain (202) of the FET (201) underlies, at least partially, the FED emitter (401 ) to thereby establish electrical contact therebetween. This realizes the integral coupling between the FED electrode (in this case the drain (202)) and the emitter (401) of the FED (104).
Fig. 4C depicts a second embodiment (4002) of the FET electrode to FED emitter configuration. In this embodiment, the FED (104) can be configured as described above with reference to Fig. 3C, inclusive of the metallization layer (302) that couples the emitter (401) of the FED (104) to a structure in a previous layer. The FET (101) can be formed as described above with reference to Fig. 2C, with the exception that in this embodiment, the drain (202) at least partially underlies the metallization layer (302) that itself couples to the FED emitter (401), thereby realizing the desired configuration.
Fig. 4D depicts a third embodiment (4003) of the FET electrode to FED emitter configuration. In this embodiment, the FED (104) comprises an inverted structure substantially as described above with reference to Fig. 2H, with the notable exception that the gate layer (103) does not electrically couple to the FET (201). Similarly, the FET (201 ) can be formed in a layer (134) of amorphous silicon or polysilicon semiconductor material, also as described above with reference to Fig. 2H. In this embodiment, however, a metal deposition (403) couples the drain (202) of the FET (201) to the metallization layer that comprises the FED emitter (401 ). An alternative embodiment would provide for intimate contact between the FET drain (202) and the FED emitter (401) thereby eliminating the need for drain metallization (403).
MULTIPLE BIPOLAR TRANSISTORS TO MULTIPLE FEDs CONFIGURATION
Fig. 5 depicts an embodiment combining a plurality of the bipolar collector to FED gate embodiments (100) and the bipolar collector to FED emitter (300) embodiments. In particular, three bipolar transistors (102) are coupled in this embodiment to the gates of three corresponding FEDs (104). A single bipolar transistor (101) has its collector (102) coupled to the emitters (301) of each of the FEDs (104). This schematic representation could of course be realized through use of any of the earlier described physical embodiments for obtaining the various configurations utilized, and/or through a mixing of these embodiments as might be appropriate to a particular application.
MULTIPLE FETs TO MULTIPLE FEDs CONFIGURATION
Fig. 6 depicts a plurality of FEDs (104) wherein the gate (103) of each FED couples to the drain (202) of a single FET (201 ) as described above with respect to Fig. 2A (and the various physical embodiments associated therewith). The emitter (401) of each FED (104) couples to the drain (202) of a corresponding FET (201) as generally described above with respect to Fig. 4A (and the physical embodiments detailed in association therewith). Again, various of the physical embodiments described above to realize these FET to FED couplings could be utilized in correspondence to the necessities of the particular application at hand.
FED COLLECTOR TO BIPOLAR TRANSISTOR BASE CONFIGURATION
Fig. 7A provides a schematic depiction (700) of an FED (104) having its collector (704) coupled to the base (701) of a bipolar transistor (101). Depending upon the needs of a particular application, the base (701) of the bipolar transistor (101) can additionally be coupled to a biasing source (703), and/or the collector (102) of the bipolar transistor (101 ) can be coupled to an appropriate current source and/or bias point (702).
Fig. 7B depicts a first embodiment (7001 ) for the FED collector to bipolar transistor base configuration. In this embodiment, the FED (104) comprises a planar device as described above with reference to Fig. 1 C, with the exception that in this embodiment, the planar device has been depicted in a reversed orientation, and the anode (704) has also been depicted in this figure. Also, the gate (103) of the FED (104) does not include the extension described in Fig. 1 C to provide coupling to the bipolar transistor collector (102). The bipolar transistor (101 ) may be formed as described above with reference to Fig. 1 C, with the exception that a metal deposition (706) has been provided to couple between the FED anode (704) and the bipolar transistor base (701 ). Also, a metal deposition (707) has been provided to allow subsequent coupling to the collector (102).
Fig. 7C depicts a second embodiment (7002) of the FED anode to bipolar transistor base configuration. In this embodiment, the FED (104) comprises a non-planar structure having a cone shaped emitter substantially as described above with reference to Fig. 1 B (with the exception that in this embodiment, the FED anode (704) is shown as well, and is disposed outwardly from the FED gate (103). The bipolar transistor (101 ) can be formed as described above with respect to Fig. 1 B, with the exception that in this embodiment, a metallization layer (708) is provided to electrically couple between the bipolar transistor base (701 ) and the FED anode (704) to realize the desired configuration.
Fig. 7D depicts a third embodiment (7003) of the FED anode to bipolar transistor base configuration. In this embodiment, the bipolar transistor (101 ) can be formed in an appropriate semiconductor substrate (108) substantially as described above in various embodiments. The FED (104) can be comprised of a non- planar structure having a cone shaped emitter in accordance with various of the embodiments described above. The emitter can be encapsulated by the FED anode (704), which anode (704) can be provided with an electrical conductive path (709 and 711 ) through the various layers that comprise the combined devices to allow electrical coupling with the base (701 ) of the bipolar transistor (101 ). FED ANODE TO BIPOLAR TRANSISTOR EMITTER CONFIGURATION
Fig. 8A provides a schematic representation (800) of an FED (104) having a collector (704) that couples to the emitter (801) of a bipolar transistor (101). As may be appropriate to a particular application, the emitter (801) of the bipolar transistor (101 ) can also couple to an appropriate current source or bias point. Fig. 8B depicts a first embodiment (8001) of the
FED anode to bipolar transistor emitter configuration. In this embodiment, both the FED (104) and the bipolar transistor (101) may be constructed in the same manner as described above with reference to Fig. 7C, with the exception that in this embodiment, the bipolar transistor is oriented such that a conductive layer (803) couples the emitter (801) of the bipolar transistor (101 ) to the anode (704) of the FED (104).
Fig. 8C depicts a second embodiment (8002) of the FED anode to bipolar transistor emitter configuration. In this embodiment, both the FED (104) and the bipolar transistor (101 ) are formed substantially in accordance with the embodiment depicted in Fig. 7D above, with the exception that the bipolar transistor (101 ) is positioned such that the bipolar transistor emitter (801 ) can be suitably electrically connected (803 and 709) to the FED anode (704) as depicted.
FED ANODE TO FET GATE CONFIGURATION
Fig. 9A depicts a schematic representation (900) wherein an FED anode (902) couples directly to the gate (901) of an FET (201). As may be appropriate to a particular application, the FET gate (901 ) can also be coupled to an appropriate bias point or current source (903). Fig. 9B depicts a first embodiment (9001 ) for the
FED anode to FET gate configuration. In this embodiment, the FED (104) can be configured as previously depicted in Fig. 8B. The FET (201) may be configured as described above with respect to Fig. 2B, with the exception that the source does not couple to the anode (902) of the FED (104). Instead, the anode (902) extends sufficiently in distance to be electrically coupled to the gate metallization (901 ) of the FET (201).
Fig. 9C depicts a second embodiment (9002) for the FED anode to FET gate configuration. In this embodiment, the FED (104) may be as described above with reference to Fig. 8C. The FET (201) may be as described above with respect to Fig. 2B. The exceptions to both of the above referred to embodiments are that here, the FET gate metallization (901 ) is directly electrically coupled to the FED anode (902).
FED ANODE TO FET SOURCE CONFIGURATION
Fig. 10A provides a schematic representation
(1000) of an FED (104) having its anode (902) directly coupled to the source (202) of an FET (201 ).
Fig. 10B depicts a first embodiment (10001 ) of an FED anode to FET source configuration. In this embodiment, the FED (104) comprises a planar structure substantially as described above with reference to Fig. 7B. The FET (201) can be formed as described above with reference to Fig. 4C. The exceptions to the above are that in this embodiment, the source (202) of the FET (201 ) is positioned to electrically contact the anode (902) of the FED (104). Fig. 10C depicts a second embodiment (10002) for the FED anode to FET source configuration. In this embodiment, the FED (104) may be configured as described above with respect to Fig. 7C. The FET (201) may be configured as described above with reference to Fig. 2B, with the exception that in this embodiment, the FET source (202) is electrically coupled (906) to the FED anode (902).
Fig. 10D depicts a third embodiment (10003) of the FED anode to FET source configuration. In this embodiment, the FED may be configured as described above with respect to Fig. 7D. The FET (201) may be configured as described above with reference to Fig. 10C, such that the FET source (202) is electrically coupled (906) to the FED anode (902).
FED ANODE TO MULTIPLE BIPOLAR TRANSISTOR BASES CONFIGURATION
Fig. 11A depicts a fourth embodiment (7004) of the FED anode to bipolar transistor base configuration. In this embodiment, the FED anode (704) couples to the bases (701) of a plurality of bipolar transistors (101 ). Such a circuit could be physically implemented in an integral package through appropriate selection of various of the above described physical embodiments. FED ANODE TO MULTIPLE BIPOLAR TRANSISTOR EMITTERS CONFIGURATION
Fig. 11 B depicts a fourth embodiment (8004) of the FED anode to bipolar transistor emitter configuration. In this embodiment, the FED anode (704) couples to the emitter (801 ) of a plurality of bipolar transistors (101 ). Such a circuit could be physically implemented in an integral package through appropriate selection of various of the above described physical embodiments.
FED ANODE TO MULTIPLE FET GATES CONFIGURATION
Fig. 12A depicts a third embodiment (9003) of the FED anode to FET gate configuration'. In this embodiment, the FED anode (902) couples to a plurality of FET gates metallization (901). Such a circuit could be physically implemented in an integral package through appropriate selection of various of the above described physical embodiments.
FED ANODE TO MULTIPLE FET SOURCES CONFIGURATION
Fig. 12B provides a fourth embodiment (10004) of the FED anode to FET source configuration. In this embodiment, the FED anode (902) couples to a plurality of FET sources (202). Such a circuit could be physically implemented in an integral package through appropriate selection of various of the above described physical embodiments.
What is claimed is:

Claims

Claim?
1. An electronic device comprising: a cold-cathode field emission device; and being further characterized by a non-field emission active device formed integrally with the cold-cathode field emission device, wherein the cold-cathode field emission device is operably coupled to the non-field emission active device.
2. The device of claim 1 , wherein the non-field emission active device comprises a bipolar transistor.
3. The device of claim 2 wherein the cold-cathode field emission device is operably controlled, at least in part, by the bipolar transistor.
4. The device of claim 2 wherein the bipolar transistor is operably controlled, at least in part, by the cold-cathode field emission device.
5. The device of claim 1 , wherein the non-field emission active device comprises a field effect transistor.
6. The device of claim 5 wherein the cold-cathode field emission device is operably controlled, at least in part, by the field effect transistor.
7. The device of claim 6 wherein the field effect transistor is operably controlled, at least in part, by the cold-cathode field emission device.
8. The electronic device of claim 1 wherein the cold- cathode field emission device is operably controlled, at least in part, by the non-field emission semiconductor device.
PCT/US1991/002025 1990-03-30 1991-03-26 Cold cathode field emission device having integral control or controlled non-fed devices WO1991015874A1 (en)

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US502,593 1990-03-30

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992020087A1 (en) * 1991-05-06 1992-11-12 Eastman Kodak Company High resolution image source
US5438240A (en) * 1992-05-13 1995-08-01 Micron Technology, Inc. Field emission structures produced on macro-grain polysilicon substrates
US5500572A (en) * 1991-12-31 1996-03-19 Eastman Kodak Company High resolution image source
EP0764967A1 (en) * 1995-09-19 1997-03-26 HE HOLDINGS, INC. dba HUGHES ELECTRONICS Low cost system for effecting high density interconnection between integrated circuit devices
WO2000054299A1 (en) * 1999-03-09 2000-09-14 Matsushita Electric Industrial Co., Ltd. Field emission device, its manufacturing method and display device using the same
US6174449B1 (en) 1998-05-14 2001-01-16 Micron Technology, Inc. Magnetically patterned etch mask

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2861755B2 (en) * 1993-10-28 1999-02-24 日本電気株式会社 Field emission type cathode device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3970887A (en) * 1974-06-19 1976-07-20 Micro-Bit Corporation Micro-structure field emission electron source
US4513308A (en) * 1982-09-23 1985-04-23 The United States Of America As Represented By The Secretary Of The Navy p-n Junction controlled field emitter array cathode

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4663559A (en) * 1982-09-17 1987-05-05 Christensen Alton O Field emission device
JPS63274043A (en) * 1987-05-02 1988-11-11 オルトン・オ−・クリステンセン Field emission electron gun
FR2641108A1 (en) * 1988-12-23 1990-06-29 Thomson Csf Display device having a cathode ray tube screen
JP2656843B2 (en) * 1990-04-12 1997-09-24 双葉電子工業株式会社 Display device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3970887A (en) * 1974-06-19 1976-07-20 Micro-Bit Corporation Micro-structure field emission electron source
US4513308A (en) * 1982-09-23 1985-04-23 The United States Of America As Represented By The Secretary Of The Navy p-n Junction controlled field emitter array cathode

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP0476108A4 *

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992020087A1 (en) * 1991-05-06 1992-11-12 Eastman Kodak Company High resolution image source
US5818500A (en) * 1991-05-06 1998-10-06 Eastman Kodak Company High resolution field emission image source and image recording apparatus
US5500572A (en) * 1991-12-31 1996-03-19 Eastman Kodak Company High resolution image source
US5438240A (en) * 1992-05-13 1995-08-01 Micron Technology, Inc. Field emission structures produced on macro-grain polysilicon substrates
DE4315731B4 (en) * 1992-05-13 2006-04-27 Micron Technology, Inc. (N.D.Ges.D. Staates Delaware) Macro grain substrate semiconductor device and method of making the same
EP0764967A1 (en) * 1995-09-19 1997-03-26 HE HOLDINGS, INC. dba HUGHES ELECTRONICS Low cost system for effecting high density interconnection between integrated circuit devices
US5754009A (en) * 1995-09-19 1998-05-19 Hughes Electronics Low cost system for effecting high density interconnection between integrated circuit devices
US6174449B1 (en) 1998-05-14 2001-01-16 Micron Technology, Inc. Magnetically patterned etch mask
WO2000054299A1 (en) * 1999-03-09 2000-09-14 Matsushita Electric Industrial Co., Ltd. Field emission device, its manufacturing method and display device using the same

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EP0476108A1 (en) 1992-03-25
EP0476108A4 (en) 1992-06-24
JPH04506435A (en) 1992-11-05

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