WO1991015841A1

WO1991015841A1 - Video display for digital images at high frequency of frame refresh

Info

Publication number: WO1991015841A1
Application number: PCT/IT1990/000036
Authority: WO
Inventors: Antonio Maccari; Antonella Fresa
Original assignee: Tower Tech S.R.L.
Priority date: 1990-03-30
Filing date: 1990-03-30
Publication date: 1991-10-17

Abstract

The device enables to visualize the images registered in the video memory on the base of standard modes guaranteeing the compatibility with such informatic standards and improving the ergonomic characteristics of the display. The device consists of an intelligent programmable video controller (21) which generates the data and control signals for the cathode-ray tube monitor (22). The number of pixels on each line and the number of lines on each frame are defined by the standard graphics for Personal Computers, named VGA. Such standard is foreseen to use a frequency for frame refresh under 60 Hz for the resolution graphic modes (640 pixels for 480 lines) and equal to 70 Hz for the text modes. The invention device enables to obtain frame refresh frequency above 70 Hz for whatever mode, while respecting the compatibility with the standard VGA, by means of speeder pixel clocks (27 and 28), of the circuitry (5) used to select them, as well as for the monitor (22) capable of synchronizing on the frequencies generated for the ergonomic mode.

Description

"Video display for digital images at high frequency of frame refresh".

The present invention concerns a device able to display digital images formed by pixels ordered on lines and columns on ^' an intelligent screen. This visualization consists of a set of pixel signals, characterized by the horizontal and vertical scanning frequency on the screen, according to pre-fixed resolutions on the base of the contents of a video memory which is periodically read by the pixel signal generator. The viϊleo controller includes a series of registers which must be programmed with the proper parameters according to the chosen type of resolution. The video contains the mechanisms for the horizontal and vertical synchronization and sweep, in order to synchronize on the pixel signal, generated by the video controller, and consequently to position the cathode-rays gun in the right position on the screen.

There are many video displays of the above described type. Some of such video controllers which use particular resolu¬ tions, a certain set of programmable registers and a video memory structured according to exact access mode, became a standard in the industrial branch of the personal computer. For these controllers a very large number of programs and applications has been developed with reference to them and, therefore it is essential for a personal computer to offer the compatibility with this "de facto standard". One of the most powerful and diffused standard is- called VGA. The technical problem resolved by the present invention is to improve the visual characterists of th image on the screen, still respecting the need of compatibility due to the VGA standard. There are many parameters that define the quality of the video image, and one of the most important is the frequency of the frame refresh. This frequency determines the time between two subsequent passages of the electron beam on the same point of the screen. More frequent is this passage, more stable the immage appears to the eye of the observing operator, thus reducing the wear of the retina and of whole view apparatus.

The device is expressed through the operational components which operate in the numeral sequence of table 1. Through the communication channel of data and addresses 2, the central control unit 1 of the host system accesses to register 20 and gets the information on the monitor type to determine the program sequences to use for programming the timing registers of the video controller. Consequently, the said unit 1 accesses the program memory 3, to activate the program sequences 4 which inform the circuit of pixel clock selection 5. This circuit, on the base of this information as well as of the identification signal 19 coming from the monitor 22, selects the pixel clock 6, which will temporize the operations of the video signal generator 8 and of the digital-to-analog converter of the video signal 12. The same central control unit 1 of the host system, through the same communication channel of data and addresses 2, accesses to the same program memory 3 to activate the sequences of program 7, which, with the programming sequences required by the set video mode, initialize the registers of the video signal generator 8. This video signal generator 8 scans the video memory 17, previously filled by the central control unit 1 through the data and addresses channel 2, to obtain the information through the data and addresses channel 18. The same video signal generator 8 will transform these information into digital video signals and will put them on the data channel 11 towards the D/A converter 12, as well as will generate the horizontal 9 and vertical 10 sync signal which are sent both to the D/A converter 12, to interprete the data flow of channel 11, to the mode detector circuit 14, which stays in the video module, and to the circuitry of the monitor. For the timing of the video signals and synchronisms the video signal generator 8 will use the pixel clock 6 as the time base, and the contents of its timing registers, which are programmed by the program sequences 7, will define the characteristics of these timings. The mode detector circuit 14 arranges to generate the information 15 for the synchroniza- tion circuits afid for the actuators of the cathode-ray beam 16, in order to select the operation of higher frequences than the standard one.

A preferred execution form of the circuit for the pixel clock selction is represented in table 2, for an exemplifying but not limiting purpose. Through the data and addresses channel 4, the selction register 23 for the ergonomicor the standard VGA mode is initialized. The coincidence (logical AND) of the information coming from the register 23 and of the identification signal 19 coming from the monitor, which indicates whether the monitor is able to support the high frequency refresh mode, is sent on the INPUT selection ^' signal (A/B) of the MULTIPLEXER 24. The MULTIPLEXER 24 in INPUT has the standard clocks 25 and 26, respectively like

90 25,275 MHz and 28,322 MHz, and the speeder clocks 27 and 28 used for the ergonomic mode. On the OUTPUT lines 29 and 30 the MULTIPLEXER 24 selects the pixel clock for the alpha- numerical and graphic modes which have different horizontal resolutions and, therefore, different pixel clocks. It must

95 be noted that the monitor, through the identification signal 19, will state to the video controller that it can to support the ergonomic mode, when it is able to accept two horizontal frequences equal to 31,5 KHz, standard VGA frequency and at least 35,5 KHz required for the ergonomic VGA mode. The

100 pixel clocks 29 and 30 become the INPUT for a second MULTIPLE¬ XER 31 which in OUTPUT selects the pixel clock 6 on the base of the INPUT selection signal coming from the register 32.which is programmed through the data and addresses channel 4 and which indicates whether the current mode is alpha-

105 numerical or graphic.

Alternatively, the register 32 could be replaced by a register which memorizes the information of a user accessable switcn, who selects between standard VGA video mode and ergonomic 110 VGA video mode.

The present device is illustrated in a merely indicative way by the drawings of the tables 1 and 2. With reference to these tables, fig. 1 is the scheme of the different operati- 115 ve components, whereas fig. 2 is a preferred execution form for the selection circuit of pixel clock 5.

Claims

Claim.

1) Video display for digital images at high frequency of frame refresh, characterized by the fact that through the communi¬ cation channel of data and addresses (2) the central control unit (1) of the host system accesses to register (20) and gets the information on the monitor type to determine the program sequences to use for programming the timing registers of the video controller. Consequently, the said unit (1) accesses the program memory (3) to activate the program sequences (4) which inform the circuit of pixel clock selection (5). This circuit, on the base of this information as well as of the identification signal (19) coming from the monitor (22), selects the pixel clock (6), which will temporize the operations of the video signal generator (8) and of the digital-to-analog converter of the video signal (12). The same central control unit (1) of the host system, through the same communication channel of data and addresses (2), accesses to the same program memory (3) to activate the sequences of . program (7), which, with the programming sequences required by the set video mode, initialize the registers of the video signal generator (8). This video signal generator (8) scans the video memory (17), previously filled by the central control unit (1) through the data and addresses channel (2), to obtain the information through the data and addresses channel (18). The same video signal generator (8) will transform these information into digital video signals and will put them on the data channel (11) towards the D/A converter (12), as well as will generate the horizontal (9) and vertical (10) sync signal, which are sent both to the D/A converter (12), to interprete the data flow of channel (11), to the mode detector circuit (14), which stays in the video module, and to the circuitry of the monitor. For the timing of the video signals and synchronisms. the video signal generator (8) will use the pixel clock (6) as the time base, and the contents of its timing regi¬ sters, which are programmed by the program sequences (7), will define the characteristics of these timings. The mode detector circuit (14) arranges to generate the informa- tion (15) for the synchronization circuits and for the actuators of the cathode-ray beam (16), in order to select the operation ot higher frequences than the standard one.