WO1991010261A1 - Semiconductor interconnect structure utilizing a polyimide insulator - Google Patents

Semiconductor interconnect structure utilizing a polyimide insulator Download PDF

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Publication number
WO1991010261A1
WO1991010261A1 PCT/US1990/007401 US9007401W WO9110261A1 WO 1991010261 A1 WO1991010261 A1 WO 1991010261A1 US 9007401 W US9007401 W US 9007401W WO 9110261 A1 WO9110261 A1 WO 9110261A1
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WO
WIPO (PCT)
Prior art keywords
layer
polyimide
over
metal
aperture
Prior art date
Application number
PCT/US1990/007401
Other languages
French (fr)
Inventor
Maureen A. Anthony
Melanie Chow
Louis L-C Hsu
Rajiv V. Joshi
James F. White
Original Assignee
International Business Machines Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corporation filed Critical International Business Machines Corporation
Publication of WO1991010261A1 publication Critical patent/WO1991010261A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating

Definitions

  • the present invention is directed generally to semiconductor devices and processes and more particularly to an interconnection structure for semiconductor devices utilizing a polyimide insulator.
  • LSI and VLSI very large scale integrated circuit
  • Such electrical contacts and interconnections are formed in multiple levels, adjacent interconnect levels being separated by layers of insulating material. Vias or holes are formed through the insulating layers to accommodate contacts to the devices and contacts between levels.
  • Such interconnect structures are referred to in the art as "personalization” or "back-end metallization” .
  • U.S. patent no. 4,822,753 to Pintchovski et al. shows a device structure including an aluminum line connected to a suicided device region by a tungsten stud.
  • the tungsten stud which includes a titanium-nitride via liner, extends through an insulating layer comprised of an oxide, a nitride, or a glass.
  • Many techniques are known in the art whereby this structure can be extended upward (i.e. away from the surface of the semiconductor device) to provide multiple levels of wiring.
  • polyimides exhibits a low dielectric constant which makes it particularly desirable for use as the insulating layer in the above-described interconnect structures.
  • U.S. patent no. 4,560,436 to Bukhman et al. shows a process of forming tapered vias in a polyimide insulating layer.
  • Polyimides also suffer from certain disadvantages, not the least of which is the frangible nature of the material itself. Polyimides are particularly susceptible to contamination and subsequent breakdown caused by the materials and processes conventionally used in semiconductor processing. Many etchants, for example, are very detrimental to polyimide, as are many of the metals used to make the interconnections.
  • European patent application EPA 0 195 977 by Manley et al. shows a process wherein polyimide is used to provide planar insulating levels in a personalization structure for a field effect transistor (FET) .
  • FET field effect transistor
  • the polyimide insulator preferably covered with silicon dioxide, is etched to provide vias. The bottoms of these vias are treated to act as an activator, for example by roughening the polyimide, so as to attract selectively deposited tungsten.
  • This process of using polyimide insulator with selectively deposited tungsten is repeated to provide a multi-level interconnect structure.
  • the Manley et al. process suffers from several significant disadvantages, including the tendency for the tungsten metal to damage the exposed polyimide.
  • the use of selectively deposited tungsten is not readily adaptable to device surfaces of varying topology, as shallow vias will over-fill while deep vias are being filled.
  • Selective deposition of metals does not fill vias well, i.e. it tends to leave voids, for example due to out-gassing of the unprotected polyimide (termed
  • An object of the present invention is to provide a new and improved semiconductor interconnect structure utilizing polyimide as an insulator, and a method of manufacturing the same.
  • Another object of the present invention is to provide such a method and apparatus which is readily applicable for forming interconnections to device structures having features of varying heights.
  • a further object of the present invention is to provide such a method and apparatus which accommodates the use of different types of conductors at different levels in the structure.
  • a semiconductor structure comprising: a substrate of semiconductor material including a device region on a surface of the substrate whereat it is desired to provide a conductive contact; a layer of polyimide over the surface of the substrate; an aperture in the layer of polyimide exposing the device region; a lining of metal over the surface of the aperture; and, a stud of refractory metal filling the lined aperture so as to form a conductive contact to the device region.
  • a process comprising the steps of: providing a substrate of semiconductor material including a device region on a surface of the substrate whereat it is desired to provide a conductive contact; forming a layer of polyimide over the surface of the substrate; forming an aperture in the layer of polyimide to expose the device region; forming a lining of metal over the surface of the aperture in the polyimide layer; depositing a layer of refractory metal conformally over the substrate so as to substantially fill the lined aperture in the polyimide layer; and planarizing the refractory metal layer; whereby a conductive contact is formed to the device region.
  • FIGS. 1-9 are cross-sectional views showing consecutive steps in the fabrication of a field-effect transistor (FET) including an interconnect structure constructed accordance with the present invention.
  • FET field-effect transistor
  • FIGS. 10-12 are cross-sectional views highlighting a feature of the present invention utilized to overcome an undercutting problem encountered when etching vias in polyimide.
  • FIG. 1 shows a field-effect (FET) transistor 20 fabricated on a major surface 22 of an N ⁇ silicon substrate 24.
  • FET 20 includes highly doped P + source and drain regions 26, 28, respectively, these source and drain regions formed adjoining surface 22 and spaced by a channel region 30 of substrate 24 therebetween.
  • a gate structure is provided including a conductive gate contact 32 overlying and spaced from the surface of channel 30 by a thin layer 34 of insulating material.
  • Contact 32 comprises, for example, metal or doped polysilicon
  • insulator 34 comprises, for example, thermally grown silicon dioxide ⁇ SiO bombard) .
  • FET 20 further includes oxide sidewall spacers
  • FET 20 and electrically isolating the FET from other devices (not shown) formed in substrate 24.
  • FET 20 with its associated features comprises a conventional device in the art, and many methods are known for manufacturing the same.
  • the detailed method of constructing FET 20 with isolation region 40 does not comprise part of the present invention, and need not be detailed herein.
  • a thin layer 44 of an inorganic insulating material preferably silicon nitride (Si-,N.) , is deposited conformally over the structure described above, including FET 20 and field isolation region 40.
  • Layer 44 is formed, for example, to a thickness of about 2,000 Angstroms. Layer 44 functions to block out mobile ion contamination from subsequently deposited materials.
  • a layer 46 of polyimide is deposited over layer 44 to a thickness greater than that of the step-height 48 between the top of contact 32 and surface 22 - for example to a thickness of about 2.5 micrometers.
  • Polyimide 46 preferably comprises a thermally stable polyimide capable of sustaining high temperature operation in the range of about 450-500 degrees centigrade, for example PIQ L-100 as available from the Hitachi Corporation.
  • a layer 49 of epoxy or resin is spun in a conventional manner onto the surface of polyimide layer 46 so as to yield a plan- arized upper surface 48A.
  • the device of FIG. 2 is then subjected to a blanket etching process, for example a reactive ion etch (RIE) using oxygen plasma, which is continued through layer 49 and into layer 46 so as to planarize the top surface of poly ⁇ imide layer 46.
  • RIE reactive ion etch
  • polyimide layer 46 is shown with upper surface 46A planarized in the manner described above.
  • a layer 50 of inorganic insulating material for example comprising silicon nitride, silicon dioxide, or glass, is deposited onto the surface of layer 46 to a thickness of about 3,500 Angstroms.
  • layer 50 comprises an important feature of the present invention, functioning variously as: an etch stop, a polishing stop, and as a getterer to protect the underlying polyimide from damage by subsequent processing steps.
  • Via 54 extends from the surface of layer 50 downward through layers 50, 46, and 44, to expose a surface portion of gate contact 32. Vias 52 and 54 likewise extend downward through the same layers to expose surface portions of source and drain regions
  • Vias 52, 54, 56 are formed, for example, by using a CF. plasma to etch through layer 50, an oxygen plasma to etch through layer 46, and, after removing the photoresist mask, another CF. plasma to etch through the exposed portion of layer 44.
  • etching polyimide layer 46 with an oxygen plasma permits complete, and even over-etching without damage to underlying substrate
  • a thin layer 58 of a conductive material is deposited conformally over the structure.
  • Layer 58 is selected to form a diffusion barrier between layers 48, 50 and a subsequently deposited refractory metal, and preferably comprises a two layer structure: a first layer of titanium (Ti) , and a second level of titanium-nitri.de (TiN) .
  • Layer 58 can be formed, for example, by first sputtering titanium conformally over the device to a thickness of about 500 Angstroms, and then sputtering titanium-nitride conformally over the titanium to a thickness of about 500 Angstroms.
  • tungsten layer 60 is formed by chemical vapor deposition (CVD) of the tungsten at a temperature in the range of about 300-420 degrees centigrade and at a pressure in the range of about 5-50 Torr.
  • CVD chemical vapor deposition
  • This CVD process can utilize a conventional tungsten source gas, for example WFg+SiH 4 +H 2 .
  • tungsten layer 60 is able to fill vias 52, 54, and 56 evenly and without gaps, even when the vias have very high aspect ratios - i.e. on the order of 1:4.
  • inorganic layer 50 functions to protect polyimide layer 46 from the degrading and corrosive effects of the metal formation processes, particularly of the corrosive effects of the gas used in the CVD tungsten process.
  • Layer 58 functions to improve the adhesion of tungsten layer 60 to the device, and to lower the contact resistance of the tungsten to the underlying device regions.
  • FIG. 7A shows an alternate embodiment of the invention wherein layers 50 and 46 have been removed by etching and replaced with a silicon dioxide (or quartz) insulator 63.
  • Layers 46 and 50 can be re ⁇ moved, for example, by RIE processing with a CF./0 2 plasma.
  • Layer 63 can be deposited using a conventional chemical vapor oxide deposition (CVD) process, and then planarized using a conventional chemical-mechanical polishing process to yield the structure shown in FIG. 7A.
  • CVD chemical vapor oxide deposition
  • a thin layer 64 of a conductive material is deposited conformally over the device and used as an etch stop for a subsequently deposited, thicker layer 66 of conformally deposited conductive material. Layers 64 and 66 are required to have differing etch characteristics.
  • layer 64 can comprise sputter-deposited copper formed to a thickness of about 0.1 micrometers
  • layer 66 can comprise a multilevel structure including a first layer of sputter deposited Ti formed to a thickness of about 0.5 micrometers overlain by a second layer of sputter-deposited aluminum-copper alloy ( ⁇ lCu) formed to a thickness of about 0.5 micrometers.
  • ⁇ lCu sputter-deposited aluminum-copper alloy
  • Aperture 68 can be formed, for example, by using a BCl 3 , Cl 2 , CC1. RIE plasma to etch down to etch stop layer 64, and an HF dip to remove the exposed portion of layer 64.
  • metal lines 64A/66A, 64B/66B can be formed using a conventional lift-off process.
  • second interconnection level 70 including polyimide insulator 72 and metal-filled vias/studs 74, 76, and 78.
  • Via 76 extends through insulator 72 into contact with interconnect 66A (and hence FET gate contact 32)
  • vias 74 and 76 similarly extend into contact with interconnects 66A (and hence FET ⁇ ource region 26) and 66B (and hence FET drain region 28) , respectively.
  • each level being defined as one layer of polyimide insulator (i.e. layer 46) supporting metal-filled vias (i.e. vias 52, 54, 56) and overlying metal interconnects (i.e. interconnects 66A, 66B) .
  • FIG. 10 shows a,silicon substrate 80 supporting overlying, consecutive layers of silicon nitride 82, polyimide 84, and silicon nitride 86. (It will be appreciated that this is substantially the same insulator structure shown in FIG. 3 above.)
  • An aperture 88 is shown extending from the surface of layer 86 into contact with layer 82, the aperture having been over-etched with an O ⁇ plasma so as to form an undercut 90 underneath of masking silicon nitride layer 86.
  • a conventional photolithographic mask over layer 86 is understood, and not shown.
  • silicon nitride layer 86 is removed, simultaneously with the exposed portion of layer 82 in aperture 88, using, for example, a CF. RIE plasma etchant.
  • a barrier metal layer 92 and blanket tungsten deposition 94 are formed in the manner described above.
  • tungsten layer 94 is chemically-mechanically polished to the top of layer 84, providing filled via 94 ⁇ .
  • the desirable layer of inorganic is then reapplied, for example a layer 96 of silicon nitride, and further processing is continued in accordance with the present invention.
  • the present invention thus can accommodate over-etching of the vias with no significant changes in process or process complexity.
  • the interconnect structure provides significant advantages over the prior art structures, including:
  • the present invention has particular application in the manufacturing of semiconductor devices, including bipolar, FET, and bi-FET devices, and is particularly useful with very large scale integrated circuits (VLSI) requiring multiple levels of wiring to contact densely-packed devices.
  • VLSI very large scale integrated circuits

Abstract

A semiconductor structure is provided including a substrate of semiconductor material including a device region on a surface of the substrate whereat it is desired to provide a conductive contact. A planarized layer of polyimide is disposed over the surface of the substrate, and a layer of inorganic material is disposed over the polyimide layer. An aperture is formed in the layer of polyimide exposing the device region, and a lining of metal is formed over the surface of the aperture in the polyimide layer so as to provide a diffusion barrier. A layer of refractory metal fills the lined aperture in the polyimide layer so as to form a conductive contact to the device region.

Description

SEMICONDUCTOR INTERCONNECT STRUCTURE
UTILIZING A POLYIMIDE INSULATOR
The present invention is directed generally to semiconductor devices and processes and more particularly to an interconnection structure for semiconductor devices utilizing a polyimide insulator.
Background of the Invention
Semiconductor devices typically require the formation of electrical contacts and interconnections to device regions formed in substrates such as silicon or gallium arsenide. In current, large scale and very large scale integrated circuit (LSI and VLSI) technology, these electrical contacts and interconnections are formed in multiple levels, adjacent interconnect levels being separated by layers of insulating material. Vias or holes are formed through the insulating layers to accommodate contacts to the devices and contacts between levels. Such interconnect structures are referred to in the art as "personalization" or "back-end metallization" .
In the past, the insulating materials used in these interconnect structures were predominantly inorganic insulators such as silicon dioxide, silicon nitride, or glass. U.S. patent no. 4,822,753 to Pintchovski et al., for example, shows a device structure including an aluminum line connected to a suicided device region by a tungsten stud. The tungsten stud, which includes a titanium-nitride via liner, extends through an insulating layer comprised of an oxide, a nitride, or a glass. Many techniques are known in the art whereby this structure can be extended upward (i.e. away from the surface of the semiconductor device) to provide multiple levels of wiring.
It has been recognized for a period of time that the class of materials known as "polyimides" exhibits a low dielectric constant which makes it particularly desirable for use as the insulating layer in the above-described interconnect structures. U.S. patent no. 4,560,436 to Bukhman et al., for example, shows a process of forming tapered vias in a polyimide insulating layer. Polyimides, however, also suffer from certain disadvantages, not the least of which is the frangible nature of the material itself. Polyimides are particularly susceptible to contamination and subsequent breakdown caused by the materials and processes conventionally used in semiconductor processing. Many etchants, for example, are very detrimental to polyimide, as are many of the metals used to make the interconnections.
European patent application EPA 0 195 977 by Manley et al. shows a process wherein polyimide is used to provide planar insulating levels in a personalization structure for a field effect transistor (FET) . In Manley et al. the polyimide insulator, preferably covered with silicon dioxide, is etched to provide vias. The bottoms of these vias are treated to act as an activator, for example by roughening the polyimide, so as to attract selectively deposited tungsten. This process of using polyimide insulator with selectively deposited tungsten is repeated to provide a multi-level interconnect structure.
The Manley et al. process suffers from several significant disadvantages, including the tendency for the tungsten metal to damage the exposed polyimide. The use of selectively deposited tungsten is not readily adaptable to device surfaces of varying topology, as shallow vias will over-fill while deep vias are being filled. Selective deposition of metals does not fill vias well, i.e. it tends to leave voids, for example due to out-gassing of the unprotected polyimide (termed
"creep-up" formation) . Further, this selective deposition is limited in the metals with which it can be practiced. More specifically, it does not work well for such desirable interconnect metals as copper and aluminum. Manley et al. is also deficient in that it does not provide for any type of gettering of mobile ions.
Other examples using polyimide as an insulator in interconnect structures are shown in U.S. patents 4,702,792 to Chow et al. (assigned to the assignee of the present invention) , and 4,386,116 to Nair et al. Nair et al. shows the use of polyimide as an insulator in a multi-level interconnect structure, while Chow et al. shows a process of forming a multi-level interconnect structure by chemically-mechanically polishing a polyimide insulator.
No prior process is known to the present inven¬ tors which utilizes polyimide as a back-end insulator while maintaining the structural integrity of the polyimide material, optimizing its beneficial dielectric characteristics, and which is further adaptable to varying topologies and differing types of interconnect metals.
Summary of the Invention
An object of the present invention is to provide a new and improved semiconductor interconnect structure utilizing polyimide as an insulator, and a method of manufacturing the same.
Another object of the present invention is to provide such a method and apparatus which is readily applicable for forming interconnections to device structures having features of varying heights.
A further object of the present invention is to provide such a method and apparatus which accommodates the use of different types of conductors at different levels in the structure.
In accordance with the present invention there is provided a semiconductor structure comprising: a substrate of semiconductor material including a device region on a surface of the substrate whereat it is desired to provide a conductive contact; a layer of polyimide over the surface of the substrate; an aperture in the layer of polyimide exposing the device region; a lining of metal over the surface of the aperture; and, a stud of refractory metal filling the lined aperture so as to form a conductive contact to the device region.
In accordance with another aspect of the present invention, there is provided a process comprising the steps of: providing a substrate of semiconductor material including a device region on a surface of the substrate whereat it is desired to provide a conductive contact; forming a layer of polyimide over the surface of the substrate; forming an aperture in the layer of polyimide to expose the device region; forming a lining of metal over the surface of the aperture in the polyimide layer; depositing a layer of refractory metal conformally over the substrate so as to substantially fill the lined aperture in the polyimide layer; and planarizing the refractory metal layer; whereby a conductive contact is formed to the device region.
Brief Description of the Drawings
These and other features, objects, and advantages of the present invention will become apparent upon a consideration of the following detailed description of the invention when read in conjunction with the drawing Figures, in which:
FIGS. 1-9 are cross-sectional views showing consecutive steps in the fabrication of a field-effect transistor (FET) including an interconnect structure constructed accordance with the present invention; and
FIGS. 10-12 are cross-sectional views highlighting a feature of the present invention utilized to overcome an undercutting problem encountered when etching vias in polyimide.
Detailed Description of the Invention
Referring now to the drawings, FIG. 1 shows a field-effect (FET) transistor 20 fabricated on a major surface 22 of an N~ silicon substrate 24. FET 20 includes highly doped P+ source and drain regions 26, 28, respectively, these source and drain regions formed adjoining surface 22 and spaced by a channel region 30 of substrate 24 therebetween. A gate structure is provided including a conductive gate contact 32 overlying and spaced from the surface of channel 30 by a thin layer 34 of insulating material. Contact 32 comprises, for example, metal or doped polysilicon, while insulator 34 comprises, for example, thermally grown silicon dioxide <SiO„) .
FET 20 further includes oxide sidewall spacers
36, 38 covering the vertical edges of the gate structure, and a field oxide region 40 surrounding
FET 20 and electrically isolating the FET from other devices (not shown) formed in substrate 24. FET 20 with its associated features comprises a conventional device in the art, and many methods are known for manufacturing the same. The detailed method of constructing FET 20 with isolation region 40 does not comprise part of the present invention, and need not be detailed herein. In accordance with the present invention, a thin layer 44 of an inorganic insulating material, preferably silicon nitride (Si-,N.) , is deposited conformally over the structure described above, including FET 20 and field isolation region 40. Layer 44 is formed, for example, to a thickness of about 2,000 Angstroms. Layer 44 functions to block out mobile ion contamination from subsequently deposited materials.
A layer 46 of polyimide is deposited over layer 44 to a thickness greater than that of the step-height 48 between the top of contact 32 and surface 22 - for example to a thickness of about 2.5 micrometers. Polyimide 46 preferably comprises a thermally stable polyimide capable of sustaining high temperature operation in the range of about 450-500 degrees centigrade, for example PIQ L-100 as available from the Hitachi Corporation.
Referring now to FIG. 2 , in preparation for an etch-back planarization step, a layer 49 of epoxy or resin is spun in a conventional manner onto the surface of polyimide layer 46 so as to yield a plan- arized upper surface 48A. The device of FIG. 2 is then subjected to a blanket etching process, for example a reactive ion etch (RIE) using oxygen plasma, which is continued through layer 49 and into layer 46 so as to planarize the top surface of poly¬ imide layer 46.
Referring now to FIG. 3, polyimide layer 46 is shown with upper surface 46A planarized in the manner described above. Subsequent to the planarization of layer 46, a layer 50 of inorganic insulating material, for example comprising silicon nitride, silicon dioxide, or glass, is deposited onto the surface of layer 46 to a thickness of about 3,500 Angstroms. As will be discussed in further detail below, layer 50 comprises an important feature of the present invention, functioning variously as: an etch stop, a polishing stop, and as a getterer to protect the underlying polyimide from damage by subsequent processing steps.
Referring now to FIG. 4, conventional photolithographic masking (not shown) is used with anisotropic RIE processes to form vias 52, 54, and
56. Via 54 extends from the surface of layer 50 downward through layers 50, 46, and 44, to expose a surface portion of gate contact 32. Vias 52 and 54 likewise extend downward through the same layers to expose surface portions of source and drain regions
26 and 28, respectively. Vias 52, 54, 56 are formed, for example, by using a CF. plasma to etch through layer 50, an oxygen plasma to etch through layer 46, and, after removing the photoresist mask, another CF. plasma to etch through the exposed portion of layer 44. In accordance with yet another advantage of the present invention, etching polyimide layer 46 with an oxygen plasma permits complete, and even over-etching without damage to underlying substrate
24 or FET 20. Substantial over-etching of the polyimide, often desirable to insure good vias to features of varying step-heights or topography, can be accommodated by the present invention in accordance with a minor process variation as described with respect to FIGS. 10-12 below. Referring now to FIG. 5, a thin layer 58 of a conductive material is deposited conformally over the structure. Layer 58 is selected to form a diffusion barrier between layers 48, 50 and a subsequently deposited refractory metal, and preferably comprises a two layer structure: a first layer of titanium (Ti) , and a second level of titanium-nitri.de (TiN) . Layer 58 can be formed, for example, by first sputtering titanium conformally over the device to a thickness of about 500 Angstroms, and then sputtering titanium-nitride conformally over the titanium to a thickness of about 500 Angstroms.
Referring now to FIG. 6, a layer of refractory metal, preferably CVD tungsten (W) , is deposited over the surface of the structure to form a generally conformal layer 60 which fills vias 52, 54, and 56 leaving no gaps. In accordance with a key feature of the present invention, tungsten layer 60 is formed by chemical vapor deposition (CVD) of the tungsten at a temperature in the range of about 300-420 degrees centigrade and at a pressure in the range of about 5-50 Torr. This CVD process can utilize a conventional tungsten source gas, for example WFg+SiH4+H2. Within these temperature and pressure ranges, tungsten layer 60 is able to fill vias 52, 54, and 56 evenly and without gaps, even when the vias have very high aspect ratios - i.e. on the order of 1:4.
It is noted at this point that during the formation of layers 58 and 60, inorganic layer 50 functions to protect polyimide layer 46 from the degrading and corrosive effects of the metal formation processes, particularly of the corrosive effects of the gas used in the CVD tungsten process. Layer 58 functions to improve the adhesion of tungsten layer 60 to the device, and to lower the contact resistance of the tungsten to the underlying device regions.
Referring now to FIG. 7, a conventional chemical-mechanical polishing process is used to polish away layer 60 down to insulator layer 50, leaving discrete, metal stud contacts 60Λ, 60B, and 60C to source region 26, gate contact 32, and drain region 28, respectively. FIG. 7A shows an alternate embodiment of the invention wherein layers 50 and 46 have been removed by etching and replaced with a silicon dioxide (or quartz) insulator 63. Layers 46 and 50 can be re¬ moved, for example, by RIE processing with a CF./02 plasma. Layer 63 can be deposited using a conventional chemical vapor oxide deposition (CVD) process, and then planarized using a conventional chemical-mechanical polishing process to yield the structure shown in FIG. 7A. It will be appreciated that, regardless of which embodiment of the invention is utilized at this step in the process (i.e. the embodiment of FIG. 7 or 7A) , the remaining process steps described below are performed in an identical manner. Referring now to FIG. 8, a thin layer 64 of a conductive material is deposited conformally over the device and used as an etch stop for a subsequently deposited, thicker layer 66 of conformally deposited conductive material. Layers 64 and 66 are required to have differing etch characteristics. For example, layer 64 can comprise sputter-deposited copper formed to a thickness of about 0.1 micrometers, while layer 66 can comprise a multilevel structure including a first layer of sputter deposited Ti formed to a thickness of about 0.5 micrometers overlain by a second layer of sputter-deposited aluminum-copper alloy (ΛlCu) formed to a thickness of about 0.5 micrometers.
Continuing to describe the structure of FIG. 8, subsequent to the deposition of layers 64, 66, conventional photolithographic techniques are used to mask (not shown) the layers, and an anisotropic etchant is used to form an aperture 68 generally overlying FET gate contact 32 and exposing the surfaces of filled via 60B and adjoining portions of layer 50. Aperture 68 can be formed, for example, by using a BCl3, Cl2, CC1. RIE plasma to etch down to etch stop layer 64, and an HF dip to remove the exposed portion of layer 64. With aperture 68 thusly formed in layers 64, 66, discrete metal lines/interconnects/wires are formed to metal-filled vias 60A, 60C; i.e. interconnect 64A/66A to stud 60A, and interconnect 64B/66B to via 60C.
Alternatively to the process described above with respect to FIG. 8, metal lines 64A/66A, 64B/66B can be formed using a conventional lift-off process.
Referring now to FIG. 9, the above-described steps of forming a planarized layer of polyimide and forming metal-filled vias are repeated to form second interconnection level 70 including polyimide insulator 72 and metal-filled vias/studs 74, 76, and 78. Via 76 extends through insulator 72 into contact with interconnect 66A (and hence FET gate contact 32) , while vias 74 and 76 similarly extend into contact with interconnects 66A (and hence FET εource region 26) and 66B (and hence FET drain region 28) , respectively.
It will be appreciated that the above-described process of the present invention can be extended to provide further layers of metallization. It is theorized that the advantages of the present invention permit up to at least four levels of metallization to be formed over a device such as FET
20 on substrate 22, each level being defined as one layer of polyimide insulator (i.e. layer 46) supporting metal-filled vias (i.e. vias 52, 54, 56) and overlying metal interconnects (i.e. interconnects 66A, 66B) .
Referring now to the series of FIGS. 10-12, a significant advantage of the present invention is illustrated wherein it is necessary or desirable to over-etch a via so as to undercut the etching mask.
Such a situation is encountered, for example, where it is necessary to etch vias of differing aspect ratios.
FIG. 10 shows a,silicon substrate 80 supporting overlying, consecutive layers of silicon nitride 82, polyimide 84, and silicon nitride 86. (It will be appreciated that this is substantially the same insulator structure shown in FIG. 3 above.) An aperture 88 is shown extending from the surface of layer 86 into contact with layer 82, the aperture having been over-etched with an O^ plasma so as to form an undercut 90 underneath of masking silicon nitride layer 86. A conventional photolithographic mask over layer 86 is understood, and not shown.
In accordance with this feature of the present invention, silicon nitride layer 86 is removed, simultaneously with the exposed portion of layer 82 in aperture 88, using, for example, a CF. RIE plasma etchant. Referring to FIG. 11, a barrier metal layer 92 and blanket tungsten deposition 94 are formed in the manner described above.
Referring to FIG. 12, tungsten layer 94 is chemically-mechanically polished to the top of layer 84, providing filled via 94Λ. The desirable layer of inorganic is then reapplied, for example a layer 96 of silicon nitride, and further processing is continued in accordance with the present invention. The present invention thus can accommodate over-etching of the vias with no significant changes in process or process complexity.
There is thus provided a new and improved method for forming metal interconnects for semiconductor devices. Utilizing a polyimide insulator with protective inorganic coatings, and diffusion-barrier lined, refractory-metal-filled vias or studs, the interconnect structure provides significant advantages over the prior art structures, including:
- the ability to use a low dielectric insulator;
- etchability without damage to underlying structures; - the ability to provide reliable electrical connections to underlying features of varying step-heights;
- the substantial elimination of mobile ion contamination of the device substrate; and - the ability to use different dielectric materials if desired.
The present invention has particular application in the manufacturing of semiconductor devices, including bipolar, FET, and bi-FET devices, and is particularly useful with very large scale integrated circuits (VLSI) requiring multiple levels of wiring to contact densely-packed devices.
While the present invention has been shown and described with respect to specific embodiments, it is not thus limited. Numerous modifications, changes, and improvements will occur which fall within the spirit and scope of the invention.

Claims

What is claimed is:
1. A process comprising the steps of:
providing a substrate of semiconductor material including a device region on a surface of said substrate whereat it is desired to provide a conductive contact;
forming a layer of polyimide over said surface of said substrate;
forming an aperture in said layer of polyimide to expose said device region;
forming a lining of metal over the surface of said aperture in said polyimide layer;
depositing a layer of refractory metal conformally over said substrate so as to substantially fill the lined aperture in said polyimide layer; and
planarizing said refractory metal layer;
whereby a conductive contact is formed to said device region.
2. The method of claim 1 and further including the steps of forming a layer of inorganic material over the surface of said polyimide before said step of forming said aperture.
3. The method of claim 1 and further including the step of planarizing said layer of polyimide before said step of forming said aperture.
4. The method of claim 3 wherein said step of planarizing said layer of polyimide includes chemical-mechanical polishing of said layer of polyimide.
5. The method of claim 3 wherein said step of planarizing said layer of polyimide includes:
coating said layer of polyimide with an organic polymer; and
etching said organic polymer and said layer of polyimide.
6. The method of claim 1 wherein said step of planarizing said refractory metal layer includes chemically-mechanically polishing said refractory metal layer.
7. The method of claim 1 wherein said metal lining comprises a first layer of titanium (Ti) and a second layer of titanium-nitride alloy (TiN) .
8. The method of claim 1 wherein said refractory metal comprises tungsten (W) .
9. The method of claim 8 wherein said tungsten (W) is deposited by a process of chemical vapor deposition at a temperature in the range of 300-420 degrees centigrade and at a pressure in the range of 5-50 Torr.
10. The method of claim 1 and further including the step of forming multiple levels of polyimide having metal-filled vias to provide multiple levels of electrical interconnections.
11. A process comprising the steps of:
providing a substrate of semiconductor material including a device region on a surface of said substrate whereat it is desired to provide a conductive contact;
forming a layer of polyimide over said surface of said substrate;
planarizing the surface of said polyimide layer;
forming a layer of inorganic material over said polyimide layer;
etching said inorganic layer and said polyimide layer to form an aperture exposing said device region;
forming a lining of metal over the surface of said aperture in said polyimide layer;
depositing a layer of refractory metal conformally over said substrate so as to substantially fill the lined aperture in said polyimide layer; and
planarizing said refractory metal layer to remove said refractory metal from the surface of said layer of polyimide and leave said refractory metal in said via;
whereby a conductive contact is formed to said device region.
12. The method of claim 11 wherein said layer of inorganic material is comprised of silicon dioxide or silicon nitride or glass.
13. The method of claim 11 wherein said step of planarizing said layer of polyimide comprises the steps of:
coating said layer of polyimide with an organic polymer; and
etching said organic polymer and said layer of polyimide.
14. The method of claim 11 wherein said step of planarizing said layer of polyimide includes chemically-mechanically polishing said layer of polyimide.
15. The method of claim 11 wherein said metal lining comprises:
a layer of titanium (Ti) over said polyimide; and
a layer of titanium-nitride alloy (TiN) over said layer of titanium.
16. The method of claim 11 wherein said refractory metal comprises tungsten (W) .
17. The method of claim 16 wherein said step of forming said layer of tungsten comprises depositing said tungsten by a process of chemical vapor deposition at a temperature in the range of 300-420 degrees centigrade and a pressure in the range of 5-50 Torr.
18. The method of claim 16 wherein said step of planarizing said layer of refractory metal includes chemically-mechanically polishing said refractory metal.
19. The method of claim 11 and further including the step of forming a layer of conductive material over the surface of said layer of polyimide to provide at least one conductive wire to said stud.
20. The method of claim 11 wherein said step of forming a metal liner on the surface of said via includes the steps of:
forming said layer of metal conformally over the surface of said polyimide; and
removing said layer of metal except in said via.
21. The method of claim 11 and further including the step of forming multiple levels of polyimide with metal-filled vias to provide multiple levels of electrical interconnections.
22. A semiconductor structure comprising:
a substrate of semiconductor material including a device region on a surface of said substrate whereat it is desired to provide a conductive contact;
a layer of polyimide over said surface of said substrate;
an aperture in said layer of polyimide exposing said device region;
a lining of metal over the surface of said aperture;
a stud of refractory metal filling the lined aperture so as to form a conductive contact to said device region.
23. The structure of claim 22 and further comprising a layer of inorganic material over the surface of said polyimide outside of said aperture.
24. The structure of claim 22 wherein said metal lining comprises:
a layer of titanium over said polyimide; and
a layer of titanium nitride (TiN) over said layer of titanium.
25. The structure of claim 22 wherein said refractory metal comprises tungsten (W) .
26. The structure of claim 22 and further including at least one additional level of polyimide having metal-filled vias to provide multiple levels of electrical interconnections.
27. The structure of claim 22 and further including a region of conductive material over the surface of said polyimide layer to provide at least one conductive wire to said stud.
28. A semiconductor structure comprising:
a substrate of semiconductor material including a device region on a surface of said substrate whereat it is desired to provide a conductive contact;
a planarized layer of polyimide over said surface of said substrate;
a layer of inorganic material over said polyimide layer;
an aperture formed in said layer of polyimide exposing said device region;
a lining of metal over the surface of said aperture in said polyimide layer so as to provide a diffusion barrier;
a layer of refractory metal filling the lined aperture in said polyimide layer whereby said refractory metal layer forms a conductive contact to said device region.
29. The structure of claim 28 wherein said layer of inorganic material over said polyimide layer is selected from silicon dioxide or silicon nitride or glass.
30. The structure of claim 28 wherein said metal lining comprises:
a layer of titanium (Ti) over said polyimide; and
a layer of titanium-nitride alloy (TiN) over said layer of titanium.
31. The structure of claim 28 wherein said refractory metal comprises tungsten (W) .
32. The structure of claim 28 and further including a region of conductive material over the surface of said polyimide layer to provide at least one conductive wire to said stud.
33. The structure of claim 26 and further including a layer of inorganic material intermediate said polyimide and said surface of said semiconductor substrate.
34. The structure of claim 28 and further including at least one additional layer of polyimide having metal filled vias over the surface of said polyimide layer to provide multiple levels of electrical interconnections.
PCT/US1990/007401 1990-01-04 1990-12-13 Semiconductor interconnect structure utilizing a polyimide insulator WO1991010261A1 (en)

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