WO1991009460A1

WO1991009460A1 - Low inductance converter phase assembly

Info

Publication number: WO1991009460A1
Application number: PCT/US1990/006560
Authority: WO
Inventors: Thomas Sutrina; Lawrence E. Crowe; Mark W. Metzler
Original assignee: Sundstrand Corporation
Priority date: 1989-12-20
Filing date: 1990-11-08
Publication date: 1991-06-27

Abstract

Previous electronic circuit assemblies have exhibited unnecessarily high parasitic inductance. In order to overcome this problem, an apparatus in accordance with this invention is provided with a transistor (24) having power terminals, and first and second diodes (28, 29). The apparatus comprises a first bus (20a) connected to the first diode (28) and one of the power terminals, and a second bus (16a) connected to the second diode (29), the first and second buses (20a, 16a) comprising parallel plates having substantially the same configuration.

Description

LOW INDUCTANCE CONVERTER PHASE ASSEKSLY

Field and Background of the Invention

This invention relates to electronic circuit assemblies, and more particularly to an improved arrangement of the components of an assembly which reduces parasitic inductance. The arrangement of the electronic components and the accompanying hardware (such as the conductors) of a circuit has a significant effect on the parasitic inductance of the circuit. Parasitic inductance is present in conductors between the components, for exa - pie, and the amount depends upon the type of conductor (flat plate, round wire, etc.) and its length. The designer normally arranges the parts so as to reduce the inductance to a minimum because its existence in a switch¬ ing circuit can produce voltage spikes at the instant of switching, called ringing. For example, in a transistor switch circuit having substantial parasitic inductance, at the time that the transistor is turned off, ringing or voltage spikes appear across the transistor. The potentially damaging effects of the voltage spikes are avoided in the prior art by connecting a snubber circuit across the transistor, but it would be more expedient to reduce the amount of the parasitic inductance and there¬ by the magnitude of the voltage spikes. Such a reduc¬ tion would enable the use of smaller circuit components or the capability for higher currents.

Porst et al. U.S. patent No. 4,816,984 shows an assembly of the components of an inverter circuit, wherein the components are arranged on flat substrate, the conductors being arranged to induce feedback currents. Compression bonded circuit assemblies are also known in the prior art. For example, L.E. Crowe et al. U.S. Patent No. 4,830,979, and the prior art and the pending applications cited therein, shows a hermetically sealed compression bonded assembly of an inverter switch. Further, Thomas S. atos pending patent application

Serial No. , filed on the same date as the present application and titled "Inverter Switch With Par¬ allel Free-Wheel Diodes" discloses a transistor switch circuit having reduced parasitic inductance. The dis- closure of the above Latos application is incorporated herein by reference.

Summary of the Invention

Apparatus in accordance with this invention is for use in a circuit including a transistor having power terminals, and first and second diodes. The apparatus comprises first bus means connected to said first diode and one of said power terminals, and second bus means connected to said second diode, said first and second bus means comprising parallel plates having substantial¬ ly the same configuration.

Brief Description of the Drawings

The invention will be better understood from the following detailed description taken in conjunction with the accompanying- figures of the drawings, wherein: FIG. 1 is a schematic diagram of an electric circuit of the general character disclosed in the-above- referenced Latos application;

FIG. 2 is an exploded perspective view of the structural parts of apparatus incorporating the invention; and FIG. 3 is an exploded perspective view of an alternative embodiment incorporating the invention.

Detailed Description of the Drawings

With reference first to FIG. 1, there are illustrated two transistor switch modules 10 and 11, the module 10 being referred to herein for convenience as the upper module and the module 11 being referred to herein for convenience as the lower module. The two modules 10 and 11 may form, for example, one phase of a three-phase DC to AC inverter which operates in the manner described in more detail in the co-pending T. Latos patent application referred to above. In the circuit described in the Latos application, however, each module includes a single transistor, whereas in the present construction a Darlington transistor arrangement is provided. The general operation of the two circuits is, however, similar. With reference first to the upper module 10, it includes a driver transistor 12 and two parallel connec¬ ted driven transistors 13 and 14. The collectors of the three transistors 12-14 are connected to a positive DC bus 16, and the emitters of the two driven transistors 13 and 14 are connected to a load bus 17. The emitter of the driver transistor 12 is connected to the bases of the two driven transistors 13 and 14, and the base of the driver transistor 12 receives a control signal from an inverter control circuit (not shown). A freewheel or antiparallel diode 18 is connected across the power terminals of the driven transistors 13 and 14, and a series diode 19 is connected between the emitters of the driven transistors and a negative DC bus 20. The operation of that part of the circuit including the transistor 14, the diode 18 and the diode 19 is described in detail in the above-referred-to Latos patent application, and the operation of the Darlington transistor arrangement shown in FIG. 1 herein is essentially the same. The circuit of the lower module 11 is similar to that of the upper module 10 and includes a driver transistor 22, driven transistors 23 and 24, a parallel diode 28 and a series diode 29. As shown in FIG. 1, the series diode 29 is connected between the buses 16 and 17, whereas- the transistors 23 and 24 are connected between the buses 17 and 20. The base of the driver transistor also receives a control signal from a control circuit (not shown). This circuit operates essentially the same as the module 10. With reference to the embodiment of the invention illustrated in FIG. 2, there is provided a sandwich-type arrangement of two heat sinks 31 and 32 and the components of the two modules 10 and 11 which are compressed between the two heat sinks. The four components 12-14, 18 and 19 are hermetically sealed in capsules, and the undersides of the capsules for the three transistors are connected to the emitters. The two driven transistors 13 and 14 rest directly on the upper surface of the metal heat sink 32 which forms the load bus 17, and a disk-shaped thin sheet of insulation 38 separates the heat sink 32 from the emitter of the driver transistor 12. The emitter of the transistor 12 is electrically connected in a conventional manner (not illustrated) to the bases of the two transistors 13 and 14. The cathode of the series diode 19 also engaςres the upper plate of the heat sink 32, and the anode of the parallel diode 18 is connected to the heat sink 32 by, for example, screwing the casing of the diode 18 into the heat sink. Recesses 42 and 62 are formed in the upper plate of the heat sink and receive the components 12-14 and 19 in order to locate them properly.

The collectors of the three transistors 12, 13 and 14 are connected (through the upper sides of the capsules) to the collector bus 16 which overlies and makes contact with the capsules. The collector bus 16 has three lobes 43 which are circular and located to overlie the upper sides of the three transistor cap¬ sules. The lobes 43 are attached by connecting portions 44; a terminal portion 46 of the bus 16 is connected to one of the lobes 43 and extends to the periphery of the assembly for connection to an external circuit (not shown) . Bus portions 44 and 46 are flexible to allow for dimensional variation without changing clamping loads or distribution on the transistors. All connections are similarly flexible.

Located above the collector bus 16 is a sheet 48 of insulation which also has three lobes 49 located over the lobes 43, connecting portions 50 and a portion 51 which extends over the terminal portion 46 of the collector bus 16. The insulation sheet 48 is sandwiched between the collector bus 16 and a diode bus 20 which also has three lobes 54 located over the lobes 43, two connecting portions 55 located over the connecting por- tions 44, and a terminal portion 56 which overlies the terminal portion 46. While the diode bus 20 overlies the collector bus 16, they are insulated from each other by the sheet 48. The diode bus 20 further includes a diode lobe 58 which is attached to the lobes 54 by connecting portions 59. The diode lobe 58 is located over the series diode 19 and has a contact 61 integral with it which engages the anode of the series diode 19. Above the bus 20 is located a sheet 63 of insula¬ tion which separates the parts of the upper module 10 from the parts of the lower module 11. Sheet 63 is preferably fastened by means (not shown) to heat sink 32 so that the elements of module 10 will stay together during handling.

With reference once again to the parallel diode 18, as previously mentioned, the anode of the diode 18 is electrically connected to the heat sink 32. The cathode of the diode 18 is electrically connected by a conductor 64 to the collector bus 16.

With regard to FIGS. 1 and 2, it will be apparent from the foregoing that the heat sink 32 forms the load bus 17 in FIG. 1, the terminal portion 46 of the collector bus 16 forms the plus DC bus 16, and the terminal portion 56 of the diode bus 20 forms the negative DC bus 20. The two buses 16 and 20 are formed by thin parallel sheets or plates of metal and they are separated by a thin sheet 48 of insulation, the buses 16 and 20 and the sheet 48 having similar configurations or shapes. Further, the sheets 16 and 20 are parallel with and close to the upper surface of the heat sink 32, the recesses 42 and 62 also serving to reduce the distance of the bus 16 from the heat sink.

The lower module 11 is between the previously referred-to heat sink 31 and the upper module 10 and has a construction similar to the module 10. The collectors of three transistors 22, 23. and 24 and the anode of a series diode 29 are received in recesses 76 formed in the metal heat sink 31. A lower emitter bus 20a has lobes 79 which overlie the emitter sides of the three transistors 22-24, but an insulation disk 81 separates the emitter bus 20a from the emitter side of the driver transistor 22. The heat sink 31 corresponds or forms the load bus 17, and a terminal portion 83 of the lower emitter bus 20 forms the negative DC bus 20a in FIG. 1. A lower diode bus 16a is separated from the emitter bus 20a by a thin sheet 87 of insulation, the two buses 20a and 16a and the sheet 87 having generally similar configurations as shown in FIG. 2 and as des¬ cribed in connection with the upper module 10. The diode bus 16a further includes a diode lobe and contact 87 which makes electrical contact with the cathode of the series diode 29. A sheet of insulation 89 covering the lower side of the diode bus 16a separates the components of the lower module 11 from those of the upper module 10. The lower module 46 further includes the parallel diode 28 which has its cathode electrically connected to the heat sink 31 by screwing the casing of the diode into the heat sink. A conductor 92 electrically connects the emitter bus 20a with the anode of the parallel diode 28.

It will again be noted that the lower diode bus 16a and the lower emitter bus 20a have similar configur¬ ations and overlie each other, but of course they are separated by the thin sheet 87 of insulation. It will further be noted that the two buses 20a and 16a are flat, thin electrical conductors. All three sheets contain strain relieving features between lobes, like buses 16, 20 and insulation 48 in module 10. Below the bus 16a is located a sheet 89 of insulation which separates and constrains the elements of the lower module 11 by being fastened by means (not illustrated) to the heat sink 31.

The two heat^' sinks 31 and 32 are electrically connected and mechanically secured together by four bolts 96, which extend through bolt holes 97 formed in the two heat sinks and bolt holes 98 formed in the two sheets 63 and 89. Washer-like compression springs 99 are on the center axes of the four semiconductor columns and located between the sheets 86 and 89 of insulation by recesses in the sheets. When the nuts 100 are tightened onto the bolts 96, a high degree of compress¬ ion is formed on the electrical components, which are sandwiched between the two heat sinks, and on the compression springs 99 which serve to limit and maintain the compression. The bolts 96 and the nuts 100 also establish electrical contact between the two heat sinks. Externally of the assembly shown in FIG. 2, the upper emitter bus 20a is electrically connected to the lower diode bus 20 and to the negative DC bus, and the lower collector bus 16 is electrically connected to the upper diode bus 16a and to the positive DC bus.

The emitters of the two transistors 13 and 14 of the upper module 10, for example, the parallel diode 18 and the series diode 19 are all connected directly to the surface of the heat sink 32, thereby making them physically and electrically close to each other and minimizing the electrical path between these compon¬ ents. By minimizing the path, the parasitic inductance between the components is substantially reduced. Fur- ther, the parallel diode 18 is also mounted on the heat sink 32 and is physically and electrically close to the collector bus 16 and the two transistors 13 and 14, again thereby reducing parasitic inductance. The reduc¬ tion in the parasitic inductance is important for the reasons given in the Latos et al. application.

A further advantage of the configuration is the fact that the configuration or outline of the diode bus 20 is similar to or matches that of the collector bus 16, and the emitter bus 17 is close to the collector and diode buses 20, 16. Further, bus 17 is connected- at locations 17b to the circuit which is in close proximity to the circuit connections for buses 16, 20. As a con¬ sequence, during operation of the switch at the time that the transistors 13 and 14 are switched off and the field in the conductors leading to the collectors of these transistors is collapsing, the current flow is transferred to the conductor leading to the series diode 19 and the field starts to build up in the latter con¬ ductor. The current field in the emitter bus also switches from transistors to diode and is in opposite direction to those in buses 16 and 20. The close prox¬ imity of the three buses and the collapse of one field simultaneously with the build up of the other field results in a cancellation of nearly all of the induct- ance. Since the buses 16 and 20 are laminated one on top of the other with a thin insulation between them, the distance between the buses at any point is less than the width of the buses, and consequently current in either bus will create the same magnetic field. Since the cur- rent switches between the two buses at the instant of switching, the field in the area where the buses overlap does not change. Further, the series diode is located close to the driven transistors and as equal distant to them as possible. Also the emitter bus 17, being the heat sink 32, has a width much greater than the distance between buses 20 and 16, so the fields of the three buses are similar in magnitude at any point and signi¬ ficant cancellation occurs. The result is very low apparent inductance and even less apparent inductance differences between the two driven transistors 13 and 14.

Still another advantage results from the use of thin, flat conductors for the buses 16, 20, 16a and 20a. At the instant when a driven transistor is turned off, any parasitic inductance in the circuit produces the previously mentioned ringing or voltage spikes, which are high frequency voltage signals. Since the buses are very thin and flat, skin effect resistance in the buses is substantially reduced. Bus 17 also being a plate structure receives the above-discussed advantages plate structure receives the above-discussed advantages but to a lesser degree.

The foregoing comments, of course, apply to both modules. In the event that only a single transistor is provided instead of the Darlington configuration shown on the drawings, the drive transistor 12 (of the lower module 10, for example) and one of the two driven transistors 13 and 14 may be removed and replaced by spacers made of insulating material. The control signal would then be connected to the base of the remaining transistor, and the operation of the circuit and the foregoing described advantages would be the same as described above and in the T. Latos application. The embodiment of the invention shown in FIG. 2 is advantageous and preferred in a situation where low volume production is anticipated; further, it is rela¬ tively easy to service. The embodiment shown in FIG. 3 is advantageous and preferred for high volume production and where servicing is not expected to be a problem. In FIG. 2, the transistors and the diodes are mounted in separate hermetically sealed components, whereas in FIG. 3, a hermitically sealed compartment or enclosure is formed around unsealed components. FIG. 3 includes the structure for a single module and in this example the lower module 11 is illus¬ trated. It comprises a metal pan 110 having a flat rectangular section 112 and an upraised rim 113. The collectors of a driver transistor 115 and two driven transistors 116 and 117 are placed on the section -112, and the cathode of a series diode 118 is also placed on the section 112. Further, the anode of a parallel diode 119 is electrically connected to the section 112 as by cold welding, sodering or brazing. Annular insulators 120 around the transistors 115-117 separate them, and metal disks 21, 22 and 23 are placed on the upper sides (the emitters) of the three transistors. The transistors consist of a brazed assem¬ bly of a metal disk on silicon, an etched metal plate indexed to the silicon and a metal washer. Slots 126 are formed in the disks 121-123 to the centrally located base terminals 127 of the transistors, and prongs 124 extend through the slots and connect the bases of the two driven transistors 116 and 117 with the emitter disk 123 of the driver transistor 115. Another prong 128 connects with the base of the driver transistor 115, and a conductor (not shown) connects the prong 128 with a control circuit.

An emitter bus 131 overlies the three trans- istors 115 to 117 and includes three disk lobes 132, 133 and 134 and connecting portions 136. The lobes 132 and 133 are electrically connected to the disks 121 and 122 and to the emitters of the driven transistors 116 and 117, but an insulation disk 137 separates the lobe 134 from the emitter disk 126 of the driver transistor 115. Holes 138 are formed at the centers of the lobes 132 to 134 and the disk 137, and spring assemblies 139 extend through the holes 138 and load the base con¬ tacts 140 at the ends of the prongs 124 and 128. The emitter bus 131 is connected by a conductor 142 to the anode of the parallel diode 119 which has its cathode secured to the pan 110.

A diode bus 145 overlies the emitter bus 131 but is separated therefrom by an insulation sheet 146. The bus 145 and the sheet 146 have lobes 147 and L48, respectively, which correspond in shape to that of the lobes 132-134 of the emitter bus 131. The diode bus 145 further includes a diode contact 149 which is electric¬ ally connected to the lobes 147, the contact 149 being located to engage the cathode side of the series diode 118. A spacer 151 of insulation surrounds the diode 118 and the contact 149 and separates them from the other parts.

The pan 110 forms the load bus 17 in FIG. 1, the emitter bus 131 includes a terminal portion 152 which is connected to the negative DC bus 20a, and the diode bus 145 includes a terminal portion 153 which is connected to the positive DC bus 16a.

Above the diode bus 145, a sheet 154 of insulation separates the bus 145 from a metal lid or cover 155. The transistors, buses, etc. are mounted on the pan 110 and then the edges of the lid 155 are connected as by cold welding to the rim 113 of the pan 110 to form a portion of the welding of a hermetically sealed enclosure.

In practice, another assembly similar to that described above, which represents the upper module 10, but inverted, is positioned above the lid 155, and the two assemblies are secured tightly together by bolts and heat sinks (not shown) similar to the bolts 96 and heat sinks 31 and 32. Impressions or recesses 156 are formed in lid 155 in order to properly located the spring 157 on the axes of the transistors and the diodes. These springs 157, like spring 99, when compressed provide clamping force for the semiconductors to operate and maintain the load within required limits.

The apparatus of FIG. 3 further includes assemblies 161 of hermetic contacts which are mounted hermetically by welding on the pan 110 and extend through openings 162, the contact assemblies being electrically connected to the buses 131 and 145. A control circuit 163 may also be mounted on the pan 110 and be electrically connected to the base 128 of the driver transistor 115, the connector, emitter, and base buses of transistors 116 and 117, and to one of the contact assemblies 161. Tubular spacers 164 are pre¬ ferably mounted around the holes for the previously mentioned bolts which compress the components between the pan and the lid, the spacers serving to limit the amount of compression. The spacers 164 are integral to the pan 110 (hermetic) and hermetically cold welded to the lid 155 at the edge of the holes 165. This completes the hermetic enclosure.

In the embodiment of FIG. 3, the buses are again close together and parallel, and the buses 131 and 145 have similar configurations.

It will be apparent from the foregoing that a novel and improved assembly of electrical parts has been provided. The semiconductor components (the transistors and the diodes) are physically and electrically close to each other, thereby reducing the lengths of the electri¬ cal conductors. The buses are formed by thin, flat, parallel sheets of metal and have similar configura¬ tions, which improve the operating characteristics of the circuit.

The embodiment shown uses transistors but other compression bonded semiconductors that are controllable may be used, such as 1GBT, GTO, etc.

Further, the Darlington configuration shown only uses two semiconductors and one compression diode. Additional semiconductors and diode may be used by changing the angles between the buses but maintaining the symmetry about the driving semiconductor.

Further, as shown by diodes 18, 28 and 119, some of the semiconductors do not have to be compression bonded. Typical in some circuits, the driver semicon¬ ductor is smaller and is available in noncompression bonded forms. Also, this semiconductor does not have to be of the same family of semiconductors.

Claims

What Is Claimed Is:

1. Apparatus for use in a circuit including a transistor having power terminals, and first and second diodes, said apparatus comprising first bus means con¬ nected to said first diode and one of said power term¬ inals, and second bus means connected to said second diode, said first and second bus means comprising par¬ allel plates having substantially the same configuration.

2. Apparatus as set forth in Claim 1, and further comprising a thin sheet of insulation, said parallel plates being separated only by said thin sheet.

3. Apparatus as set forth in Claim 2, wherein said parallel plates and said thin sheet are substan¬ tially flat.

4. Apparatus as set forth in Claim 1, and further comprising a third bus means connected between said transistor and said second bus means, said third bus means comprising a plate which is substantially parallel with said parallel plates.

5. Apparatus comprising at leas^'t one trans¬ istor having power terminals, a first diode, a second diode, first and second transistor buses, and a diode bus, said transistor being connected between said first and second transistor buses, said first diode being connected in parallel with said power terminals of. said transistor, said second diode being connected in series with said power terminals of said transistor and between said diode bus and one of said transistor buses, said two transistor buses and said diode bus comprising flat plates.

6. Apparatus as set forth in Claim 1, wherein said diode bus has a configuration similar to that of said one transistor bus.

7. A low inductance assembly, comprising a plate, first and second diodes and at least one transistor positioned on said plate, a first bus in electrical contact with said transistor and with said first diode, and a second bus in electrical contact with said second diode, said plate and said first and second buses being substantially parallel and closely adjacent each other.

8. Apparatus as set forth in Claim 7, wherein said plate and said first and second buses are substan¬ tially flat.

9. An assembly as set forth in Claim 8, wherein said first and second buses have similar configurations.