WO1991009395A1 - Agencement de circuit pour l'attaque d'un dispositif d'affichage a cristaux liquides avec des elements d'image disposes en trame - Google Patents

Agencement de circuit pour l'attaque d'un dispositif d'affichage a cristaux liquides avec des elements d'image disposes en trame Download PDF

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Publication number
WO1991009395A1
WO1991009395A1 PCT/DE1990/000855 DE9000855W WO9109395A1 WO 1991009395 A1 WO1991009395 A1 WO 1991009395A1 DE 9000855 W DE9000855 W DE 9000855W WO 9109395 A1 WO9109395 A1 WO 9109395A1
Authority
WO
WIPO (PCT)
Prior art keywords
counter
frequency
horizontal
circuit arrangement
flip
Prior art date
Application number
PCT/DE1990/000855
Other languages
German (de)
English (en)
Inventor
Werner Wiedemann
Dieter Faber
Uwe Hovestadt
Original Assignee
Robert Bosch Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch Gmbh filed Critical Robert Bosch Gmbh
Publication of WO1991009395A1 publication Critical patent/WO1991009395A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
    • H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
    • H04N3/12—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by switched stationary formation of lamps, photocells or light relays
    • H04N3/127—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by switched stationary formation of lamps, photocells or light relays using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof

Definitions

  • Circuit arrangement for driving a liquid crystal display device with picture elements arranged in a grid
  • the invention relates to a circuit arrangement according to the type of the main claim.
  • Liquid crystal display devices in which the picture elements are arranged in a grid pattern are increasingly being used to reproduce video signals.
  • a considerably more complicated control is required in order to supply the corresponding instantaneous value of the video signal to each picture element. It is therefore for different
  • LCD displays Liquid crystal display devices, hereinafter referred to as LCD displays, have become known as integrated control circuits (controllers).
  • a control circuit of this Art is offered by Hitachi under the type designation HD 66840 and is designed to control TFT displays (thin film transistor displays).
  • Integrated control circuits for LCD displays are supplied with video signals - in the case of color reproduction, the color value signals R, G, B.
  • the control circuit requires horizontal-frequency and vertical-frequency synchronous pulses. Both can be supplied, for example, from a graphics card (for example EGA) from a personal computer.
  • the control circuit also requires a clock signal (hereinafter referred to as the system clock) and a timing signal which essentially defines the beginning of each line and the picture.
  • the object of the present invention is to provide a circuit arrangement for driving a liquid crystal display device, in which the system clock and the timing signal are generated in such a way that a constant, image-correct position of the image on the LCD display is ensured.
  • the circuit arrangement according to the invention with the characterizing features of the main claim has the advantage that a system clock and a timing signal can be derived with little effort.
  • Fig. 1 is a block diagram of the embodiment
  • Embodiment according to FIG. 1 occurring signals.
  • an LCD display 1 is connected via a plurality of parallel lines 2 to an integrated control circuit 3, to which a static read-write memory 3 'is assigned for temporary storage.
  • the color value signals R, G and B are fed to this via inputs 4, 5, 6.
  • the control circuit 3 receives horizontal frequencies and vertical frequency synchronizing pulses H, V via inputs 7, 8.
  • a clock signal CLK and a timing control signal DTMG are required to operate the control circuit 3. Both signals are derived using the circuits described below.
  • a controllable oscillator 11 is provided for the clock signal CLK, which oscillates at a frequency of 14.3 MHz.
  • the frequency of the clock signal is controlled with the aid of a control voltage which is generated by a phase comparison circuit 12, to which the horizontal frequency synchronizing pulse H and the output signal of a frequency divider 13 are supplied.
  • the circuits 11, 12 and 13 represent a phase and frequency locked loop (PLL) which causes an integer ratio n between the frequency of the clock signal CLK and the horizontal frequency.
  • the timing control signal DTMG comprises a horizontal frequency component and a vertical frequency component, which are each generated with the aid of an 8-bit down counter 14, 15 and a D flip-flop 16, 17.
  • the counter 14 is clocked with the clock signal CLK, while H pulses are inverted with the aid of an inverter 9 and fed to an input PE.
  • An output TC of the down counter 14 is connected to the clock input CP of the D flip-flop 16, the reset input RD of which receives H pulses.
  • the D input receives operating voltage (logical 1).
  • the output Q of the D flip-flop 16 is connected to a further input TE of the counter 14 and to an input of a non-switching circuit 18, which together with a further inverter 19 forms an switching circuit.
  • the counter 15 and the D flip-flop 17 act together in the same way, the counter 15 being clocked with inverted horizontal-frequency synchronizing pulses H. Inverted vertical frequency synchronizing pulses V are fed to the PE input of the counter 15 with the inverter 10.
  • the counter 14 can be preset to a value Z via inputs PO to P7, for which purpose each of the inputs is connected on the one hand to the operating voltage (logic 1) via a resistor 20 and can be supplied with ground potential via a switch 21.
  • the counter 15 can be preset using the resistors 22 and the switches 23.
  • Integrated counters of the type 74 HC 103 are preferably suitable as counters 14, 15. The generation of the timing control signal DTMG is explained below using the circuit diagram and the timing diagrams shown in FIG. 2.
  • Line a) shows inverted horizontal-frequency synchronizing pulses H
  • line b) the output signal TC of the counter, which assumes the value 0 at the counter reading 0 and the value 1 during all other counter readings.
  • Line c) represents the output signal of the D flip-flop 16.
  • the supply of the output signal of the D flip-flop in the input TE of the counter 14 has the effect that this is released if the value 1 is also supplied to the input PE. This is the case with the trailing edge of the pulse H (highlighted by an arrow in FIG. 2).
  • the counter 14 counts down from the counter reading Z in time with the clock signal CLK.
  • the signal at the output TC jumps to 0 for a period of the clock signal CLK and clocks with the subsequent positive edge (indicated by the arrow) the D flip-flop 16, which thereby has the value at the D input, namely 1 takes over.
  • the input TE also receives the value 1 and blocks the counter until the D flip-flop 16 is reset by the next pulse H.
  • the counter 15 and the D flip-flop 17 are used to generate the vertical frequency component of the timing signal DTMG.
  • the AND combination of the two components creates a signal that assumes the value 1 during the so-called active lines, i.e. if the video signals contain valid information.

Abstract

Dans le cas d'un agencement de circuit pour l'attaque d'un dispositif d'affichage à cristaux liquides comportant des éléments d'image disposés en trame, où des signaux vidéo (R, G, B) et des impulsions de synchronisation (H, V) à fréquence de ligne et à fréquence de trame peuvent être amenés à un circuit de commande intégré, un oscillateur pilotable comportant un circuit comparateur de phases et un diviseur de fréquence est prévu pour la dérivation d'un signal d'horloge. En outre, un signal de rythme (DTMG) peut être amené au circuit de commande, ledit signal prenant essentiellement pendant les lignes actives des signaux vidéo un premier niveau logique et, pendant les impulsions de synchronisation à fréquence de ligne et à fréquence de trame et les intervalles de temps prédéterminés y consécutifs, un second niveau logique.
PCT/DE1990/000855 1989-12-09 1990-11-10 Agencement de circuit pour l'attaque d'un dispositif d'affichage a cristaux liquides avec des elements d'image disposes en trame WO1991009395A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3940750A DE3940750A1 (de) 1989-12-09 1989-12-09 Schaltungsanordnung zur ansteuerung einer fluessigkristall-anzeigevorrichtung mit rasterfoermig angeordneten bildelementen
DEP3940750.0 1989-12-09

Publications (1)

Publication Number Publication Date
WO1991009395A1 true WO1991009395A1 (fr) 1991-06-27

Family

ID=6395147

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1990/000855 WO1991009395A1 (fr) 1989-12-09 1990-11-10 Agencement de circuit pour l'attaque d'un dispositif d'affichage a cristaux liquides avec des elements d'image disposes en trame

Country Status (2)

Country Link
DE (1) DE3940750A1 (fr)
WO (1) WO1991009395A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5854615A (en) * 1996-10-03 1998-12-29 Micron Display Technology, Inc. Matrix addressable display with delay locked loop controller

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4275421A (en) * 1979-02-26 1981-06-23 The United States Of America As Represented By The Secretary Of The Navy LCD controller
JPS60158780A (ja) * 1984-01-27 1985-08-20 Sony Corp 表示装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4275421A (en) * 1979-02-26 1981-06-23 The United States Of America As Represented By The Secretary Of The Navy LCD controller
JPS60158780A (ja) * 1984-01-27 1985-08-20 Sony Corp 表示装置

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Patent Abstracts of Japan, Band 9, Nr., 328 (E-369), 24. Dezember 1985; & JP-A-60158780 (SONY KK) 20. August 1985 *
Society for Information Display - International Symposium, Digest of Technical Papers, Band XVIII, Mai 1987, New Orleans, Louisiana, US, Palisades Institute for Research Services, Inc., (New York, US), A. Kompolt: "Video to LCD interface (VLI) IC converts video signals into signals suitable for LCDs", Seiten 416-418 *

Also Published As

Publication number Publication date
DE3940750A1 (de) 1991-06-13

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