WO1991009395A1 - Circuit arrangement for controlling a liquid crystal display device with pixels in a grid array - Google Patents

Circuit arrangement for controlling a liquid crystal display device with pixels in a grid array Download PDF

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Publication number
WO1991009395A1
WO1991009395A1 PCT/DE1990/000855 DE9000855W WO9109395A1 WO 1991009395 A1 WO1991009395 A1 WO 1991009395A1 DE 9000855 W DE9000855 W DE 9000855W WO 9109395 A1 WO9109395 A1 WO 9109395A1
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WIPO (PCT)
Prior art keywords
counter
frequency
horizontal
circuit arrangement
flip
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PCT/DE1990/000855
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German (de)
French (fr)
Inventor
Werner Wiedemann
Dieter Faber
Uwe Hovestadt
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Robert Bosch Gmbh
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Publication of WO1991009395A1 publication Critical patent/WO1991009395A1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
    • H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
    • H04N3/12—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by switched stationary formation of lamps, photocells or light relays
    • H04N3/127—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by switched stationary formation of lamps, photocells or light relays using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof

Definitions

  • Circuit arrangement for driving a liquid crystal display device with picture elements arranged in a grid
  • the invention relates to a circuit arrangement according to the type of the main claim.
  • Liquid crystal display devices in which the picture elements are arranged in a grid pattern are increasingly being used to reproduce video signals.
  • a considerably more complicated control is required in order to supply the corresponding instantaneous value of the video signal to each picture element. It is therefore for different
  • LCD displays Liquid crystal display devices, hereinafter referred to as LCD displays, have become known as integrated control circuits (controllers).
  • a control circuit of this Art is offered by Hitachi under the type designation HD 66840 and is designed to control TFT displays (thin film transistor displays).
  • Integrated control circuits for LCD displays are supplied with video signals - in the case of color reproduction, the color value signals R, G, B.
  • the control circuit requires horizontal-frequency and vertical-frequency synchronous pulses. Both can be supplied, for example, from a graphics card (for example EGA) from a personal computer.
  • the control circuit also requires a clock signal (hereinafter referred to as the system clock) and a timing signal which essentially defines the beginning of each line and the picture.
  • the object of the present invention is to provide a circuit arrangement for driving a liquid crystal display device, in which the system clock and the timing signal are generated in such a way that a constant, image-correct position of the image on the LCD display is ensured.
  • the circuit arrangement according to the invention with the characterizing features of the main claim has the advantage that a system clock and a timing signal can be derived with little effort.
  • Fig. 1 is a block diagram of the embodiment
  • Embodiment according to FIG. 1 occurring signals.
  • an LCD display 1 is connected via a plurality of parallel lines 2 to an integrated control circuit 3, to which a static read-write memory 3 'is assigned for temporary storage.
  • the color value signals R, G and B are fed to this via inputs 4, 5, 6.
  • the control circuit 3 receives horizontal frequencies and vertical frequency synchronizing pulses H, V via inputs 7, 8.
  • a clock signal CLK and a timing control signal DTMG are required to operate the control circuit 3. Both signals are derived using the circuits described below.
  • a controllable oscillator 11 is provided for the clock signal CLK, which oscillates at a frequency of 14.3 MHz.
  • the frequency of the clock signal is controlled with the aid of a control voltage which is generated by a phase comparison circuit 12, to which the horizontal frequency synchronizing pulse H and the output signal of a frequency divider 13 are supplied.
  • the circuits 11, 12 and 13 represent a phase and frequency locked loop (PLL) which causes an integer ratio n between the frequency of the clock signal CLK and the horizontal frequency.
  • the timing control signal DTMG comprises a horizontal frequency component and a vertical frequency component, which are each generated with the aid of an 8-bit down counter 14, 15 and a D flip-flop 16, 17.
  • the counter 14 is clocked with the clock signal CLK, while H pulses are inverted with the aid of an inverter 9 and fed to an input PE.
  • An output TC of the down counter 14 is connected to the clock input CP of the D flip-flop 16, the reset input RD of which receives H pulses.
  • the D input receives operating voltage (logical 1).
  • the output Q of the D flip-flop 16 is connected to a further input TE of the counter 14 and to an input of a non-switching circuit 18, which together with a further inverter 19 forms an switching circuit.
  • the counter 15 and the D flip-flop 17 act together in the same way, the counter 15 being clocked with inverted horizontal-frequency synchronizing pulses H. Inverted vertical frequency synchronizing pulses V are fed to the PE input of the counter 15 with the inverter 10.
  • the counter 14 can be preset to a value Z via inputs PO to P7, for which purpose each of the inputs is connected on the one hand to the operating voltage (logic 1) via a resistor 20 and can be supplied with ground potential via a switch 21.
  • the counter 15 can be preset using the resistors 22 and the switches 23.
  • Integrated counters of the type 74 HC 103 are preferably suitable as counters 14, 15. The generation of the timing control signal DTMG is explained below using the circuit diagram and the timing diagrams shown in FIG. 2.
  • Line a) shows inverted horizontal-frequency synchronizing pulses H
  • line b) the output signal TC of the counter, which assumes the value 0 at the counter reading 0 and the value 1 during all other counter readings.
  • Line c) represents the output signal of the D flip-flop 16.
  • the supply of the output signal of the D flip-flop in the input TE of the counter 14 has the effect that this is released if the value 1 is also supplied to the input PE. This is the case with the trailing edge of the pulse H (highlighted by an arrow in FIG. 2).
  • the counter 14 counts down from the counter reading Z in time with the clock signal CLK.
  • the signal at the output TC jumps to 0 for a period of the clock signal CLK and clocks with the subsequent positive edge (indicated by the arrow) the D flip-flop 16, which thereby has the value at the D input, namely 1 takes over.
  • the input TE also receives the value 1 and blocks the counter until the D flip-flop 16 is reset by the next pulse H.
  • the counter 15 and the D flip-flop 17 are used to generate the vertical frequency component of the timing signal DTMG.
  • the AND combination of the two components creates a signal that assumes the value 1 during the so-called active lines, i.e. if the video signals contain valid information.

Abstract

In a circuit arrangement for controlling a liquid crystal display device with pixels in a grid array, in which video signals (R, G, B) and horizontal and vertical frequency synchronous pulses (H, V) can be supplied to an integrated control circuit, there is a controllable oscillator with a phase comparator circuit and a frequency divider to derive a beat signal. In addition, to the control circuit may be supplied a time control signal (DTMG) which essentially assumes a first logic level during the active lines of the video signal and a second logic level during the horizontal and line frequency synchronous pulses and subsequent predetermined times.

Description

Schaltungsanordnung zur Ansteuerung einer Flüssigkristall-Anzeigevorrichtung mit rasterförmig angeordneten Bildelementen Circuit arrangement for driving a liquid crystal display device with picture elements arranged in a grid
Die Erfindung geht aus von einer Schaltungsanordnung nach der Gattung des Hauptanspruchs.The invention relates to a circuit arrangement according to the type of the main claim.
Zur Wiedergabe von Videosignalen werden in zunehmenden Maße Flüssigkristall-Anzeigevorrichtungen verwendet, bei denen die Bildelemente rasterförmig angeordnet sind. Gegenüber herkömmlichen Bildwiedergaberöhren ist neben anderen an sich bekannten Unterschieden eine erheblich kompliziertere Ansteuerung erforderlich, um jedem Bildelement den entsprechenden Momomentanwert des Videosignals zuzuführen. Es sind daher für verschiedeneLiquid crystal display devices in which the picture elements are arranged in a grid pattern are increasingly being used to reproduce video signals. Compared to conventional picture display tubes, in addition to other differences known per se, a considerably more complicated control is required in order to supply the corresponding instantaneous value of the video signal to each picture element. It is therefore for different
Flüssigkristall-Anzeigevorrichtungen, im folgenden LCD-Displays genannt, integrierte Steuerschaltungen (Controller) bekanntgeworden. Eine Steuerschaltung dieser Art wird unter der Typenbezeichnung HD 66840 von der Firma Hitachi angeboten und ist zur Ansteuerung von TFT-Displays (Thin film transistor displays) ausgelegt.Liquid crystal display devices, hereinafter referred to as LCD displays, have become known as integrated control circuits (controllers). A control circuit of this Art is offered by Hitachi under the type designation HD 66840 and is designed to control TFT displays (thin film transistor displays).
Integrierten Steuerschaltungen für LCD-Displays sind Videosignale zuzuführen - im Falle einer Farbwiedergabe die Farbwertsignale R, G, B. Außerdem benötigt die SteuerSchaltung horizontalfrequente und vertikalfreguente Synchronimpulse. Beides kann beispielsweise von einer Graphikkarte (beispielsweise EGA) eines Personalcomputers zugeführt werden.Integrated control circuits for LCD displays are supplied with video signals - in the case of color reproduction, the color value signals R, G, B. In addition, the control circuit requires horizontal-frequency and vertical-frequency synchronous pulses. Both can be supplied, for example, from a graphics card (for example EGA) from a personal computer.
Die Steuerschaltung benötigt ferner ein Taktsignal (im folgenden Systemtakt genannt) und ein Zeitsteuersignal, das im wesentlichen den Beginn einer jeden Zeile sowie des Bildes festlegt. Aufgabe der vorliegenden Erfindung ist es, eine Schaltungsanordnung zur Ansteuerung einer Flüssigkristall-Anzeigevorrichtung anzugeben, bei welcher der Systemtakt und das Zeitsteuersignal derart erzeugt werden, daß eine konstante bildgenaue Lage des Bildes auf dem LCD-Display sichergestellt ist.The control circuit also requires a clock signal (hereinafter referred to as the system clock) and a timing signal which essentially defines the beginning of each line and the picture. The object of the present invention is to provide a circuit arrangement for driving a liquid crystal display device, in which the system clock and the timing signal are generated in such a way that a constant, image-correct position of the image on the LCD display is ensured.
Die erfindungsgemäße Schaltungsanordnung mit den kennzeichnenden Merkmalen des Hauptanspruchs hat den Vorteil, daß mit geringem Aufwand ein Systemtakt und ein Zeitsteuersignal abgeleitet werden.The circuit arrangement according to the invention with the characterizing features of the main claim has the advantage that a system clock and a timing signal can be derived with little effort.
Durch die in den Unteransprüchen aufgeführten Maßnahmen sind vorteilhafte Weiterbildungen und Verbesserungen der im Hauptanspruch angegebenen Erfindung möglich.Advantageous further developments and improvements of the invention specified in the main claim are possible through the measures listed in the subclaims.
Einige Weiterbildungen ermöglichen in vorteilhafter Weise, daß eine Verschiebung des Bildes sowohl in horizontaler als auch in vertikaler Richtung ebenfalls bildelementgenau möglich ist. Ein Ausführungsbeispiel der Erfindung ist in der Zeichnung anhand mehrerer Figuren dargestellt und in der nachfolgenden Beschreibung näher erläutert. Es zeigt:Some further developments advantageously make it possible for the image to be shifted in the horizontal as well as in the vertical direction with the same precision as the picture element. An embodiment of the invention is shown in the drawing using several figures and explained in more detail in the following description. It shows:
Fig. 1 ein Blockschaltbild des Ausführungsbeispiels undFig. 1 is a block diagram of the embodiment and
Fig. 2 Spannungs-Zeit-Diagramme einiger bei demFig. 2 voltage-time diagrams of some in the
Ausführungsbeispiel gemäß Fig. 1 auftretender Signale.Embodiment according to FIG. 1 occurring signals.
In an sich bekannter Weise ist ein LCD-Display 1 über eine Vielzahl von parallelen Leitungen 2 mit einer integrierten Steuerschaltung 3 verbunden, welcher zur Zwischenspeicherung ein statischer Schreib-Lese-Speicher 3' zugeordnet ist. Dieser werden über Eingänge 4, 5, 6 die Farbwertsignale R, G und B zugeführt. Außerdem erhält die Steuerschaltung 3 über Eingänge 7, 8 horizontalfrequente und vertikalfreguente Synchronimpulse H, V.In a manner known per se, an LCD display 1 is connected via a plurality of parallel lines 2 to an integrated control circuit 3, to which a static read-write memory 3 'is assigned for temporary storage. The color value signals R, G and B are fed to this via inputs 4, 5, 6. In addition, the control circuit 3 receives horizontal frequencies and vertical frequency synchronizing pulses H, V via inputs 7, 8.
Zusätzlich werden zum Betrieb der Steuerschaltung 3 noch ein Taktsignal CLK und ein Zeitsteuersignal DTMG benötigt. Beide Signale werden mit den im folgenden beschriebenen Schaltungen abgeleitet. Für das Taktsignal CLK ist ein steuerbarer Oszillator 11 vorgesehen, der mit einer Frequenz von 14,3 MHz schwingt. Die Frequenz des Taktsignals wird mit Hilfe einer Steuerspannung gesteuert, die von einer Phasenvergleichsschaltung 12 erzeugt wird, welcher der horizontalfrequente Synchronimpuls H und das Ausgangssignal eines Frequenzteilers 13 zugeführt werden. Die Schaltungen 11, 12 und 13 stellen eine Phasen- und Frequenzregelschleife (PLL) dar, die ein ganzzahliges Verhältnis n zwischen der Frequenz des Taktsignals CLK und der Horizontalfrequenz bewirkt. Das Zeitsteuersignal DTMG umfaßt eine horizontalfrequente und eine vertikalfrequente Komponente, die jeweils mit Hilfe eines 8-bit-Abwärtszählers 14, 15 und eines D-Flip-Flops 16, 17 erzeugt werden.In addition, a clock signal CLK and a timing control signal DTMG are required to operate the control circuit 3. Both signals are derived using the circuits described below. A controllable oscillator 11 is provided for the clock signal CLK, which oscillates at a frequency of 14.3 MHz. The frequency of the clock signal is controlled with the aid of a control voltage which is generated by a phase comparison circuit 12, to which the horizontal frequency synchronizing pulse H and the output signal of a frequency divider 13 are supplied. The circuits 11, 12 and 13 represent a phase and frequency locked loop (PLL) which causes an integer ratio n between the frequency of the clock signal CLK and the horizontal frequency. The timing control signal DTMG comprises a horizontal frequency component and a vertical frequency component, which are each generated with the aid of an 8-bit down counter 14, 15 and a D flip-flop 16, 17.
Für die horizontalfrequente Komponente wird der Zähler 14 mit dem Taktsignal CLK getaktet, während H-Impulse mit Hilfe eines Inverters 9 invertiert und einem Eingang PE zugeführt werden. Ein Ausgang TC des Abwärtszählers 14 ist mit dem Takteingang CP des D-Flip-Flops 16 verbunden, dessen Rücksetzeingang RD H-Impulse erhält. Der D-Eingang erhält Betriebsspannung (logisch 1 ) . Der Ausgang Q des D-Flip-Flops 16 ist mit einem weiteren Eingang TE des Zählers 14 und mit einem Eingang einer Nicht-Undschaltung 18 verbunden, welche zusammen mit einem weiteren Inverter 19 eine Undschaltung bildet.For the horizontal frequency component, the counter 14 is clocked with the clock signal CLK, while H pulses are inverted with the aid of an inverter 9 and fed to an input PE. An output TC of the down counter 14 is connected to the clock input CP of the D flip-flop 16, the reset input RD of which receives H pulses. The D input receives operating voltage (logical 1). The output Q of the D flip-flop 16 is connected to a further input TE of the counter 14 and to an input of a non-switching circuit 18, which together with a further inverter 19 forms an switching circuit.
Der Zähler 15 und das D-Flip-Flop 17 wirken in gleicher Weise zusammen, wobei der Zähler 15 mit invertierten horizontalfrequenten Synchronimpulsen H getaktet wird. Dem PE-Eingang des Zählers 15 werden mit dem Inverter 10 invertierte vertikalfrequente Synchronimpulse V zugeführt.The counter 15 and the D flip-flop 17 act together in the same way, the counter 15 being clocked with inverted horizontal-frequency synchronizing pulses H. Inverted vertical frequency synchronizing pulses V are fed to the PE input of the counter 15 with the inverter 10.
Über Eingänge PO bis P7 kann der Zähler 14 auf einen Wert Z voreingestellt werden, wozu jeder der Eingänge einerseits über je einen Widerstand 20 mit Betriebsspannung (logisch 1 ) verbunden ist und über einen Schalter 21 mit Massepotential beaufschlagbar ist. Der Übersichtlichkeit halber sind in der Zeichnung nur zwei Widerstände 20 und zwei Schalter 21 dargestellt. Vorzugsweise eignen sich sogenannte DIP-Schalter, von denen acht Stück in einem Gehäuse erhältlich sind. In gleicher Weise kann der Zähler 15 mit Hilfe der Widerstände 22 und der Schalter 23 voreingestellt werden. Als Zähler 14, 15 eignen sich vorzugsweise integrierte Bausteine vom Typ 74 HC 103. Die Erzeugung des Zeitsteuersignals DTMG wird im folgenden anhand des Schaltbildes und der in Fig. 2 dargestellten Zeitdiagramme erläutert. Dabei sind lediglich die Signale zur Ableitung der horizontalfrequenten Komponente des Zeitsteuersignals DTMG dargestellt. Die vertikalfrequente Komponente wird in entsprechender Weise erzeugt. Zeile a) zeigt invertierte horizontalfrequente Synchronimpulse H, Zeile b) das Ausgangssignal TC des Zählers, das bei dem Zählerstand 0 den Wert 0 und während aller anderen Zählerstände den Wert 1 annimmt. Zeile c) stellt das Ausgangssignal des D-Flip-Flops 16 dar.The counter 14 can be preset to a value Z via inputs PO to P7, for which purpose each of the inputs is connected on the one hand to the operating voltage (logic 1) via a resistor 20 and can be supplied with ground potential via a switch 21. For the sake of clarity, only two resistors 20 and two switches 21 are shown in the drawing. So-called DIP switches are preferred, eight of which are available in one housing. In the same way, the counter 15 can be preset using the resistors 22 and the switches 23. Integrated counters of the type 74 HC 103 are preferably suitable as counters 14, 15. The generation of the timing control signal DTMG is explained below using the circuit diagram and the timing diagrams shown in FIG. 2. Only the signals for deriving the horizontal-frequency component of the time control signal DTMG are shown. The vertical frequency component is generated in a corresponding manner. Line a) shows inverted horizontal-frequency synchronizing pulses H, line b) the output signal TC of the counter, which assumes the value 0 at the counter reading 0 and the value 1 during all other counter readings. Line c) represents the output signal of the D flip-flop 16.
Durch die Vorderflanke eines Impulses H wird das D-Flip-Flop 16 zurückgesetzt (Q = 0). Die Zuführung des Ausgangssignals des D-Flip-Flops im Eingang TE des Zählers 14 bewirkt, daß dieser freigegeben wird, wenn außerdem dem Eingang PE der Wert 1 zugeführt wird. Dieses ist mit der Rückflanke des Impulses H (in Fig. 2 durch einen Pfeil hervorgehoben) der Fall. Von da ab zählt der Zähler 14 im Takt des Taktsignals CLK vom Zählerstand Z abwärts. Ist der Zählerstand 0 erreicht, springt das Signal am Ausgang TC für eine Periodendauer des Taktsignals CLK auf 0 und taktet mit der anschließenden positiven Flanke (durch Pfeil gekennzeichnet) das D-Flip-Flop 16, das dadurch den Wert am D-Eingang, nämlich 1 übernimmt. Dadurch erhält auch der Eingang TE den Wert 1 und sperrt den Zähler, bis durch den nächsten Impuls H das D-Flip-Flop 16 wieder rückgesetzt wird.The D flip-flop 16 is reset by the leading edge of a pulse H (Q = 0). The supply of the output signal of the D flip-flop in the input TE of the counter 14 has the effect that this is released if the value 1 is also supplied to the input PE. This is the case with the trailing edge of the pulse H (highlighted by an arrow in FIG. 2). From then on, the counter 14 counts down from the counter reading Z in time with the clock signal CLK. When the counter reading reaches 0, the signal at the output TC jumps to 0 for a period of the clock signal CLK and clocks with the subsequent positive edge (indicated by the arrow) the D flip-flop 16, which thereby has the value at the D input, namely 1 takes over. As a result, the input TE also receives the value 1 and blocks the counter until the D flip-flop 16 is reset by the next pulse H.
Wie bereits erwähnt, wird mit Hilfe des Zählers 15 und des D-Flip-Flops 17 die vertikalfrequente Komponente des Zeitsteuersignals DTMG erzeugt. Durch die Und-Verknüpfung beider Komponenten entsteht ein Signal, das während der sogenannten aktiven Zeilen den Wert 1 annimmt, wenn also die Videosignale gültige Informationen enthalten. As already mentioned, the counter 15 and the D flip-flop 17 are used to generate the vertical frequency component of the timing signal DTMG. The AND combination of the two components creates a signal that assumes the value 1 during the so-called active lines, i.e. if the video signals contain valid information.

Claims

Ansprüche Expectations
1. Schaltungsanordnung zur Ansteuerung einer Flüssigkristall-Anzeigevorrichtung mit rasterförmig angeordneten Bildelementen, wobei einer integrierten Steuerschaltung Videosignale (R, G, B) und horizontalfrequente und vertikalfrequente Synchronimpulse (H, V) zuführbar sind, dadurch gekennzeichnet, daß zur Ableitung eines Taktsignals ein steuerbarer Oszillator mit einer Phasenvergleichsschaltung und einem Frequenzteiler vorgesehen ist und daß der Steuerschaltung ferner ein Zeitsteuersignal (DTMG) zuführbar ist, welches im wesentlichen während der aktiven Zeilen der Videosignale einen ersten logischen Pegel und während der horizontalfrequenten und zeilenfrequenten Synchronimpulse und daran anschließenden vorgegebenen Zeitabschnitten einen zweiten logischen Pegel annimmt. 1. Circuit arrangement for controlling a liquid crystal display device with grid-like picture elements, an integrated control circuit video signals (R, G, B) and horizontal-frequency and vertical-frequency synchronization pulses (H, V) can be supplied, characterized in that a controllable oscillator for deriving a clock signal is provided with a phase comparison circuit and a frequency divider and that the control circuit can also be supplied with a timing signal (DTMG) which essentially has a first logic level during the active lines of the video signals and a second logic level during the horizontal-frequency and line-frequency sync pulses and subsequent predetermined time periods assumes.
2. Schaltungsanordnung nach Anspruch 1 , dadurch gekennzeichnet, daß die vorgegebenen Zeitabschnitte einstellbar sind.2. Circuit arrangement according to claim 1, characterized in that the predetermined periods are adjustable.
3. Schaltungsanordnung nach Anspruch 1 , dadurch gekennzeichnet, daß zur Ableitung des Zeitsteuersignals ein erster Zähler mit dem Taktsignal und mit dem horizontalfrequenten Synchronimpuls beaufschlagbar ist und ausgangsseitig mit einem ersten Flip-Flop verbunden ist, daß ein zweiter Zähler mit dem horizontalfrequenten Synchronimpuls und dem vertikalfrequenten Synchronimpuls beaufschlagbar ist und ausgangsseitig mit einem zweiten Flip-Flop verbunden ist und daß Ausgangssignale beider Flip-Flops zum Zeitsteuersignal verknüpft werden.3. Circuit arrangement according to claim 1, characterized in that for deriving the time control signal, a first counter with the clock signal and with the horizontal frequency synchronizing pulse can be acted upon and on the output side is connected to a first flip-flop, that a second counter with the horizontal frequency synchronizing pulse and the vertical frequency Synchronization pulse can be acted upon and is connected on the output side to a second flip-flop and that output signals of both flip-flops are combined to form the time control signal.
4. Schaltungsanordnung nach Anspruch 3, dadurch gekennzeichnet, daß das Taktsignal dem Takteingang des ersten Zählers (14) und der horizontalfrequente Synchronimpuls einem Steuereingang (PE) des ersten Zählers (14) zuführbar ist, daß ein Ausgang (TC) des ersten Zählers (14) an den Takteingang (CP) des ersten D-Flip-Flops (16) angeschlossen ist, das vom horizontalfrequenten Synchronimpuls rücksetzbar ist, und daß der Ausgang des ersten D-Flip-Flops (16) mit einem weiteren Steuereingang (TE) des ersten Zählers (14) verbunden ist.4. Circuit arrangement according to claim 3, characterized in that the clock signal to the clock input of the first counter (14) and the horizontal-frequency synchronizing pulse to a control input (PE) of the first counter (14) can be fed in that an output (TC) of the first counter (14 ) is connected to the clock input (CP) of the first D flip-flop (16), which can be reset by the horizontal-frequency synchronizing pulse, and that the output of the first D flip-flop (16) with a further control input (TE) of the first Counter (14) is connected.
5. Schaltungsanordnung nach Anspruch 3, dadurch gekennzeichnet, daß der horizontalfrequente Synchronimpuls dem Takteingang des zweiten Zählers (15) und der vertikalfrequente Synchronimpuls einem Steuereingang (PE) des zweiten Zählers (15) zuführbar ist, daß ein Ausgang (TC) des zweiten Zählers (15) an den Takteingang (CP) des zweiten D-Flip-Flops (17) angeschlossen ist, das vom vertikalfrequenten Synchronimpuls rücksetzbar ist, und daß der Ausgang des zweiten D-Flip-Flops (17) mit einem weiteren Steuereingang (TE) des zweiten Zählers (15) verbunden ist. 5. A circuit arrangement according to claim 3, characterized in that the horizontal frequency synchronizing pulse to the clock input of the second counter (15) and the vertical frequency synchronizing pulse to a control input (PE) of the second counter (15) can be fed in that an output (TC) of the second counter ( 15) is connected to the clock input (CP) of the second D flip-flop (17), which can be reset by the vertical frequency synchronizing pulse, and that the output of the second D flip-flop (17) with a further control input (TE) second counter (15) is connected.
6. Schaltungsanordnung nach Anspruch 3, dadurch gekennzeichnet, daß die Anzahl der Impulse am Takteingang des jeweiligen Zählers von einem Beginn des Zählvorgangs bis zur Abgabe eines Ausgangssignals einstellbar ist.6. Circuit arrangement according to claim 3, characterized in that the number of pulses at the clock input of the respective counter is adjustable from the beginning of the counting process until the output of an output signal.
7. Schaltungsanordnung nach Anspruch 3, dadurch gekennzeichnet, daß die Zähler (14, 16) voreinstellbare Abwärtszähler sind. 7. Circuit arrangement according to claim 3, characterized in that the counters (14, 16) are presettable down counters.
PCT/DE1990/000855 1989-12-09 1990-11-10 Circuit arrangement for controlling a liquid crystal display device with pixels in a grid array WO1991009395A1 (en)

Applications Claiming Priority (2)

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DE3940750A DE3940750A1 (en) 1989-12-09 1989-12-09 CIRCUIT ARRANGEMENT FOR DRIVING A LIQUID CRYSTAL DISPLAY DEVICE WITH GRID-SHAPED IMAGE ELEMENTS
DEP3940750.0 1989-12-09

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WO1991009395A1 true WO1991009395A1 (en) 1991-06-27

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PCT/DE1990/000855 WO1991009395A1 (en) 1989-12-09 1990-11-10 Circuit arrangement for controlling a liquid crystal display device with pixels in a grid array

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Publication number Priority date Publication date Assignee Title
US5854615A (en) * 1996-10-03 1998-12-29 Micron Display Technology, Inc. Matrix addressable display with delay locked loop controller

Citations (2)

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Publication number Priority date Publication date Assignee Title
US4275421A (en) * 1979-02-26 1981-06-23 The United States Of America As Represented By The Secretary Of The Navy LCD controller
JPS60158780A (en) * 1984-01-27 1985-08-20 Sony Corp Display

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4275421A (en) * 1979-02-26 1981-06-23 The United States Of America As Represented By The Secretary Of The Navy LCD controller
JPS60158780A (en) * 1984-01-27 1985-08-20 Sony Corp Display

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Patent Abstracts of Japan, Band 9, Nr., 328 (E-369), 24. Dezember 1985; & JP-A-60158780 (SONY KK) 20. August 1985 *
Society for Information Display - International Symposium, Digest of Technical Papers, Band XVIII, Mai 1987, New Orleans, Louisiana, US, Palisades Institute for Research Services, Inc., (New York, US), A. Kompolt: "Video to LCD interface (VLI) IC converts video signals into signals suitable for LCDs", Seiten 416-418 *

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