WO1991003896A2

WO1991003896A2 - Computer communications system

Info

Publication number: WO1991003896A2
Application number: PCT/GB1990/001386
Authority: WO
Inventors: Nigel Peter Brown; Aaron Michael Turner; Nigel John Halse; Paul Nicholas Williams
Original assignee: Verran Electronics Limited
Priority date: 1989-09-07
Filing date: 1990-09-07
Publication date: 1991-03-21
Also published as: GB8920261D0; AU6332990A; WO1991003896A3

Abstract

A data communications device for communication via the mains wiring (18) of a building comprises an analog PCB (34) and a digital PCB (36). The analog PCB includes a modem (44) including a line driver (48) with a power amplifier (54) that has a high input impedance when receiving, and compensates for different mains impedances when transmitting. The digital PCB (36) includes hardware and algorithms for encrypting the data that is being sent, and decrypting it on receipt. A standard CRC shift register (72) is used to provide pseudo random data for the encryption and decryption. The digital PCB also includes means for varying the size of the packets of frames of data being sent, to maximise the overall transmission rate.

Description

COMPUTER COMMUNICATIONS SYSTEM

The present invention relates to a computer communications system, and particularly although not exclusively to a system for communicating along mains wiring. It also relates to certain aspects of a method of computer communication, and to the encryption of data.

In an office or business or home a need frequently exists to provide communication between computers or computer peripherals situated in various parts of the building. One way of providing this communication is to provide dedicated cabling between all the required points. This is known as hardwiring. It has the advantage that communication may be at high speed, but is frequently unsuitable for reasons of cost. Hard- wiring also has the disadvantage that it is very inflexible: computers or terminals need to be wired up in position and cannot then be moved without very considerable cost.

A second method is to provide a dedicated "ring network". This consists, generally of a ring of screened cable which is wired into the building and is provided with computer access points ("node points") where required. Communication between two computers attached to two of the nodes is as follows: the sending computer transmits the data to be sent to its corresponding node which then converts it to some suitable format and passes it along the ring. To each block of data the node affixes further information, such as the address of the node to which the data is being sent, and a checksum. When the data block reaches the next node along the ring, the address label is read to check whether it is directed to that particular node. If so, the data is accepted, transformed back into a suitable format and passed on to the recipient computer; the receiving node then sends a "data received" signal around the ring which will eventually reach the sending node, confirming that the data have been correctly received. If the data are not addressed to that node they are taken in by the node, regenerated, and passed on (in the same direction) along the ring; the process is then repeated at the next node. If no node accepts the data they are generally allowed to pass around the ring a second time after which, when they return to their sending node, they are stopped and a message is sent back to the user to say that the data, for some reason, have not reached the recipient.

In order to provide a cheaper and more flexible communication system it has previously been proposed to use the mains wiring of a building as the carrier medium. Such an idea has been in use for some time in the field of internal intercom systems. These transmit a signal by impressing an analogue voltage signal upon, for example, the live and neutral wires of the mains wiring which can be picked up anywhere in the building simply by plugging a suitable receiver into any mains socket. Recently a similar system has become available for the transmission of digital computer data in a similar way. It is believed that this system works by impressing a modulated signal onto the live/neutral wires using the method known as frequency-shift keying. This signal can be read by any suitable receiving device (tuned into the correct frequency) which is plugged into the ring main. True networking capability is thus lacking, since individual receivers cannot be independently addressed. However, through the use of several independent frequency-bands several groups of transmitters/receivers may be used at the same time, all those within one band being in communication with each other. It is one of the objects of the present invention at least to alleviate the problems of the prior art.

It is a further object of the present invention to provide a device for communication along mains wiring which is convenient in use and which can be used for communicating between a variety of different hosts.

According to a first aspect of the present invention there is provided a data encryption or decryption device comprising an input register, a cyclic redundancy code (CRC) shift register; an output register; means arranged to load an initial key into the CRC shift register; means to load data to be encrypted or decrypted into the input register, and sequentially out of the input register to form a raw data stream; means for combining sequential bits of the raw data stream with sequential bits derived from one of the stages of the CRC shift register to form an encrypted or decrypted data stream; means for shifting the encrypted or decrypted data stream sequentially through the CRC shift register, so modifying the key; and means for loading the encrypted or decrypted data stream sequentially into the output register.

The invention also extends to a method of data encryption or decryption.

The means for combining may comprise an XOR gate, or a series of devices logically equivalent thereto. There may be selection means for selecting between an encryption mode and a decryption mode in a particularly advantageous embodiment in which both operations are provided for within the same device. The selection means could comprise a multiplexer. A second multiplexer may also be provided, this enabling the device to be operated in addition in a conventional CRC manner, that is to provide a check sum on data which is being passed through it.

The CRC shift register most preferably is 22 bits in length, with the 16th bit being used to provide the pseudo random sequence which is combined with the incoming raw data for decryption or encryption.

To prevent the situation arising in which very short packages or frames of data, for example frames containing a single character generated at typing speed, are always encrypted in the same way, additional pseudo random data values may be incorporated to "pad out" any such short packets. In this way, a succession of frames each containing a single letter will be successively encrypted in different ways.

According to a second aspect of the invention there is provided a method of digital communication over a broadcast medium comprising detecting the amount of noise present on the medium and broadcasting a discrete frame of information, the amount of data within the broadcast frame varying with the detected noise level.

The invention also extends to an apparatus for digital communication over a broadcast medium suitable for carrying out this method.

The "noise" which is detected may, but need not, include data which has been broadcast onto the medium by other units. If they are a plurality of pairs of units on the medium, each pair being differently addressed, it is possible for one of the units of a particular pair to detect the amount of foreign traffic on the medium consisting of frames which are "wrongly addressed", that is frames which are being passed between units of another pair. This information may be used to vary the amount of data in a subsequent broadcast frame in dependence upon the detected foreign traffic level. Under some circumstances, there are regulations which limit the length of time that a single group of transmitters may send a sequential series of frames on to the broadcast medium without a specified gap. The purpose of such regulations is to prevent one group of units from "hogging" the communications medium at the expense of another group of units. This problem can be dealt with in a distributed way by arranging that every unit of a group monitors combined transmissions of that group, and does not exceed the maximum permitted length of time. If, on the other hand, a particular unit in a group wants to transmit a quantity of data, and there is time before the maximum permitted period for that group expires (no other unit in the group also wanting to send data at the same time) , then that unit may send just that amount of data that it is able to fit in within the permitted period. To that end, the amount of data that is transmitted in a frame or frames within that period is varied according to how much time is left, to ensure that the maximum period for the group is not exceeded.

The quantity of noise in the broadcast medium may b e d e t erm i n e d by mo n i t o r i ng th e numb e r o f retransmissions that have to be made , for example because no "acknowledge" signal is received.

According to a third aspect of the invention there is provided a device for digital communications over mains wiring including amplifier means for impressing a signal on the mains wiring when the device is in a transmit mode, and switch means to cause the amplifier to assume a high impedance state, as seen from the mains wiring, when the device is in a receive mode.

The invention also extends to a method of operating a device for digital communications over mains wiring, by causing an amplifier means for impressing a signal on the mains wiring to assume a high impedance state, as seen from the mains wiring, when the device is in a receive mode. Feedback means may be provided to enable the amplifier to compensate for differing mains impedances in the transmit mode. Desirably, when the device is transmitting, the impedance of the unit should be low in relation to the mains impedance. Live/neutral reveral detection means may be provided to detect whether the live and neutral lines of the mains are reversed. The detection means may then either prevent operation of the device, swap back the live and neutral lines, or impress the signal on the neutral/earth pair if the wires are correct, and the live/earth if the live and neutral wires are reversed.

The switch means for causing the amplifier to assume a high impedance state when the device is in the receive mode may act under control of a control signal, the signal being on when the device is transmitting and off when it is receiving, or vice versa.

The device may include interface means via which it can communicate with a host, these interface means being selectable by the user to communicate either serially or in parallel. In this way, a pair of similar devices attached to the mains wiring may be used for communication, for example, from a PC having a parallel interface and a printer having a serial interface.

There may be user-operable switch means for selecting whether the data signal is impressed on the neutral/live pair or the neutral/earth pair. Alternatively, the data signal may be impressed on both at the same time.

The data signal is preferably impressed by means of frequency switch keying (FSK) techniques. With a pair of devices of the present invention, a user is able, without any difficulty, to take data from a computer and transmit it through the AC mains to any peripheral, such as a terminal, a printer or a modem. Provided that the computers and peripherals use either a parallel (Centronics) or a serial (RS232) port as a data connection, the device can make connections regardless of the make, operating system, or type of port. As a result, it is easy to connect a serial printer to the parallel port of a PC. The individual devices are addressable, and each pair of devices connected to the mains for communication therebetween has to be similarly addressed. Thus, a first pair of devices having an address A can communicate with each other, with no interference from a similar pair of devices connected to the same ring main, this pair having a different address B. Pairs of devices having identical addresses can thus communicate with each other, but not with other pairs on the same ring main having other addresses.

Signalling and transmission protocols can easily be taken care of as means may be provided to operate on the incoming and/or outgoing data, for example to convert line feed characters to carriage returns, or vice versa. Alternatively, line feed characters or carriage returns may each separately be converted into a line feed followed by a carriage return.

It is further conceived that the unit can compress data for transmission between units in order to optimise the use of available bandwidth.

By making use of the device of the present invention, users can easily share peripherals between two or more computers. For example, a single laser printer in one room of a building may be shared between two PC's, each in different rooms. The device is provided with an integral power socket into which, for example, a mains plug for a computer may be inserted. Thus, although the device itself takes up one mains socket, a corresponding mains socket is always additionally provided in return. The integral power socket may be modular, so that it can be easily removed and replaced, if necessary, by another type of power socket, for example one appropriate for mains plugs in countries that do not use the three pin socket arrangement of the UK.

The devices of the present invention may be "intelligent", that is they may enable the user to connect computers and computer peripherals, largely regardless of the protocols involved, without having to set up the appropriate protocols on the host computer. There is no need, for example, for a host computer to include a specially-written comms program. While the specific embodiment of the present invention will be described in relation to communications on the mains wiring, the basic principles could also apply to communications on any other type of broadcast medium, for example radio. All that would be needed would be to replace the modem of the device that is described with a suitable radio transmitter/receiver interface. The present invention may be carried into practice in a number of ways and_, one specific device and its method of operation will now be described with reference to the drawings, in which:

Figure 1 is an overview showing how two identical units may communicate via the mains wiring of a building;

Figure 2 is a top level block diagram of a unit embodying the present invention;

Figure 3 is a block diagram of the analog PCB; Figure 4 is a block diagram of the modem;

Figure 5 is a block diagram of the line driver;

Figure 6 is a block diagram of the line amplifier;

Figure 7 is a block diagram of the power amplifier; Figure 8 is a circuit diagram representing a practical realisation of the block diagram of Figure 7;

Figure 9 shows the hardware for data encryption and decryption;

Figure 10 shows a typical frame of data; Figure 11 is a graph illustrating a property of random noise; and

Figures 12A and 12B illustrate transmissions of a sequence of individual frames. 10

The device of the present embodiment (which will be referred to hereafter as "the DataLink") is a computer peripheral that provides for the transfer of data between computers and peripherals via installed mains wiring. DataLinks are intended to be used in pairs, as is shown in Figure 1 of the drawings. Via the intermediary of two DataLinks 10, 12, a host computer or peripheral 14 is enabled to communicate with a host peripheral or computer 16 via mains wiring 18. Typically, one of the hosts will be for example a PC, and the other will be a peripheral such as a printer, terminal or modem. Communications between the host and its respective DataLink are by means of data leads 20, 22, which may for example be the type of lead described in the present applicants' co-pending G.B. patent application entitled "Computer System Interconnection", filed at the U.K. Patent Office on the same day as the present application. Communication between the DataLinks 10, 12 and the mains 18 are by respective standard mains leads 24, 26 which simply plug into mains outlet sockets (not shown) by means of the usual type of mains plug. (In the UK this would be of a three-pin type) .

Data transfer between the hosts 14, 16 may proceed in both directions if necessary, depending of course upon the exact nature of the hosts. Both of the DataLinks 10, 12 may therefore be set up if required to transmit data onto the mains 18 as well as to receive it from the mains. The DataLinks 10 and 12 may be identical, and accordingly only the DataLink 10 will subsequently be described.

A high level box diagram of the DataLink 10 is shown in Figure 2. As will be seen, the mains lead 24 terminates in a standard mains plug 28 by which the DataLink can be connected to the mains 18 both for supply and communication purposes. A optional mains on/off switch 30 is provided on the line 24, as is a further optional mains socket 32, the purpose of which is to allow the apparatus to be used in an environment where mains socket outlets are in limited supply. The provision of the additional mains socket 32 effectively allows the user another outlet into which a computer, for example, may be plugged, even if the only available installed mains socket has been taken up by the DataLink plug 28.

The mains lead 24 is connected to an analog PCB which is the mains-signalling sub-system of the apparatus. When the DataLink 10 is to transmit a signal onto the mains, the analog PCB takes a serial digital data stream as input on the line notSEROUT, and transforms it into an appropriate analog carrier signal which is then injected onto the mains lead 24. An active input on the line MODULATE indicates to the analog PCB that the signal is to be passed to the mains.

The analog PCB similarly detects when a carrier is present on the mains, and it indicates this fact on the line notCARDET. In addition, the detected carrier is transformed into a serial digital data stream, which is then output on the line notSERIN.

The analog to digital and digital to analog transformations are such that, assuming that the mains is free of noise and does not attenuate the transmitted signal, two suitably operated analog PCBs, in separate DataLinks 10, 12, together act as an information- preserving communications system. It should be noted, however, that the analog PCBs in themselves would provide an error-prone communica¬ tions channel, that is, error correction, error recovery and so on are left to a further stage of the apparatus, a digital PCB 36.

The analog PCB 34 is also responsible for generating the DC supply rails, as is evidenced by the GND, +5 Volt, +12 Volt and -12 Volt outputs.

The digital PCB 36 includes a microprocessor, RAM and circuit logic which together provide the necessary control systems which are needed to detect and recover from transmission errors, and to configure the system as a whole as may be required by a specific application. The digital PCB may also be programmed, if desired, to perform operations on the data, for example encrypting it or decrypting it. Additional algorithms could also be used to transform the data in other ways, such as by stripping out bytes or by converting one particular type of byte to another. A practical example of this would be where the user wishes to transform a carriage return character into a line feed character, or vice versa, or perhaps to transform a carriage return or a line feed into a carriage return followed by a line feed. Also the unit may incorporate data compression techniques to reduce the amount of data for transmission over the mains medium.

Data for transmission to or from the host, along with control signals, are passed to and from the digital PCB 36 by means of the data lead 20. An LED PCB 38 is provided, along with corresponding LEDs, to indicate the status of the DataLink to the user. A suitable PCB for this purpose could easily be configured by a skilled man, according to the status information that he requires, and it will not therefore be described further in any greater detail.

Turning now to Figure 3 , there is shown a lower level block diagram of the analog PCB 34 shown in Figure 2. The PCB 34 comprises a power supply unit or PSU 40, a live/neutral reversal detection circuit or LNRD 42 and a modem 44. The PSU sub-system 40 is a standard unit, the purpose of which is simply to provide the DC supply rails and a further output labelled LFCprime, which is also shown in Figure 2. This is simply a low-frequency timing signal derived from the AC mains which is used by other sub-systems of the DataLink. The PSU 40, being essentially a standard item, will not be described in any further detail.

The live/neutral reversal detection circuit or LNRD 42, as its name suggests, determines whether the live and neutral connections of the mains supply have been correctly wired. For many products, a reversal of the live and neutral connections will be of no consequence, and the user may well in fact not know that the building or mains sockets in which he is proposing to use his DataLink has not been properly wired. The correct wiring of the live and neutral connections is, however, important to the operation of the DataLink since, as will be explained in more detail below, it has the capability of communicating with a like DataLink over either the live and neutral pair or the neutral and earth pair. Also, communication by the DataLink over incorrectly wired mains could cause excessive earth leakage currents.

If the DataLink is configured to communicate over the neutral and earth pair, and the live and neutral connections have been reversed, then it would obviously actually be communicating over the live and earth pair. By injecting a signal along this path, the DataLink would effectively be creating a current flow between the live and earth wires. This current flow would almost certainly exceed the maximum value of 0.7 A which is specified by the British Standards Institute BS415 Standard. In order to avoid this, the LNRD circuit 42 detects whether the live and neutral connections have been reversed and, if so, takes remedial action.

In one specific embodiment of the LNRD circuit 42, the line Nprime is connected to the neutral line on the mains only if the signal level on the neutral line does not exceed +V or -V. +V and -V may be any suitable voltages, such as +15 Volts and -15 Volts respectively. In this way, a signal can be sent to or received from the neutral line only if the live and neutral wires are properly connected. Otherwise, a relay (not shown) breaks the connection. Accordingly, if the wires have been wrongly connected, then the apparatus will not work at all. Suitable control LEDs on the LED PCB 38

(Figure 2) may be provided to indicate this condition.

In a further embodiment the LNRD circuit 42 may include means (not shown) , for example relays, to connect the line Nprime to the correct mains wire. Thus, if live and neutral are reversed, Nprime would be connected to live, and if they are wired correctly then it would be connected to neutral. In an alternative embodiment switching means (not shown) , for example relays, may be provided to un- reverse the live and neutral lines, if they are found to be incorrectly wired. The mains-signalling functions of the analog PCB 34 are carried out by a modem 44, which will be described below in further detail with reference to Figure 4. As can be seen, the modem 44 is effectively connected directly to the live and earth lines of the mains, and is connected to the neutral line via the LNRD circuit 42 and the line Nprime.

Figure 4 illustrates the modem 44 in more detail. The modem consists of two main parts, a thick-film hybrid or TFH 46 and a line driver 48. The TFH performs the digital to analog transformation on notSEROUT (giving LINESIGOUT when MODULATE is active) , and the analog to digital transformation on LINESIGIN (giving notSERIN) . When MODULATE is inactive, no signal appears on LINESIGOUT. The TFH 46 also generates notCARDET and, incidentally, in the specific implementation generates the +12 Volt supply rail for use by other sub-systems. The TFH is implemented using techniques which are well known to the man skilled in the art, and hence will not be described in any greater detail.

The line driver sub-system 48 will now be described further with reference to Figure 5. The driver essentially comprises a line amplifier 50 which places the signal onto the mains lead 24 via a line interface circuit 52. The connection between the line amplifier 50 and the line interface 52 is by way of a signal line LINESIGOUT5.

When the MODULATE line is active, the line amplifier 50 amplifies the input signal on LINESIGOUT to give LINESIGOUT5 such that the peak to peak amplitude of LINESIG0UT5 is -almost a constant over a range of characteristic impedances at point A as seen from the line interface 52. The constant may have one or more values depending on the provision of and position of a user-selectable switch (not shown) which acts as a crude 'volume' control. When MODULATE is inactive, the line amplifier 50 appears as a high impedance as seen from point A.

The purpose of the line interface 52 is to inject LINESIGOUT5 onto the mains, and to recover LINESIGIN from the mains. The interface incorporates a user- selectable switch (not shown) to allow selection between live/neutral and neutral/earth communication. Alternatively, the user-operable switch could be replaced by suitable detection means (not shown) which would select the most suitable path automatically. In some circumstances, even communication along the live/ earth path might not be out of the question.

Alternatively, the apparatus could be arranged to transmit simultaneously over more than one path, for instance over the live/neutral and neutral/earth paths. This could be achieved by the use of two separate signal transformers to give isolation between the live and earth lines; alternatively, a centre-tapped transformer could be used. _ Where simultaneous transmission is provided for, disabling means (not shown) may be provided to enable the user the option of disabling any path if so desired. This may be necessary if a problem is encountered with one path in a given installation or environment.

If the characteristic impedance of the selected mains path as seen from the line interface 52 varies, then the characteristic impedance of the line interface as seen from point A may also vary, although not necessarilv in direct proportion. The line interface 52 itself simply comprises a signal transformer and a capacitor. It is only by having such a simple interface stage that the overall performance of the line driver 48 can be achieved, allowing the line amplifier 50 to be closely coupled to the mains, thus allowing the line amp to compensate for the mains impedance.

The line amplifier 50 will now be considered with reference to Figure 6. The line amplifier consists of three separate components: a power amplifier 54, a gain control circuit 56, and an op-amp supply regulator 58. The last of these is a very simple circuit which generates clean supply rails +REG and -REG from +V, -V, +12 V and -12 V. The gain control circuit incorporates the gain switch, which has previously been referred to; if the gain switch is in one position, the circuit amplifies LINESIGOUT to give LINESIGOUT2, which is passed to the power amplifier 54, and if the gain switch is in the other position the LINESIGOUT input is not amplified. In practice the gain switch may be used to select two (or more) different amplification factors since it may be desirable that LINESIGOUT is amplified even if the gain switch is in its basic setting. The power amplifier circuit 54 is more complicated: its purpose is to provide an amplified version of LINESIG0UT2, as LINESIGOUT5, for transmission onto the selected mains path. The overall gain is almost constant, at approximately 4, over a range of characteristic impedances at point A as seen from the power amplifier. When MODULATE is inactive, the power amplifier appears as a high impedance as seen from point A.

Figure 7 is a block diagram which will be useful in understanding the operation of the power amplifier 54, shown in Figure 6, and Figure 8 shows a practical actual embodiment of the power amplifier 54.

Before describing the power amplifier in greater detail, it may be helpful to review the problem that has to be solved by this amplifier. In any system in which a signal is injected across a pair of mains wires, or several pairs of mains wires, the device, as seen from the mains, will represent a load impedance. If conventional amplifier and interface circuit design techniques were used, then each device would represent a local load on the mains, thereby limiting the range of any transmitted signal. The DataLink device is intended to be operated with several units in close proximity, and attached to the same mains network. A conventional design would therefore impose unacceptable limitations on the performance of a plurality of units. A further problem is that the mains network may represent a unknown or variable load impedance as seen from the DataLink. This could have the effect of attenuating the transmitter carrier by an unknown or variable amount and could cause variance in the amplitude of this signal.

To overcome these problems, the power amplifier 54 of the present embodiment includes a means to tri-state (i.e. put into a high-impedance state) the output stage, and to provide feedback which compensates for mains impedance variations.

As shown in Figure 7, the power amplifier 54 may be conceptualised as including a high gain stage or HGS 60, receiving LINESIGOUT2, a high slew rate amplifier 62, receiving an output from the HGS 60, and a Class B output stage or CBOS 64, receiving an output from the HSRA 62. A feedback path 66 is provided to roll off the amplifier's high frequency response, so reducing the risk of instability and effectively providing compensation including compensation for the mains load impedance variations. On/off control of the amplifier is provided by means of an output disable circuit 68 which receives as an input the MODULATE signal and produces as outputs corresponding signals labelled MOD2, MOD3 and MOD4 which are respectively sent to the HGS 60, the HSRA 62 and the CBOS 64. MOD2, M0D3 and MOD4 are on/off signals, as is MODULATE, but possibly at a different voltage. The CBOS 64 is switched off (thereby tri-stating LINESIGOUT 5) by putting MOD4 inactive and ensuring that LS04 is at a negative voltage. The HSRA is switched off by putting MOD3 inactive, which results in LS04 assuming a negative value. The HGS 60 may oscillate (an undesirable situation) when its input LINESIGOUT 5 is tri-stated. This is prevented by switching off the HGS by putting MOD2 inactive.

The practical embodiment of the power amplifier 54 is shown in Figure 8. In order to be able to impose the required signal onto the mains, via the signal transformer within the line interface 52 (Figure 5) , the power amplifier 54 needs sufficient drive and slew rate. Furthermore, the coupling impedance between the power amplifiers and the line interface 52 needs to be low relative to the expected mains impedance so that the feedback along the line 66 can compensate for the expected varying mains load impedances.

Th e input t o th e p ower amp l i f i e r 5 4 i s LINESIGOUT2 , which may already have been pre-amplif ied by the gain control circuitry 56 , of Figure 6. It is anticipated, however, that this additional gain control could if required be incorporated within the power amplifier itself. The signal is fed to an op-amp 70, embodying the HGS 60. In the conceptual design of Figure 7, the HSRA requires a gain of 4. However, this was not available with the required slew rate using standard FET op-amps, so single transistors have been employed. The amplifier's load impedance is provided by a constant current sink. This is useful for increasing the DC stability of the CBOS stage.

The CBOS stage is embodied, in Figure 8, by a push-pull design. Transistors T-^ and T₂ are the output stage. The amplifier relies on the diodes D-^ and D₂ virtually biasing the transistors T-^ and T₂ into conduction. To do this, D-^ and D₂ need a bias current such that they generate a voltage of two diode drops (approximately 1.2 Volts) across them. This bias current is generated by the current sink T₃. The transistor T₃ is used as a constant current sink both to increase the DC stability of the HSRA and also to bias the diode chain, so enabling the CBOS.

With feedback along the line 66 taken from between the transistors T-^ and T₂, the overall gain of the power amplifier can be selected and therefore controlled by the ratio of the two impedances beta and alpha. By incorporating reactive elements, these impedances can affect the high frequency amplifier roll off, thereby providing greater stability.

When MODULATE is inactive, the power amplifier 54 effectively has to be switched off. An appropriate signal (M0D2) applied at point X provides a small bias current into the op-amp 70 via D₃ and R₂, effectively saturates the op-amp by forcing its output to the negative supply rail, so preventing oscillation when LINESIGOUT 2 or LINESIGOUT 5 are tri-stated or are unknown. The signal MOD3 applied at point Y to the base of the transistor T₄ effectively turns off the HSRA by removing the positive supply to the diode pair D_{l f} D₂ and the HSRA. The signal MOD4 applied at point Z tri-states the Class B amplifier by disabling the current sink: this is achieved by taking the base of transistor T₃ down to the negative rail. That concludes the detailed description of the analog PCB 34. Returning now to Figure 1, some features of the operation of the digital PCB 36 will now be discussed.

To ensure the security of data that is being transmitted through the mains, the DataLink incorporates encryption means within the digital PCB 36. Data to be transmitted is first encrypted, using a key derived from user-operable switches (not shown) ; at the other end, the receiving DataLink decrypts the data using the same key. Of course, the switches on the second DataLink are set to ensure that the key is the same as for the first DataLink. In current systems, several encryption techniques may be employed, these techniques being the subject of several respective standards. One method of data encryption is called block encryption. Here, blocks of data typically comprising a plurality of characters (although a block could, in fact, be a single character) are encrypted, block by block, using an appropriate key. One example of such a technique is the encryption standard knov/n as DES (Data Encryption Standard; US National Bureau of Standards, 1977) .

An alternative to this technique is a technique called stream encryption. The fundamental concept of stream encryption is that a block of data is broken into smaller elements (bits or bytes) . At the start of a block the key is initialized as specified by a user. Each element is then individually encrypted using the key, and after encrypting each element the key itself is replaced by a new key which is a function (F) of the previous key and the element just encrypted.

In the present embodiment, the function F is carried out by a mechanism called cyclic redundancy code (or CRC) , which is a technique which is better known for ensuring reliable data transfer within a communications system.

The way in which CRC works is as follows. When data is transferred, a CRC is generated by the transmitting unit using a technique in which the data stream is considered to represent a polynomial with coefficients of O and 1. CRC algorithms then divide this data polynomial by a divisor or generator polynomial to give a remainder polynomial which is the CRC value. This generated CRC value is sent with the data to be transferred, and the receiver checks this against a corresponding CRC value which it calculates itself from the received data. If the two CRC values do not match, then an error has occurred, and corrective action (for example retransmission of the data) may be undertaken.

There are a great many CRC algorithms which have been defined, and some are accepted as standards for specific applications. For the purpose of this general description, individual generator polynomials are not important. One suitable general purpose polynomial, howe"°'- wh.r.h is the preferred polynomial in the present implementation, is x°+x²+x¹³+x²². It has been found that this gives very good overall performance in terms of complexity, error detection and encryption.

Polynomial division is generally carried out by means of a shift register which is designed with exclusive-OR feedback to various stages within the register. This feedback defines the divisor polynomial. Each stage to which feedback is added takes the feedback signal and exclusively OR's it with the output of the previous stage. The exclusive OR output then becomes the input to that stage. Bit 0 (the first stage of the shift register) takes the output of the last stage and exclusively OR's it with the raw data input to form the input to the first stage.

The size of the shift register is defined by the CRC algorithm. The stages to which feedback is taken are obviously determined by the precise polynomial that is to be used. In some cases, a dynamic shift register can be employed which can cater for several polynomials and/or CRC algorithms.

To generate a CRC remainder polynomial, data is shifted into the data register bit-wise. Obviously, upon each clock edge the contents of the shift register change. If we consider only one bit of the shift register, then as the data is shifted through the CRC unit it continually changes and can be viewed as being pseudo-random. Of course, by knowing the value to which the shift register was initially set, and the data which has since passed through it, the value of the bit can be calculated at any point in time. The present applicants have realised that this phenomenon can be exploited for the purpose of data encryption, 24

with the logic normally used for CRC generation being used instead as the source of pseudo-random data, in other words the function F.

With reference to Figure 9, a particular implementation will now be explained. A CRC shift register, as referred to above, has an input register 74 and an output register 76. A control unit 78 controls data transfer, and may also enable the shift register 72 both to be written to and read from by other parts of the system.

The input register 74, which is one word wide (preferably eight bits) receives the data to be input and this data is serially shifted into the shift register 72 under control of the control unit 78. At the same time, the control logic shifts output data into the output register 76. This register is likewise one word wide (preferably eight bits) . After the whole input word has been shifted into the shift register, the output register will contain a valid word of output data.

The arrangement shown in Figure 9 makes use of a

CRC shift register 72 for encryption and decryption

(ie, the function F) as well as for the usual purpose of generating CRC's in order to check that the data has been transferred properly. To this end, two multiplexers 80, 82 are provided enabling the unit to switch between the three modes, data encryption, data decryption and CRC generation. For all of these modes the CRC shift register remains unchanged, and it is only the external logic which is modified.

To generate a CRC remainder polynomial in the CRC generation mode, the CRC shift register is pre-loaded with a value, either all O's or all l's. The data is then fed through the unit with the multiplexer 82 selecting its input from the input register's serial output data (input 1) .

In the data encryption mode, the CRC shift register is pre-loaded with an encryption key. The data are then shifted through the unit via the multiplexer 82. The multiplexer 82 takes its input from an exclusive OR 84, the inputs to which are the raw data and a line 86 which derives from an inter- mediate stage of the CRC shift register. This line, then, acts as a source of pseudo-random data (the function F) required for stream encryption. Any suitable stage of the shift register could be used for this purpose. Preferably, however, bit 16 of a 22 bit register is used.

It will be appreciated that the consequence of performing an exclusive OR on the raw data and the output from the chosen CRC stage is that the input to the CRC register is effectively pseudo-random, thereby encrypting the data as it is passing. The encrypted data is selected, via the multiplexer 80, to be loaded into the output register ready for reading by the system.

When it is desired to decrypt data, the system is placed in the decryption mode, and the CRC shift register loaded with the encryption key. If the encrypted data is then fed into the unit in the same sequence as it was encrypted, then provided that the encryption and decryption algorithms are the same and the same key is used, the shift register will undergo an identical series of states. Accordingly, the series of pseudo-random data extracted from it will be identical to that extracted during encryption. Therefore, if the encrypted data is fed, via the input register 74, to the unit with the multiplexer 82 selecting its input 1 and the multiplexer 80 selecting its input 2, the output register 76 will be loaded with decrypted data.

A potential problem might arise with this type of data encryption, in that if only a single character is sent in a message over the mains (ie, if there is only a single character is an encryption block) , that character will always be encrypted in the same way. This would therefore enable (or make easier) cracking of encryption by non-authorised people. This is overcome by ensuring that each message (encryption block) that is sent includes at least several bytes. If necessary, some of these bytes may be random data, inserted by the system simply to make up the length of the message. At the other end, these random bytes are decrypted and are thrown away by the receiving DataLink. The purpose of this random data is to randomly jumble the encryption key before any real data is encrypted. This ensures that very short messages, for example messages containing a single character generated at typing speed, are very much harder to decrypt by an intruder. Since the same unit provides encryption, decryption and CRC generation, the CRC algorithm chosen should be one which provides good overall error detection facilities, as well as good encryption. A suitable algorithm for this purpose is the polynomial which has been mentioned above. Since the encryption key is continually modified as the data passes through, a high level of integrity is provided. If a user repeatedly sends an identical sequence of characters between two DataLinks, these characters will be encrypted differently each time as the encryption key effectively changes each time as well. The insertion of random characters into identical single character frames will also avoid each from being encrypted the same. The digital circuit therefore decides when to insert these random characters. It is proposed that it could actually insert a pseudo-random number of pseudo¬ random bytes and it is further proposed that the number of bytes could be coded (in some form) into either the first byte or one byte or some control or header or footer information which will always be transmitted.

In this way the receiver can extract the number of random bytes which it decrypts and then ignores. These bytes must be decrypted in order to ensure correct decryption of the real data: this should be obvious to any person skilled in the technology.

The pseudo-random bytes should be as random and unpredictable as possible. In this way their effect on the encryption key will not be known. It is suggested that by combining (by exclusively OR-ing) various rapidly changing information sources this random data can be generated. Suitable sources of this changing information are high speed counters within the processor and in a baud rate generator for the serial communications (which uses a 20 mHz clock) . It is therefore proposed that the Datalink would exclusively OR words from each of these sources in order to generate the random bytes. A further task of the digital PCB 36 (Figure 1) is to assemble the data that is to be transmitted down the mains into suitably sized packets or frames. Similarly, it has the task of extracting the useful data from a packet or frame which has been received. The principle of bundling data into frames whenever data is to be sent over a broadcast medium (i.e. to which there is a possibility of more than one receiver attached) , or where there is a possibility of transmission errors, is in itself very well known. The digital PCB 36 includes an algorithm to do what is necessary, and it will be evident to a skilled man how to design a unit to do this. In fact, packeting and unpacketing devices are nowadays fairly standard, and commercial products can be obtained that will deal with these functions.

In a typical broadcast situation, both the sender of data and the receiver of data will agree to comply with the same frame-based communications protocol. A typical such protocol will now be described, with reference to Figure 10 which indicates how a single frame may be made up.

The frame shown in Figure 10 consists of a message portion containing the data to be sent, and a control portion. The control portion contains a check sum, a destination address, and two sequence counters. Conventionally, the check sum is sent at the end of the frame, though this is not essential. When a frame is received by a receiver, the check sum is inspected to determine if the frame has been corrupted by noise. If so, the frame is ignored. If the frame appears to be free of errors, and the destination address matches the address of the receiver, then the receiver accepts the data and sends a special acknowledge frame back to the sender. If the sender does not receive an appropriate acknowledge frame within a specified period of time after sending a data frame, then the data frame is retransmitted; this is repeated until an acknowledge frame is received.

The two sequence counters are used to ensure that no possible sequence of intact and corrupted frames (which may include corrupted acknowledge frames) results in any portion of a message being lost, duplicated or accepted out of order.

This basic mechanism works very well, but may still be improved. I the present embodiment, the digital PCB is arranged to vary the size of the frame. Thus, the frame being sent always includes as much data as there is available, up to some limit which we can call M. It will be appreciated that the (fixed size) control information that must be present in each frame, and the short gaps that are necessary between frames, represent a communication overhead. The larger M is, the less significant this overhead becomes, and the greater the actual data throughput of the system. It seems advantageous, therefore, for M to be made as large as possible.

However, if the medium on which the data is to be transferred is subject to noise (as is certainly the case with mains wiring) then larger frames are not always beneficial. Noise may be considered to be a random property of the medium: that is it may occur, or not occur, at any time. Some noise will corrupt a frame and some will not; an instance of noise that is sufficient to corrupt a frame may be called a 'noise event'. For a particular communications medium at a particular time, noise events may be characterised by a graph such as that of Figure 11. It will be obvious that short frames have a better chance of being 30

received than longer frames: for example, if noise events are occurring on average about every 50 milliseconds then it is very unlikely, although not impossible, that a 1 second frame will be received incorrupted. Thus, the overall data transmission rate over the medium will be virtually zero. The transmission rate could, however, be substantially increased if the frame size were to be reduced to something more comparable to the average period between noise events.

By monitoring the number of retransmissions that are necessary over a period of time, the digital PCB 36 estimates the amount of noise that is present on the mains (that is the shape of the graph of Figure 11) , and dynamically adjusts the value of M accordingly. When it appears that the mains are relatively noise- free, M is increased to maximise actual data throughput. When the mains are more noisy, however, actual data throughput is likely to be optimised by reducing M.

An additional possibility would be for the PCB to monitor the number of uncorrupted but inappropriate- addressed frames (that is frames that are intended for some other receiver) that are received over a period of time. This gives a receiving unit an idea of the amount of 'foreign traffic' that is present on the mains.

Where there are a number of pairs of DataLinks on the same mains line, each pair having separate addresses, it is not possible for a unit which wishes to transmit a frame to do so until the line is clear. Thus, if one unit is sending a long frame, then another unit may well have to wait for a significant period of time before it can start sending its own frame. This may result in data that was being received by a user on, say, a terminal to appear 'jumpy'. In some applications, therefore, it may be desirable to reduce the value of M when there appears to be a lot of foreign traffic, so that the resultant smaller frames from different sending units are more finely interleaved. This technique of course reduces overall system throughput during heavy traffic (as there would be proportionately more overhead) , but this may sometimes be less important from a users point of view.

Finally, under some circumstances, for example in some countries, there may be regulations limiting the length of time that a group of sending units may send frames without a specified gap. Examples of such regulations are BS6839 in the U.K., or CENELEC pr EN 50 065 in the EEC. The purpose of such regulations is to prevent one group of units from 'hogging' the mains at the expense of another group of units. Turning now to Figure 12, a sequence of frames 88 bounded by gaps D_{l r} D₂ of at least the specified duration D-_maχ may be referred to as a 'transmission'. If all units measure the length of the inter-frame gaps, then all units will simultaneously detect the start of a new transmission, labelled 90 in Figure 12B. Knowing the maximum allowable transmission time MAXTX and the elapsed time of the transmission in progress ELXTX, each unit will then be able to calculate the maximum allowed duration of any further frames REMTX. From REMTX, a sending unit will be able to determine if there is time, in the current transmission, to send a new frame at all, and if so how long it may be. The sending unit will therefore be able to adjust M 32

accordingly to put the maximum amount of data (subject to the other constraints on data length, mentioned above) in that frame. When a unit determines that REMTX has decreased to zero, then it must not send a new frame until at least the specified time gap D_maχ has elapsed since the end of the transmission.

This algorithm is performed by every unit connected to the mains, that is each unit is autonomous and there is no single master unit governing the behaviour of several slave units.

In the most convenient embodiment, each DataLink operates an algorithm by which the value of M is chosen to be the smallest of the values dictated by the amount of noise present, by the amount of foreign traffic present, and by any applicable regulations.

Claims

CLAIMS :

1. A data encryption or decryption device comprising an input register, a cyclic redundancy code (CRC) shift register; an output register; means arranged to load an initial key into the CRC shift register: means to load data to be encrypted or decrypted into the input register, and sequentially out of the input register to form a raw data stream; means for combining sequential bits of the raw data stream with sequential bits derived from one of the stages of the CRC shift register to form an encrypted or decrypted data stream; means for shifting the encrypted or decrypted data stream sequentially through the CRC shift register, so modifying the key; and means for loading the encrypted or decrypted data stream sequentially into the output register.

2. A device as claimed in Claim 1 in which the means for combining is an XOR gate.

3. A device as claimed in Claim 1 or Claim 2 including selection means for selecting between an encryption mode and a decryption mode.

4. A device as claimed in Claim 3 in which the selection means includes a first multiplexer, the output of which is the data stream which is sequentially loaded through the CRC shift register, a first input thereof being chosen in the decryption mode and a second input in the encryption mode.

SUBSTITUTE SHEET

5. A device as claimed in any one of Claims 1 to 4 including a second multiplexer, the output of which is the data stream which is loaded onto the output register, a first input thereof being chosen in a non encrypting or decrypting mode, and a second input being chosen in an encrypting mode or a decrypting mode.

6. A device as claimed in any one of Claims 1 to 5 in which the CRC shift register has 22 bits.

7. A device as claimed in Claim 6 in which the said stage of the CRC shift register is the 16th bit.

8. A device as claimed in Claim 6 or Claim 7 in which the CRC shift register embodies the polynominal x° + x² + x¹³ + x²².

9. A device as claimed in any one of Claims 1 to 8 including means for dividing the encrypted data into a plurality of individual frames, the encrypted data forming a data field of those frames.

10. A device as claimed in Claim 9 in which the encryption key is altered or scrambled prior to it being used to encrypt the raw data.

11. A device as claimed in Claim 10 in which the encryption key is modified by encrypting an amount of pseudo-random data prior to encrypting the raw data.

12. A device as claimed in Claim 11 where the amount of pseudo-random data is a random amount, the device having means for determining the amount of pseudo-random data in a given frame.

13. A pair of devices, each as claimed in any one of Claims 9 to 12, one encrypting the other decrypting, the two devices being synchronised at the start of each frame to re-load their respective registers with a predefined key.

14. A data encryption or decryption device substantially as specifically described, with reference to figure 9.

15. A method of digital communication over a broadcast medium comprising detecting the amount of noise present on the medium and broadcasting a discrete frame of information, the amount of data within the broadcast frame being a function of the history of the detected noise level.

16. A method as claimed in Claim 16 including detecting the amount of foreign traffic on the medium consisting of frames of the type broadcast but addressed to another unit, and varying the amount of data in a subsequently broadcast frame with the detected traffic level.

17. A method as claimed in Claim 15 or Claim 16 including detecting the start of a transmission comprising a series of sequential frames which is being broadcast on the medium, measuring the elapsed time of the transmission in progress and hence determining, given a maximum allowable transmission length, the maximum allowed duration of any further frame or frames, and varying the amount of data in a subsequently broadcast frame or frames to ensure that they fit within the said maximum allowed duration.

18. A method as claimed in Claim 17 in which the transmission in progress is being transmitted by one unit of a group of like units all arranged to broadcast on the medium, the subsequent broadcast frame or frames being broadcast by a different unit within the group from the said one unit.

19. A method as claimed in any one of Claims 15 to 18 in which the level of noise present on the medium is determined by monitoring the number of retransmissions that are necessary over a period of time.

20. A method of digital communication over a broadcast medium substantially as specifically described, with or without reference to figure 10 and with or without reference to figure 12.

21. A device for digital communications over mains wiring including amplifier means for impressing a signal on the mains wiring when the device is in a transmit mode, and switch means to cause the amplifier to assume a high impedance state, as seen from the mains wiring, when the device is in a receive mode.

22. A device as claimed in Claim 21 including feedback means adapted to enable the amplifier to compensate for differing means impedances in the transit mode.

23. A device as claimed in Claim 21 or Claim 22 including live/neutral reversal detection means adapted to detect whether the live and neutral lines of the mains wiring are reversed.

24. A device as claimed in Claim 23 in which, if reversal is detected, operation of the device is halted.

25. A device as claimed in Claim 23 in which, if reversal is detected, live/neutral switch means act to un-reverse the lines.

26. A device as claimed in Claim 23 in which the signal is impressed on the neutral and earth pair of wires if the live and neutral wires are not reversed, and on the live and earth pair if they are reversed.

27. A device as claimed in any one of Claims 21 to 26 in which the switch means act under control of a control signal, the assertion of which causes the device to adopt the transmit mode, and the non- assertion of which causes it to adopt the receive mode.

28. A device as claimed in any one of Claims 21 to 27 including interface means via which the device can communicate with a host, the interface means allowing at the users selection both parallel and serial communication.

29. A device as claimed in any one of Claims 21 to 27 including encryption means arranged to encrypt outgoing data in the transmit mode, and decryption means arranged to decrypt incoming data in the receive mode.

30. A device as claimed in Claim 29 in which the encryption means and the decryption means comprise stream cypher means.

31. A device as claimed in any one of Claims 21 to 30 including user-operable switch means for selectively impressing the signal either on the live/neutral pair of wires on the mains, or on the earth/neutral pair.

32. A device as claimed in any one of Claims 21 to 30, in which the signal is impressed on both the live/neutral and the earth/neutral pairs of wires on the mains simultaneously.

33. A device as claimed in Claim 23 in which the live/neutral reversal detection means includes means for detecting whether the voltage on the neutral line falls within a defined range.

34. A device as claimed in any one of Claims 21 to 33 including means for dividing data to be transmitted into addressed frames, and means for impressing those frames on the mains wiring.

35. A device as claimed in Claim 34 including means for varying the amount of data in a frame to be transmitted in dependence upon the amount of noise on the mains, or the amount of traffic on the mains.

36. A device as claimed in any one of Claims 21 to 35 in which the signal is impressed on the mains using frequency switch keying.

37. A device for digital communications over mains wiring substantially as specifically described.

38. A device as claimed in Claim 1 or Claim 2 including means for selecting a CRC checksum generating mode.

39. A communications device arranged to measure one or a plurality of characteristics of physical media to be used for communication purposes.

40. A device as claimed in Claim 35 arranged to measure the noise voltage levels on the media.

41. A device as claimed in Claims 35 or Claim 36 arranged to measure the impedances of the media.

42. A device as claimed in any one of Claims 35 to 37 arranged to adjust its transmitter's output signal strength as a result of the measured characteristics.

43. A device as claimed in any one of Claims 35 to 38 arranged to adjust its receiver's input sensitivity as a result of the measured characteristics.

44. A device as claimed in any one of Claims 35 to 39 arranged automatical ly to choose between dif f erent communications media based on their respective measured characteristics.

45. A device as claimed in Claim 40 adapted to choose between Earth and Neutral, and Live and Neutral , on a mains electricity supply.