WO1990001803A1 - Light emitting diode array - Google Patents
Light emitting diode array Download PDFInfo
- Publication number
- WO1990001803A1 WO1990001803A1 PCT/GB1989/000926 GB8900926W WO9001803A1 WO 1990001803 A1 WO1990001803 A1 WO 1990001803A1 GB 8900926 W GB8900926 W GB 8900926W WO 9001803 A1 WO9001803 A1 WO 9001803A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- substrate
- light emitting
- array
- light
- emitting diodes
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars
- H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73257—Bump and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Definitions
- the present invention concerns improvements in or relating to the manufacture of light emitting diode (LED) arrays, more particularly arrays comprised of many close-spaced diode elements.
- LED light emitting diode
- LED arrays made by hybrid techniques are relatively coarse in geometry, it being difficult to achieve a closer pitch than 0.5mm.
- For finer geometry arrays in LED'S it is necessary to fabricate monolithic structures but this presents difficulties in addressing, since without specialized isolation techniques all the LED's in a monolithic structure have a common cathode and require individual connections.
- For fine geometries and for large numbers of pixels interconnection by conventional wirebonding is quite impracticable.
- the present invention is intended to provide a remedy and thus enables the provision of an array of close-spaced elements complete with connections to LED driver circuitry .
- the solution to the aforesaid problem is based upon: a) the fabrication of the LED array in a material with a transparent substrate so that the array can be viewed from the reverse side; and b ) making the interconnections to the array by 'flip- chipping' the array directly onto the silicon driving circuitry.
- a light emitting diode array comprising an optically transparent substrate (1) of semiconductor material in which a multiplicity of light emitting diodes (10) are defined on one surface of the substrate, each of said diodes (10) having an electrical contact (4) on one surface of the substrate, said substrate (1) being provided with a common electrode of an optically transparent material for all the diodes (10).
- a further substrate (6) in which a multiplicity of driver circuits are defined corresponding to the number and positions of the light emitting diodes 10 on the substrate (1 ), each driver circuit having a corresponding contact and wherein the contacts of the light emitting diodes and the corresponding contacts of the driver circuits are in alignment and in electrical soldered contact.
- a method of manufacturing a light emitting diode arriv which comprises providing a semiconductor substrate ( 1 ) of o ⁇ iealiv transparent material having a multiplicity of light emitting diodes (10).
- each diode having an electrical contact (4) on one surface of the substrate, providing a further substrate (6) in which a multiplicity of contacts are defined corresponding to the number and positions of the light emitting diodes (10) on the substrate (1 ).
- LED performance In conventional fine geometry LED structures driver at high current densities, current crowding effects result in much of the light being generated underneath the contact area. With the flip-chip approach the diode is viewed from the reverse side, and all the emitting area is visible with a consequent increase in device efficiency. Improved diode performance also will result from better heat-sinking .
- LED's would be fabricated in a 100x100 array by standard diffusion techniques in GaAsP on GaP. The light-emitting region is nitrogen doped, and the emission wavelength is determined by the As/P ratio. The LED's would be (say) 40 micron in diameter and on 80 micron pitch, giving a total chip size of 9mmx9mm.
- Figure 1 shows a side view of a light emitting array embodying the invention
- Figure 2 is a section through the LED array of figure 1 showing the direction of light output from the light emitting diodes of the array;
- Figure 3 shows a single LED of the array shown in figure 1. the single LED being soldered to corresponding contact on an active silicon substrate containing driver circuits;
- Figure 4 shows a part of a two dimensional LED array embodying the invention.
- an array of light-emitting diodes 10 is provided on an optically transparent GaP substrate 1.
- the substrate 1 is formed with a light emitting GaAsP region 2 which is nitrogen doped.
- the emission wavelength of the region 2 is determined by As/P ratio.
- the light emitting diodes are formed on the substrate 1 , forming thereon a layer 3 of Sis N 4 .
- the layer 3 acts as an insulating diffusion barrier.
- the layer 3 is selectively etched at a plurality of predetermined locations on the substrate to provide exposed areas on the substrate for the formation of light emitting diodes 10.
- the number of etched location preferably correspond to the number of light emitting diodes to be provided on the array.
- each etched location has a diameter such as to provide a light-emitting diode having a diameter 40 microns and the distance between the adjacent etched locations is such that an array of diodes 10 having 80 microns pitch is formed as shown in figure 4.
- the light-emitting diodes 10 are formed at the exposed areas of the substrate by diffusion each having a P-n junction.
- a metal contact 4 is thereafter evaporated on each LED in the array.
- the metal contact may be made of material such as aluminium silicon alloy.
- a common electrode of an optical transparent material which may be an N-type contact, is provided on the reverse side of the substrate. This common contact 5 is shown only for illustration purposes in figure 1.
- An integrated circuit chip 6 having a plurality of driver circuits is provided for interconnection of each driver circuit to corresponding light-emitting diode 10.
- the chip 6 includes an active silicon substrate.
- the number of driver circuits on the active silicon substrate correspond to the number of light emitting diodes 10 and the pitch of the driver circuits on the silicon substrate correspond to the pitch of the light-emitting diodes on the substrate 1 , so that each driver circuits can be individually connected to the corresponding light-emitting diode 10 in the array.
- the driver circuits are connected to the light-emitting diodes by flip-chip solder bonding technique.
- Wet-metallisation layers 7 are provided on each light-emitting diode and on each driver circuit and a gauged amount of solder is deposited between the metallisation layers 7 and on refiowing the solder, a bump 8 is formed which connects a light-emitting diode 10 to corresponding driver circuit on the chip 6.
- the advantage of the flip-chipping technique is that the diodes are viewed from the reverse side of the substrate 1, and all the emitting area is visible with a consequent in device efficiency.
Abstract
A close-spaced diode array in which connection to driver circuitry is enabled by application of a flip-chip solder bonding technique. Not only does this allow dense packing, high pixel content to be achieved but has concomitant advantages of increased light efficiency and improved heat sinking.
Description
LIGHT EMITTING DIODE ARRAY
The present invention concerns improvements in or relating to the manufacture of light emitting diode (LED) arrays, more particularly arrays comprised of many close-spaced diode elements.
There are many modern-day applications that require displays having a large number of display elements (pixels) on a fine geometry for use in optical systems. To provide good imagery requires as many as 500x500 pixels but it is possible to produce recognizable pictures with a much lower pixel count. The conventional cathode ray tube (CRT) can give extremely good definition but is bulky and requires high power and high voltages. Alternative display technologies can be more compact but also have their own particular problems. Passive liquid crystal device (LCD ) displays use little power, but can be difficult to address and multiplex and also require back-lighting for use in the dark.
LED arrays made by hybrid techniques are relatively coarse in geometry, it being difficult to achieve a closer pitch than 0.5mm. For finer geometry arrays in LED'S it is necessary to fabricate monolithic structures but this presents difficulties in addressing, since without specialized isolation techniques all the LED's in a monolithic structure have a common cathode and require individual connections. For fine geometries and for large numbers of pixels interconnection by conventional wirebonding is quite impracticable. The present invention is intended to provide a remedy and thus enables the provision of an array of close-spaced elements complete with connections to LED driver circuitry .
The solution to the aforesaid problem is based upon: a) the fabrication of the LED array in a material with a transparent substrate so that the array can be viewed from the reverse side; and b ) making the interconnections to the array by 'flip- chipping' the array directly onto the silicon driving circuitry.
In accordance with a first aspect of this invention there is provided a light emitting diode array comprising an optically transparent substrate (1) of semiconductor material in which a multiplicity of light emitting diodes (10) are defined on one surface of the substrate, each of said diodes (10) having an electrical contact (4) on one surface of the substrate, said substrate (1) being provided with a common electrode of an optically transparent material for all the diodes (10). a further substrate (6) in which a multiplicity of driver circuits are defined corresponding to the number and positions of the light emitting diodes 10 on the substrate (1 ), each driver circuit having a corresponding contact and wherein the contacts of the light emitting diodes and the corresponding contacts of the driver circuits are in alignment and in electrical soldered contact.
In the foregoing array, light is transmitted in all directions from each addressed diode. That light which is transmitted in a reverse direction, that is, into the body of the optically transparent substrate. is used to provide the visual display. In accordance with a second aspect of this invention there is provided a method of manufacturing a light emitting diode arriv. which comprises providing a semiconductor substrate ( 1 ) of oπiealiv
transparent material having a multiplicity of light emitting diodes (10). and a common electrode of an optically transparent material for all of said diodes, each diode having an electrical contact (4) on one surface of the substrate, providing a further substrate (6) in which a multiplicity of contacts are defined corresponding to the number and positions of the light emitting diodes (10) on the substrate (1 ). depositing a gauged amounted of solder upon each contact of at least one of the aforesaid substrates, winging the substrates into surface contact which the electrical contact of each facing and in alignment. and refiowing the solder to form solder bump (8) connecting the light emitting diodes to the corresponding driver circuits.
The foregoing solution has additional advantages in LED performance. In conventional fine geometry LED structures driver at high current densities, current crowding effects result in much of the light being generated underneath the contact area. With the flip-chip approach the diode is viewed from the reverse side, and all the emitting area is visible with a consequent increase in device efficiency. Improved diode performance also will result from better heat-sinking . In an example of the proposed structure, LED's would be fabricated in a 100x100 array by standard diffusion techniques in GaAsP on GaP. The light-emitting region is nitrogen doped, and the emission wavelength is determined by the As/P ratio. The LED's would be (say) 40 micron in diameter and on 80 micron pitch, giving a total chip size of 9mmx9mm. Contact to the diode would be by individual dots completely covering the diffused region. Use of solder-bump technology would then allow contact to a corresponding
geometry silicon driver chip. The silicon driver chip can then control the intensity of each LED in accordance with received data. It can also be used to apply corrections for n on -uniformity in the LED array. The invention will now be further described by way of example with reference to the accompanying drawings:
Figure 1 shows a side view of a light emitting array embodying the invention;
Figure 2 is a section through the LED array of figure 1 showing the direction of light output from the light emitting diodes of the array;
Figure 3 shows a single LED of the array shown in figure 1. the single LED being soldered to corresponding contact on an active silicon substrate containing driver circuits;
Figure 4 shows a part of a two dimensional LED array embodying the invention.
As shown in figures 1 to 3, an array of light-emitting diodes 10 is provided on an optically transparent GaP substrate 1. The substrate 1 is formed with a light emitting GaAsP region 2 which is nitrogen doped. The emission wavelength of the region 2 is determined by As/P ratio.
The light emitting diodes are formed on the substrate 1 ,
forming thereon a layer 3 of Sis N4. The layer 3 acts as an insulating diffusion barrier. The layer 3 is selectively etched at a plurality of predetermined locations on the substrate to provide exposed areas on the substrate for the formation of light emitting diodes 10. The number of etched location preferably correspond to the number of light emitting diodes to be provided on the array. Preferably each
etched location has a diameter such as to provide a light-emitting diode having a diameter 40 microns and the distance between the adjacent etched locations is such that an array of diodes 10 having 80 microns pitch is formed as shown in figure 4. The light-emitting diodes 10 are formed at the exposed areas of the substrate by diffusion each having a P-n junction. A metal contact 4 is thereafter evaporated on each LED in the array. The metal contact may be made of material such as aluminium silicon alloy. For all the light- emitting diodes in the array, a common electrode of an optical transparent material, which may be an N-type contact, is provided on the reverse side of the substrate. This common contact 5 is shown only for illustration purposes in figure 1.
An integrated circuit chip 6 having a plurality of driver circuits is provided for interconnection of each driver circuit to corresponding light-emitting diode 10. The chip 6 includes an active silicon substrate. The number of driver circuits on the active silicon substrate correspond to the number of light emitting diodes 10 and the pitch of the driver circuits on the silicon substrate correspond to the pitch of the light-emitting diodes on the substrate 1 , so that each driver circuits can be individually connected to the corresponding light-emitting diode 10 in the array.
The driver circuits are connected to the light-emitting diodes by flip-chip solder bonding technique. Wet-metallisation layers 7 are provided on each light-emitting diode and on each driver circuit and a gauged amount of solder is deposited between the metallisation layers 7 and on refiowing the solder, a bump 8 is formed which connects a light-emitting diode 10 to corresponding
driver circuit on the chip 6. The advantage of the flip-chipping technique is that the diodes are viewed from the reverse side of the substrate 1, and all the emitting area is visible with a consequent in device efficiency.
Claims
1 . A light emitting diode array comprising an optically transparent substrate (1 ) of semiconductor material in which a multiplicity of light emitting diodes (10) are defined on one surface of the substrate, each of said diodes (10) having an electrical contact (4) on said one surface of the substrate, said substrate (1 ) being provided with a common electrode of an optically transparent material for all the diodes (10), a further substrate (6) in which a multiplicity of driver circuits are defined corresponding to the number and positions of the light emitting diodes 10 on the substrate (1 ), each driver circuit having a corresponding contact and wherein the contacts of the light emitting diodes and the corresponding contacts of the driver circuits are in alignment and in electrical soldered contact.
2. An array as claimed in claim 1 , in which said substrate ( 1 ; is GaP substrate (1 ).
3. An array as claimed in claimed 2, in which a light-emitting Ga As P region (2) is formed in said substrate (1).
4. An array as claimed in any one of claims 1 to 3, in which the. diameter of each light-emitting diode (10) is 40 microns and the pitch of the light-emitting diodes in said array is 80 microns.
5. An array as claimed in any one of the preceding claims in which said solder contact includes a solder bump (8 ) formed b\ refiowing gauged amount of solder deposited between a light- emitting diode (10) and its corresponding driver circuit.
6. A method of manufacturing a light emitting diode array, which comprises providing a semiconductor substrate (1) of opticalh transparent material having a multiplicity of light emitting diodes (10) and a common electrode of an optically transparent material for all of said diodes, each diode having an electrical contact (4 ) on one surface of the substrate, providing a further substrate (6) in which a multiplicity of driver circuits are defined corresponding to the number and positions of the light emitting diodes (10) on the substrate (1 ), each driver circuit having an electrical contact on one surface of the further substrate, depositing a gauged amounted of solder upon each contact of at least one of the aforesaid substrates. bringing the substrates into surface contact with the electrical contact of each facing and substantially in alignment, and refiowing the solder to form solder bumps (8) connecting the light emitting diodes to the corresponding driver circuits.
7. A method as claimed in claim 6. in which said substrate . I ) is
Ga P substrate having a light emitting Ga As P region (2).
8. A method as claimed in claim 6 and 7, in which the diameter of each light-emitting diode (10) is 40 microns and the pitch of the light-emitting diodes in said array is 80 microns.
9. A method as claimed in any one of claims 6 to 8, in which said light emitting diodes are formed in said substrate by forming an insulating diffusion barrier (3) on a surface of said substrate (1... selectively etching a said barrier at a plurality of locations to provide exposed areas and forming light emitting diode by diffusion in said selectively etched locations.
10. A display unit including an array as claimed in any one of claims 1 to 5 or an array made by the method as claimed in anyone of claims 6 to 9.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP50899789A JPH04501039A (en) | 1989-08-11 | 1989-08-11 | light emitting diode array |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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GB8819070.7 | 1988-08-11 | ||
GB8819070A GB2249428A (en) | 1988-08-11 | 1988-08-11 | Connections for led arrays |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1990001803A1 true WO1990001803A1 (en) | 1990-02-22 |
Family
ID=10641949
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/GB1989/000926 WO1990001803A1 (en) | 1988-08-11 | 1989-08-11 | Light emitting diode array |
Country Status (4)
Country | Link |
---|---|
US (1) | US5060027A (en) |
EP (1) | EP0383889A1 (en) |
GB (1) | GB2249428A (en) |
WO (1) | WO1990001803A1 (en) |
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US9781800B2 (en) | 2015-05-21 | 2017-10-03 | Infineon Technologies Ag | Driving several light sources |
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JPS61198690A (en) * | 1985-02-27 | 1986-09-03 | Oshino Denki Seisakusho:Kk | Light emitting diode display element |
FR2637150B1 (en) * | 1988-09-23 | 1995-07-28 | Neiman Sa | LIGHT EMITTING DIODE ARRAY |
-
1988
- 1988-08-11 GB GB8819070A patent/GB2249428A/en not_active Withdrawn
-
1989
- 1989-08-11 US US07/469,454 patent/US5060027A/en not_active Expired - Fee Related
- 1989-08-11 WO PCT/GB1989/000926 patent/WO1990001803A1/en not_active Application Discontinuation
- 1989-08-11 EP EP89909598A patent/EP0383889A1/en not_active Withdrawn
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US4039890A (en) * | 1974-08-16 | 1977-08-02 | Monsanto Company | Integrated semiconductor light-emitting display array |
Non-Patent Citations (3)
Title |
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IBM Technical Disclosure Bulletin, Vol. 26, No. 2, July 1983 (New York, US), P.E. CADE et al.: "Input/Output Device Interconnections", pages 572-574 * |
Journal of Applied Physics, Vol. 48, No. 1, January 1977, American Institute of Physics (New York, US), M. KITADA: "Upside-Down Fabricated GaP Monolithic Display", pages 279-281 * |
Proceedings of the Society for Information Display, Vol. 18, No. 2, Second Quarter 1977 (Los Angeles, US), M. INOUE et al.: "A GaP Monolithic Numeric Display with Internal Reflection Facets", pages 195-198 * |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0572779A1 (en) * | 1992-06-04 | 1993-12-08 | Motorola, Inc. | Integrated display source with emissive polymers |
US6333522B1 (en) | 1997-01-31 | 2001-12-25 | Matsushita Electric Industrial Co., Ltd. | Light-emitting element, semiconductor light-emitting device, and manufacturing methods therefor |
US6597019B2 (en) | 1997-01-31 | 2003-07-22 | Matsushita Electric Industrial Co., Ltd | Semiconductor light-emitting device comprising an electrostatic protection element |
US6642072B2 (en) | 1997-01-31 | 2003-11-04 | Matsushita Electric Industrial Co., Ltd. | Light-emitting element, semiconductor light-emitting device, and manufacturing methods therefor |
EP2343737A1 (en) * | 2000-07-18 | 2011-07-13 | Sony Corporation | Image display unit and production method for image display unit |
US8409886B2 (en) | 2000-07-18 | 2013-04-02 | Sony Corporation | Method of producing image display unit |
US9781800B2 (en) | 2015-05-21 | 2017-10-03 | Infineon Technologies Ag | Driving several light sources |
US9974130B2 (en) | 2015-05-21 | 2018-05-15 | Infineon Technologies Ag | Driving several light sources |
US10321533B2 (en) | 2015-05-21 | 2019-06-11 | Infineon Technologies Ag | Driving several light sources |
US9918367B1 (en) | 2016-11-18 | 2018-03-13 | Infineon Technologies Ag | Current source regulation |
Also Published As
Publication number | Publication date |
---|---|
US5060027A (en) | 1991-10-22 |
EP0383889A1 (en) | 1990-08-29 |
GB2249428A (en) | 1992-05-06 |
GB8819070D0 (en) | 1988-09-14 |
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