WO1989012911A1

WO1989012911A1 - Protected lead frame and method for fabricating lead frames

Info

Publication number: WO1989012911A1
Application number: PCT/US1989/002741
Authority: WO
Inventors: Michael W. Busby; Richard J. Pommer; Tony K. Johnson; Jeffrey J. Waxweiler; Martin Camen
Original assignee: Unistructure, Inc.
Priority date: 1988-06-24
Filing date: 1989-06-22
Publication date: 1989-12-28
Also published as: IL90601A0

Abstract

An interconnecting circuit for semiconductor and like integrated circuit devices has leads (20) fabricated embedded within a flexible dielectric layer (30) or layers, the leads (20) having inner contact pads (22) or points protruding through to the surface of the dielectric for conductive connection to the semiconductor or integrated circuit chip (46) or device, and outer contact pads (32) or points for conductive connection to next level interconnect circuitry. The leads (20) are fixed in relation to each other and to the lead frame structure. The lead frames (16) are fabricated on a removable substrate (72) by using photoresist and metallization techniques by forming contact pads (70) and posts (74) for one side of the frame (16), forming dielectric layer (76) around the contact pads (72), forming leads (78) in designed conductive contact with the contact pads (70), forming contact pads and posts (86, 88) extending from the opposite sides of the leads (78) for the opposite side of the lead frame (16), and forming a second dielectric layer (76) to cover the leads (78) and to surround the opposing contact pads. A simplified method uses the substrate (72) before final excision, for burn-in testing the lead frame (16) and semiconductor chip assembly before integration into a next level interconnect circuitry. A method describes dynamic testing of the lead frame (16) and chip assembly, and testing environment parameters.

Description

PROTECTED LEAD FRAME AND METHOD FOR FABRICATTxrπ T.TCΛΠ FRAMES

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to the art o semiconductor and like circuit component interconnects, and more particularly to lead frames for interconnecting semiconductor devices and like circuit devices to circuit elements.

Description of the Prior Art

In the past, lead frames have been fabricated to connect semiconductor devices and chips into next level interconnect circuitry. Electrically conductiye leads are bonded at one of their ends to connector points on the semiconductor device. The other ends of the leads are bonded to higher level circuits to interconnect the semiconductor chip to other devices. The leads frequently are formed on a longitudinally extending tape-like carrier having a metallic layer on a flexible insulative layer. The insulative layer has longitudinally spaced apertures, centrally located in frames on the tape. Spaced sets of finger-like leads are formed from the metallic layer, having the inner ends of the leads extending cantilever over a corresponding aperture for connection with a semiconductor device or chip. The aperture is designed so that the leads, when in their originally formed positions, will precisely position over connection points or terminal pads on the semiconductor device or chip. A more detailed description of such a structure may be seen in, for example, United States Patent

No. 3,689,991 issued to Aird.

The finger-like leads are very fine, fragile and delicate, and are formed spaced very close to each other.

In handling prior to connection with a semiconductor chip, the fragile finger leads frequently are bent or are moved or displaced merely with casual contact. Often, the finger leads are bent or displaced in the vertical direction, so that no connection can be made with the semiconductor device. If an effort is made to re-bend or straighten the end of the lead, it will likely break off because it is so fragile. Additionally, when such incorrect connections are made, the fault is not discovered until the chip is assembled and fails in routine testing. The chip must then be discarded. Moreover, the leads, which having a thickness of approximately 0.002 inch, are^' frequently damaged by abrasive contact during handling, resulting in an incomplete lead width, which changes the pre-designed resistance, or in an open circuit. Consequently, there has been little or no testing of lead frames before chip assembly because contact will bend or destroy the leads before connection to the chip.

Methods and apparatus have been suggested in the past to alleviate this problem. For example, it has been suggested to provide a removable but stabilizing connecting frame that interconnects all of the leads. The connecting frame is made from, and indeed is part of, the metallic layer from which the leads are formed. The connecting frame is designed with tear links connecting it to each of the leads so that the frame can be easily removed after the leads are bonded to the connector points or terminal pads of the semiconductor chip. An example of such an apparatus is described in United States Letters Patent No. 4,380,042 to Angelucci, et al.

Another suggestion to resolve the problem has been to provide a flexible tape to support the leads. The leads have terminal points extending through the tape to provide connector points for the semiconductor chip or device. Such a device is described in United States Patent No. 3,868,724 to Perrino. Such solutions appear to help in alleviating the problem. Still, the leads are left exposed to damage by abrasive contact during handling. It is desired to provide a solution to the problem which results in a sturdy lead frame that can withstand reasonably rough treatment, and certainly more than casual contact yet have the leads fixed in their spaced relationships with each other and with the position on the lead frame in which the semiconductor chip is to be placed. It is desired, moreover, to have such sturdy lead frames to allow rapid planar bonding with the semiconductor chip.

Present testing methods and procedures require delicate connections. It is desired to provide test methods and procedures that do not require delicate lead connections that can test the leads of multiple numbers of lead frames simultaneously, and that can test the leads of lead frames while still supported on sturdy substrates or panel boards used in the manufacturing"processes.

It is desired, therefore, to provide a lead frame assembly that can be tested after a semiconductor chip has been assembled to the lead frame.

SUMMARY In brief, in accordance with one aspect of the present invention, a lead frame has leads extending from inner contact pads to outer contact pads and embedded within two layers of a flexible dielectric material. The leads are formed from a thin, generally flexible metal layer, and inner and outer banks or sets of contact pads in the form of posts are fabricated to extend from the leads within the dielectric layers to the corresponding surfaces of the dielectric layers where the contact pads are exposed for conductive contact to semiconductor chips or like devices, or for conductive contact to next level interconnect circuitry. The exposed portions of the contact pads have a gold or gold and copper plating to provide a bump for ready contact with the connected devices or circuitry.

The lead frames can have their centers removed to form an aperture for exposure of the semiconductor chip or device within. Alternatively, the semiconductor chip or device can be positioned on or over the dielectric layer, and the contact points of the chip positioned to conductively connect with the inner contact pads extending through the dielectric layers from the leads. The lead frame is fabricated having a third set of contact pads, each conductively connected through leads within the dielectric layers to the outer contact pads. The third set of contact pads are more spaced apart at their outer ends for connection with test structures.

The lead frames are fabricated using photoresist and additive metallization techniques. A layer of gold is formed on a substrate in designed locations as a conducting protective coating for the posts and contact pads. The contact pads and electrically conductive posts, made mostly of copper, are built up vertically from the substrate. A dielectric layer is formed surrounding the posts and contact pads, to leave the uppermost surface of the posts exposed. It may be necessary to abrade the dielectric layer in order to leave the contact posts exposed for the next operation. The interconnect circuit layer is formed on the ^•dielectric layer using photoresist and additive metallization techniques. Additional posts are built up from the upper surfaces of the leads' ends, opposite the posts built up from the substrate using generally the same photoresist and metallization techniques as used in building the first set of posts. After the posts are built, a second layer of dielectric material is formed to surround the upper posts and to cover the leads. The upper surface of the second layer of the dielectric may need polishing or abrading to expose the upper surfaces of the posts. The posts' upper surfaces can then be plated with copper and gold to form slightly raised bumps as the actual contact pads or points for interconnection with semiconductor chips or next level interconnect circuitry, as the case may be. The brass or other substance substrate can then be removed selectively, leaving that portion of the substrate supporting the third set of contact pads or points. The contact points of the posts exposed on the lower surface can then be built up with copper and gold as a protective coating or as a raise contact bump.

The structure as described can then be tested. Th semiconductor chip contact points are then aligned with th inner contact pads of the embedded leads in the frame an metallurgically bonded. The structure, having the suppor of the substrate at the outermost, third set of contac points, can be inserted or connected into a test device, an the functioning of the semiconductor chip and lead fram assembly can be verified. The embedded lead frame and chi assembly can then be excised and connected with next level interconnect circuitry with confidence that the assembly an its semiconductor chip is functioning.

Other novel features which are believed to b characteristic of the invention, both as to organization an methods of operation, together with further objects and advantages thereof, will be better understood from the

following description in which preferred embodiments of the invention are described by way of example.

Brief Description of the Drawings Fig. 1 is a plan view of a panel of lead frames seen during the fabrication of the preferred embodiment of the invention; Fig. 1A is an enlarged detail of a lead frame of Fig. 1 of the preferred embodiment of the present invention, showing a chip in phantom assembled;

Fig. 2 is a perspective view of a detail of the lead frame of the preferred embodiment of Fig. 1, showing the chip assembled;

Fig. 2A is a side elevational, partial cross-section of the preferred embodiment of the present invention taken along line 2A - 2A in Fig. 2;

Fig. 3 is a perspective view showing prior art lead frame interconnections;

Figs. 4A through 4J are cross-sectional elevation views showing the steps of fabricating the lead frames of the preferred embodiments of Fig. 1 of the present invention;

Fig. 4K is a cross-sectional, elevation view showing a method of assembly for the lead frame of the present invention of Fig. 1 with a chip; and, Fig. 5 is a side elevation, cross-sectional view of an alternative embodiment showing the present invention in a test mode.

Description of the Preferred Embodiments A substantially dielectric panel 10 of lead frame sections 12, comprising lead frames made in accordance with the present invention is shown, reference being had initially to Fig. 1 of the accompanying drawings. Each lead frame section 12 will form a lead frame upon excision of the peripheral material and leads. The portion of the section 12 which will ultimately become the lead frame 16 is generally shown by the boundary 16 in the view of Fig. 1A. Each section 12 on the initial panel 10 has leads 14 connected within the section and extending to the periphery of the panel 10 for insertion into a testing apparatus, as will be described more particularly. The panel 10 may have tractor feed holes, not shown, for prongs on a panel handling machine. Alternatively, not shown, the lead frame sections 12 could be made on a continuous tape, having tractor feed holes for handling. The lead configuration is better seen in Fig. 1A, an enlarged detail of one of the sections 12, and Fig. 2 , an enlarged, partial detail in perspective of a portion of a lead frame of the present invention. Leads 20 conductively connect the inner ends 22 which extend over a semiconductor chip 46. The leads 20 at their inner ends have upper and lower surface contact pads 24, 26, as shown best in Figs. 1A and 2A. The leads 20 are formed within a dielectric layer 30 having surfaces through which the contact pads of the leads are exposed for contact with circuitry. At the outer ends 32 of the leads 20, upper and lower surface contact pads 34, 36 are formed. Leads 14 conductively connect with the leads 20 at their outer ends.32, and extend substantially to the edge of the panel 10.

The inner contact ends 22 of each lead 20, as better seen in Figs. 2 and 2A, is formed by design for conductive bonding or contact with the chip 46. All leads 20 are embedded within the dielectric layer 30. The dielectric layer 30 is shown with a partial cut-away portion in Fig. 2 showing the dielectric layer 31 completely surrounding or enclosing the lead 20. Each inner contact end 22 is comprised of an upper surface contact pad 24 opening through the upper surface of the dielectric layer 30. Similarly, a lower surface contact pad 26 opens through the lower surface of the dielectric layer 30.

Each lead 20 has an outer contact end 32 which also comprises an upper surface contact pad 34 and a lower surface contact pad 36. The upper surface contact pad 34 opens through the upper surface of the dielectric layer 30. The lower surface contact pads 36 open through the lower surface of the dielectric layer 30.

Each of the leads 20 in the lead frame section 12 also has a further 'upper contact pad 40 which may be considered as part of a third set, as partially shown representatively in Fig. 1. Each of the third set of contact pads 40 has an upper contact pad opening through the upper surface of the dielectric layer 30. The third set of contact pads 40 is severed from the rest of its corresponding lead frame section 12 before the lead frame 16 is placed in ultimate use.

The semiconductor device, a chip 46 seen best in Fig. 2A, has contact pads or terminal pads 48 for thermally bonding to the contact pads 26 of the lead frame 16 matching the locations of the pads 48 on the chip 46. Because the leads 20 including the portion connecting the pads 24, 26 are embedded within the dielectric layer 30, the inner ends 22 of the leads 20 cannot move, as has been known in the prior art and shown, for example, in Fig. 3.

In the prior art, frequently, the lead frame is formed into two or more parts comprising an inner frame section 50 and an outer frame section 52. The leads 54, 56 are formed onto the two sections 50, 52, often with portions of the lead unsupported by the frame. The ends 58 of the leads 56 are bonded to corresponding chip contact or terminal pads 60 of the chip 62. However, the end 66 of the lead 54 is bent out of shape and alignment, and cannot be bonded properly, if at all, to its corresponding terminal pad 68. The leads 54, 56 of such prior art devices necessarily must be formed with adequate spacing and distance between them in order to obviate shorting cross-overs and missed connections to the chip 62.

It has been found that the leads 20 can be formed much closer together when embedded within the dielectric layer 30. Such a high pitch for the lead spacing can be especially useful if it is desired to manufacture a chip having closer pitch between its terminal pads, either to manufacture a chip having more terminal pads or connecting

points., or to manufacture a smaller chip having the same number of interconnecting terminal pads.

In operation, a lead frame 16 is fabricated in accordance with a preferred embodiment of the present invention. The space within the sets of inner lead ends 22 may be excised. This space may also remain, as shown in Figs. 1 through 2A, to provide structural support for the lead frame 16 and possibly to provide some protection for the active circuit side of the chip itself. In either circumstance, the leads 20 are embedded within the dielectric layer 30, and will not bend, nor be clipped, severed or otherwise mangled without totally destroying the entire frame itself.

The chip 46 is aligned over the lead frame 16 so that its contact or terminal pads 48 are aligned with the corresponding pads 24, 26 of the inner ends 22 of the leads 20 embedded within the frame's dielectric layer 30, and metallurgically bonded. The third set of contact pads 40 are connected to a test structure for testing the connections of the chip and lead frame assembly.

The lead frame 16 of the present invention may be made by photoresist and additive metallization techniques, reference being had to Figs. 4A to 4F. A layer of copper is laid over the surface of the brass substrate 72. A layer of photoresist is then laid on the copper layer, is exposed and developed in the desired pattern of the inner and outer contact pads. A protective metal 70 such as gold is deposited in the remaining holes of the photoresist pattern. A suitable barrier is then deposited on the pattern of gold contact points or pads 70. Copper posts or vias 74 are then built up from the contact points 70 on the brass substrate 72. The photoresist material is then removed, as seen in Fig. 4A. A layer of dielectric material 76 is laid, as seen in Fig. 4B. The dielectric material may be a polyimide, silicone, epoxy or combination of these or other suitable dielectric materials. A dielectric which cures without stressful procedures is preferred. Thus, a cure which does not require excessive heating or like stresses is preferred. Preferably, the dielectric 76 will result in the least expansive stresses between it and the posts 74, and between it and the leads 78 to be described below.

The dielectric material 76 covering the tops of the posts 74, as indicated in Fig. 4B, is removed by abrading, as shown in Fig. 4C, leaving the posts 74 exposed in the pattern of lower inner and outer pads or contact connections for further contact. An adhesion layer, such as of nickel, and a layer of copper 77 is deposited over the surface. A layer of photoresist 84 is then laid on top of the surface. A pattern of leads 78 for connecting the inner ends 80, the outer ends 82 and corresponding contact pads 94, 104 exposed and developed, leaving depressions where the desired leads 78 should be. Copper is then electroplated into these depressions to form the leads 78, as shown in Fig. 4D, having inner ends 80 and outer ends 82 overlaying in electrically conductive contact with relation to their corresponding posts 74.

An additional layer of photoresist material 84 is deposited over the leads 78 and remaining photoresist of the layer 84. The second layer of the photoresist is exposed and developed to form the pattern defining the locations where additional posts and test pads or contact points are to be formed. These locations are selected to be opposite to the lower inner and lower outer posts 74. Inner posts 86 and outer posts 88 are built up by copper electroplating in the depressions resulting from the photoresist development, which depressions open to the leads 78 at locations on the side of the leads 78 opposite to the lower inner and lower outer posts 74, as seen in Fig. 4E. The photoresist material 84 is then removed from both layers, as indicated in Fig. 4F. The thin, uniform surface metal layer 77 is then etched away from the exposed surfaces to leave the individual circuits.

Referring to Fig. 4G, additional dielectric material 76 is laid over the structure to form a solid mass of dielectric embedding the leads 76 and surrounding the posts 74, 86, 88. The dielectric material over the posts 86, 88 is abraded away to leave the upper surfaces of the posts 86, 88 exposed, as seen in Fig. 4H. The upper surfaces of the posts 86, 88 are built up using additive metallization techniques to form raised bumps, and the exposed surfaces are plated over with gold for protection to complete the inner contact points or pads 92 and the outer contact pads 94, as shown in Fig. 41. The removable brass substrate 72 is also stripped away in a pattern to expose the lower surface of the frame.

The lower contact points, identified in Fig. 4J by the exposed gold layer points 70, are also built up by copper posts or bumps 96 which then are plated over with protective gold layers 98 to form respectively the inner lower surface contact points or pads 100 and the outer lower surface contact points or pads 102. As seen in Fig. 4K, the lead frame 104 is positioned so that corresponding inner lower surface contact pads 100 are aligned over corresponding contact pads or terminal pads 48 of the chip 46. Each of the chip's terminal pads 48 is also built up by a conductive post 106 of copper or gold, and plated over by a protective layer or coat 108 of gold.

In an alternative embodiment of the process, the third set of upper contact pads 40, as seen in Fig. 5, are formed simultaneously with the build up of the leads 20 and the contact pads 32. Individual pads of the third set of contact pads 110 are connected to corresponding leads 20 by formed leads 112, and through conductive posts 114 and contacts surfaces 116. The same dielectric material 30 is formed around and embeds and surrounds the leads 112 and pads 110 as embeds the leads 20 and surrounds the posts 74 and contact pads 34, 36. The contact pads 40 of this third set are used in testing the chip and lead connections before use.

In this embodiment, portions 72' of the brass substrate 12 underlying the third set of contact pads 40 are left in place when the brass substrate 12 is otherwise generally stripped away, as shown in Fig. 5. An edge card connector

120, shown in partial cross-section in Fig. 5, is slipped over the third set of contact pads 40 and over the portion 72' of the brass substrate remaining after the substrate stripping step. The edge card connector 120 has spring biased terminal leads 122 adapted to contact a corresponding surface 116 of a contact pads 40 when lead frame is inserted in the edge card connector. The leads 122 are connected to a test circuit for testing the designed operation of the connected chip and lead assembly.

The circuit connection of the chip and the leads of the assembled lead frame structure can then be tested without destructive contact by the unsupported leads 22 and their outer contact pads 32 with temporary circuits.

Upon successful test results, the chip and lead frame assembly is excised from the remaining third set of contact pads 40, the supporting portion 72' of the brass substrate and the connected edge card connector 120 to result in a fully tested and assembled chip and lead frame. Further, the resulting lead frame and chip assembly has a lead frame which is sturdy, having leads which are and will remain in stable, fixed relation to each other and to the frame. Further, the interconnections between the chip mounted on the frame and the leads of the frame are verified prior to interconnecting the chip and lead frame assembly to the next level interconnection circuit. If a chip to lead frame interconnection is faulty, that fact can be determined and the assembly discarded before the next level interconnection circuit becomes inalterably manufactured and ultimately discarded because of the fault. Alternative testing configurations may be used. For example, lead wires from a test circuit could be soldered or otherwise attached to the contact surfaces 116. In such an arrangement, the lead wires would be removed or separated after testing when the third set of contact pads 40 and the remaining brass substrate 72' are excised.

The foregoing detailed description of my invention and of preferred embodiments, as to products, compositions and processes, is illustrative of specific embodiments only. It is to be understood, however, that additional embodiments may be perceived by those skilled in the art. The embodiments described herein, together with those additional embodiments, are considered to be within the scope of the present invention.

Claims

WE CLAIM:

1. An interconnect circuit for a semiconductor chip comprising substantially solid integral leads ending in attachment pads connectable to electrical circuitry and embedded within a dielectric layer having opposed, substantially parallel surfaces, wherein said attachment pads extend through at least one surface of said dieleGtric layer.

2. The interconnect circuit of Claim 1, wherein said circuit and said dielectric layer are flexible.

3. The interconnect circuit of Claim 1, said attachment pads extend from said leads to each of said surfaces of said dielectric layer.

4. The interconnect circuit of Claim 1, wherein the portion of each of said attachment pads extending through said surface is coated with a conductive and protective bump.

5. The interconnect of Claim 4, wherein said conductive and protective bump has a plating comprising gold thereon.

6. The interconnect of Claim 4, wherein said conductive and protective bump comprises copper.

7. An interconnect lead frame prepared for immediate bonding to a semiconductor chip having leads embedded within a dielectric.

8. The interconnect lead frame of Claim 7, wherein said lead frame is flexible.

9. The interconnect lead frame of Claim 7, wherein said dielectric has at least one surface, and wherein said interconnect further comprises at least one attachment pad conductively connected to each lead frame, said attachment pad having a portion exposed for electrically conductive contact with circuit elements.

10. The interconnect lead frame of Claim 9, further comprising a conductive and protective coating bump formed on said exposed portion of said attachment pad.

11. The interconnect lead frame of Claim 10, wherein said dielectric comprises a second surface, and wherein at least one of said attachment pads has a portion exposed for electrically conductive contact with circuit elements in proximity with said second surface.

12. An interconnect lead frame prepared for immediate bonding to a semiconductor chip having leads permanently fixed in relation to each other and in electrical isolation from each other.

13. The interconnect lead frame of Claim 12, wherein said leads are flexible.

14. The interconnect lead frame of Claim 12, wherein said lead frame comprises a dielectric having at least one surface, and wherein said lead frame further comprises at least one attachment pad conductively connected to each lead frame, said attachment pad having a portion exposed through said dielectric for electrically conductive contact with circuit elements.

15. The interconnect lead frame of Claim 14, further comprising a conductive and protective bump formed on said exposed portion of said attachment pad.

16. The interconnect lead frame of Claim 15, wherein said dielectric comprises a second surface, and wherein at least one of said attachment pads has a portion exposed for electrically conductive contact with circuit elements in proximity with said second surface.

17. A method of fabricating a flexible interconnect layer comprising the steps of: a. forming on a substrate a first set of attachment pads; b. placing a dielectric layer around said first set of attachment pads; c. forming separate electrically conductive leads on said dielectric layer, each of said leads being conductively connected to predetermined pads of said first set of attachment pads; d. forming a second set of attachment pads, each of said pads being conductively connected to at least one predetermined lead; e. placing a second dielectric layer around said 5 second set of attachment pads leaving a portion of each pad of said second set of attachment pads exposed; and, f. removing said substrate to leave a portion of each pad of said first set of attachment pads exposed.

18. The method of Claim 17, wherein in each of said la steps forming a set of attachment pads, an electrically conductive material is formed in a post to form each of said attachment pads, and a protective and conductive bump is formed over the exposed portion of each pad of at least said second set of attachment pads.

15 19. The method of Claim 18, wherein said protective and conductive bump is plated with a thin film comprising gold.

20. The method of Claim 18, wherein a protective coating of metal is formed between said exposed portion of 0 each of said pads of said second set of attachment pads and said protective and conductive bump.

21. The method of Claim 20, wherein said protective coating of metal comprises gold.

22. The method of Clam 17, wherein after the substrate 5 is removed, a protective and conductive bump is formed over the exposed portion of each pad of said first set of attachment pads.

23. The method of Claim 22, wherein said protective and conductive bump is plated with a thin film comprising 0 gold.

24. The method of Claim 22, wherein a protective coating of metal is formed between said exposed portion of each of said pads of said first set of attachment pads and said protective and conductive bump. 5

25. The method of Claim 24, wherein said protective coating of metal comprises gold.

26. The method of Claim 17, wherein in each of said forming steps forming said attachment pads, said attachment pads are formed by photoresist and additive metallization methods.

27. The method of Claim 17, wherein in said first of said forming steps, a layer of photoresist is formed on said substrate, areas representing the locations of the attachment pads of said first set are removed, conductive material is inserted into said areas to form posts, said photoresist is removed from said substrate, a first dielectric layer is formed around said posts to define the first set of attachment pads, and each attachment pad has a surface temporarily exposed to contact leads to be formed.

28. The method of Claim 17, wherein in said second of said forming steps, a layer of photoresist is formed on said first dielectric layer and on leads formed on said first dielectric layer, areas contacting said leads and representing the locations of the attachment pads of said second set are removed, conductive material is inserted into said areas to form posts, said photoresist is removed, and additional dielectric is formed around said posts to define the second set of attachment pads, each attachment pad having a surface exposed through said dielectric.

29. The method of Claim 17, wherein each of said exposed surfaces has any dielectric thereon removed, and a protective and conductive bump is formed on each of said exposed surfaces.

30. The interconnect layer made by the method of Claim 17.